1 /* SPDX-License-Identifier: GPL-2.0+ */
2 /*
3  * Copyright (C) 2011-2014 Panasonic Corporation
4  */
5 
6 #ifndef ARCH_ARM_MPCORE_H
7 #define ARCH_ARM_MPCORE_H
8 
9 /* Snoop Control Unit */
10 #define SCU_OFFSET		0x00
11 
12 /* SCU Control Register */
13 #define SCU_CTRL		0x00
14 #define SCU_ENABLE		(1 << 0)
15 #define SCU_STANDBY_ENABLE	(1 << 5)
16 
17 /* SCU Configuration Register */
18 #define SCU_CONF		0x04
19 /* SCU CPU Power Status Register */
20 #define SCU_PWR_STATUS		0x08
21 /* SCU Invalidate All Registers in Secure State */
22 #define SCU_INV_ALL		0x0C
23 /* SCU Filtering Start Address Register */
24 #define SCU_FILTER_START	0x40
25 /* SCU Filtering End Address Register */
26 #define SCU_FILTER_END		0x44
27 /* SCU Access Control Register */
28 #define SCU_SAC			0x50
29 /* SCU Non-secure Access Control Register */
30 #define SCU_SNSAC		0x54
31 
32 /* Global Timer */
33 #define GLOBAL_TIMER_OFFSET	0x200
34 
35 /* Global Timer Counter Registers */
36 #define GTIMER_CNT_L		0x00
37 #define GTIMER_CNT_H		0x04
38 /* Global Timer Control Register */
39 #define GTIMER_CTRL		0x08
40 /* Global Timer Interrupt Status Register */
41 #define GTIMER_STAT		0x0C
42 /* Comparator Value Registers */
43 #define GTIMER_CMP_L		0x10
44 #define GTIMER_CMP_H		0x14
45 /* Auto-increment Register */
46 #define GTIMER_INC		0x18
47 
48 #endif /* ARCH_ARM_MPCORE_H */
49