1 /*
2  * Copyright (C) 2011-2014 Panasonic Corporation
3  *
4  * SPDX-License-Identifier:	GPL-2.0+
5  */
6 
7 #ifndef ARCH_ARM_MPCORE_H
8 #define ARCH_ARM_MPCORE_H
9 
10 /* Snoop Control Unit */
11 #define SCU_OFFSET		0x00
12 
13 /* SCU Control Register */
14 #define SCU_CTRL		0x00
15 #define SCU_ENABLE		(1 << 0)
16 #define SCU_STANDBY_ENABLE	(1 << 5)
17 
18 /* SCU Configuration Register */
19 #define SCU_CONF		0x04
20 /* SCU CPU Power Status Register */
21 #define SCU_PWR_STATUS		0x08
22 /* SCU Invalidate All Registers in Secure State */
23 #define SCU_INV_ALL		0x0C
24 /* SCU Filtering Start Address Register */
25 #define SCU_FILTER_START	0x40
26 /* SCU Filtering End Address Register */
27 #define SCU_FILTER_END		0x44
28 /* SCU Access Control Register */
29 #define SCU_SAC			0x50
30 /* SCU Non-secure Access Control Register */
31 #define SCU_SNSAC		0x54
32 
33 /* Global Timer */
34 #define GLOBAL_TIMER_OFFSET	0x200
35 
36 /* Global Timer Counter Registers */
37 #define GTIMER_CNT_L		0x00
38 #define GTIMER_CNT_H		0x04
39 /* Global Timer Control Register */
40 #define GTIMER_CTRL		0x08
41 /* Global Timer Interrupt Status Register */
42 #define GTIMER_STAT		0x0C
43 /* Comparator Value Registers */
44 #define GTIMER_CMP_L		0x10
45 #define GTIMER_CMP_H		0x14
46 /* Auto-increment Register */
47 #define GTIMER_INC		0x18
48 
49 #endif /* ARCH_ARM_MPCORE_H */
50