1 /* 2 * Copyright (c) 2010-2014, NVIDIA CORPORATION. All rights reserved. 3 * 4 * This program is free software; you can redistribute it and/or modify it 5 * under the terms and conditions of the GNU General Public License, 6 * version 2, as published by the Free Software Foundation. 7 * 8 * This program is distributed in the hope it will be useful, but WITHOUT 9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 11 * more details. 12 * 13 * You should have received a copy of the GNU General Public License 14 * along with this program. If not, see <http://www.gnu.org/licenses/>. 15 */ 16 17 #include <common.h> 18 #include <asm/io.h> 19 #include <asm/arch/clock.h> 20 #include <asm/arch/flow.h> 21 #include <asm/arch/tegra.h> 22 #include <asm/arch-tegra/clk_rst.h> 23 #include <asm/arch-tegra/pmc.h> 24 #include <asm/arch-tegra/tegra_i2c.h> 25 #include "../cpu.h" 26 27 /* Tegra30-specific CPU init code */ 28 void tegra_i2c_ll_write_addr(uint addr, uint config) 29 { 30 struct i2c_ctlr *reg = (struct i2c_ctlr *)TEGRA_DVC_BASE; 31 32 writel(addr, ®->cmd_addr0); 33 writel(config, ®->cnfg); 34 } 35 36 void tegra_i2c_ll_write_data(uint data, uint config) 37 { 38 struct i2c_ctlr *reg = (struct i2c_ctlr *)TEGRA_DVC_BASE; 39 40 writel(data, ®->cmd_data1); 41 writel(config, ®->cnfg); 42 } 43 44 #define TPS62366A_I2C_ADDR 0xC0 45 #define TPS62366A_SET1_REG 0x01 46 #define TPS62366A_SET1_DATA (0x4600 | TPS62366A_SET1_REG) 47 48 #define TPS62361B_I2C_ADDR 0xC0 49 #define TPS62361B_SET3_REG 0x03 50 #define TPS62361B_SET3_DATA (0x4600 | TPS62361B_SET3_REG) 51 52 #define TPS65911_I2C_ADDR 0x5A 53 #define TPS65911_VDDCTRL_OP_REG 0x28 54 #define TPS65911_VDDCTRL_SR_REG 0x27 55 #define TPS65911_VDDCTRL_OP_DATA (0x2400 | TPS65911_VDDCTRL_OP_REG) 56 #define TPS65911_VDDCTRL_SR_DATA (0x0100 | TPS65911_VDDCTRL_SR_REG) 57 #define I2C_SEND_2_BYTES 0x0A02 58 59 static void enable_cpu_power_rail(void) 60 { 61 struct pmc_ctlr *pmc = (struct pmc_ctlr *)NV_PA_PMC_BASE; 62 u32 reg; 63 64 debug("enable_cpu_power_rail entry\n"); 65 reg = readl(&pmc->pmc_cntrl); 66 reg |= CPUPWRREQ_OE; 67 writel(reg, &pmc->pmc_cntrl); 68 69 /* Set VDD_CORE to 1.200V. */ 70 #ifdef CONFIG_TEGRA_VDD_CORE_TPS62366A_SET1 71 tegra_i2c_ll_write_addr(TPS62366A_I2C_ADDR, 2); 72 tegra_i2c_ll_write_data(TPS62366A_SET1_DATA, I2C_SEND_2_BYTES); 73 #endif 74 #ifdef CONFIG_TEGRA_VDD_CORE_TPS62361B_SET3 75 tegra_i2c_ll_write_addr(TPS62361B_I2C_ADDR, 2); 76 tegra_i2c_ll_write_data(TPS62361B_SET3_DATA, I2C_SEND_2_BYTES); 77 #endif 78 udelay(1000); 79 80 /* 81 * Bring up CPU VDD via the TPS65911x PMIC on the DVC I2C bus. 82 * First set VDD to 1.0125V, then enable the VDD regulator. 83 */ 84 tegra_i2c_ll_write_addr(TPS65911_I2C_ADDR, 2); 85 tegra_i2c_ll_write_data(TPS65911_VDDCTRL_OP_DATA, I2C_SEND_2_BYTES); 86 udelay(1000); 87 tegra_i2c_ll_write_data(TPS65911_VDDCTRL_SR_DATA, I2C_SEND_2_BYTES); 88 udelay(10 * 1000); 89 } 90 91 /** 92 * The T30 requires some special clock initialization, including setting up 93 * the dvc i2c, turning on mselect and selecting the G CPU cluster 94 */ 95 void t30_init_clocks(void) 96 { 97 struct clk_rst_ctlr *clkrst = 98 (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE; 99 struct flow_ctlr *flow = (struct flow_ctlr *)NV_PA_FLOW_BASE; 100 u32 val; 101 102 debug("t30_init_clocks entry\n"); 103 /* Set active CPU cluster to G */ 104 clrbits_le32(flow->cluster_control, 1 << 0); 105 106 writel(SUPER_SCLK_ENB_MASK, &clkrst->crc_super_sclk_div); 107 108 val = (0 << CLK_SYS_RATE_HCLK_DISABLE_SHIFT) | 109 (1 << CLK_SYS_RATE_AHB_RATE_SHIFT) | 110 (0 << CLK_SYS_RATE_PCLK_DISABLE_SHIFT) | 111 (0 << CLK_SYS_RATE_APB_RATE_SHIFT); 112 writel(val, &clkrst->crc_clk_sys_rate); 113 114 /* Put i2c, mselect in reset and enable clocks */ 115 reset_set_enable(PERIPH_ID_DVC_I2C, 1); 116 clock_set_enable(PERIPH_ID_DVC_I2C, 1); 117 reset_set_enable(PERIPH_ID_MSELECT, 1); 118 clock_set_enable(PERIPH_ID_MSELECT, 1); 119 120 /* Switch MSELECT clock to PLLP (00) and use a divisor of 2 */ 121 clock_ll_set_source_divisor(PERIPH_ID_MSELECT, 0, 2); 122 123 /* 124 * Our high-level clock routines are not available prior to 125 * relocation. We use the low-level functions which require a 126 * hard-coded divisor. Use CLK_M with divide by (n + 1 = 17) 127 */ 128 clock_ll_set_source_divisor(PERIPH_ID_DVC_I2C, 3, 16); 129 130 /* 131 * Give clocks time to stabilize, then take i2c and mselect out of 132 * reset 133 */ 134 udelay(1000); 135 reset_set_enable(PERIPH_ID_DVC_I2C, 0); 136 reset_set_enable(PERIPH_ID_MSELECT, 0); 137 } 138 139 static void set_cpu_running(int run) 140 { 141 struct flow_ctlr *flow = (struct flow_ctlr *)NV_PA_FLOW_BASE; 142 143 debug("set_cpu_running entry, run = %d\n", run); 144 writel(run ? FLOW_MODE_NONE : FLOW_MODE_STOP, &flow->halt_cpu_events); 145 } 146 147 void start_cpu(u32 reset_vector) 148 { 149 debug("start_cpu entry, reset_vector = %x\n", reset_vector); 150 t30_init_clocks(); 151 152 /* Enable VDD_CPU */ 153 enable_cpu_power_rail(); 154 155 set_cpu_running(0); 156 157 /* Hold the CPUs in reset */ 158 reset_A9_cpu(1); 159 160 /* Disable the CPU clock */ 161 enable_cpu_clock(0); 162 163 /* Enable CoreSight */ 164 clock_enable_coresight(1); 165 166 /* 167 * Set the entry point for CPU execution from reset, 168 * if it's a non-zero value. 169 */ 170 if (reset_vector) 171 writel(reset_vector, EXCEP_VECTOR_CPU_RESET_VECTOR); 172 173 /* Enable the CPU clock */ 174 enable_cpu_clock(1); 175 176 /* If the CPU doesn't already have power, power it up */ 177 powerup_cpu(); 178 179 /* Take the CPU out of reset */ 180 reset_A9_cpu(0); 181 182 set_cpu_running(1); 183 } 184