1 /* 2 * (C) Copyright 2010-2015 3 * NVIDIA Corporation <www.nvidia.com> 4 * 5 * SPDX-License-Identifier: GPL-2.0+ 6 */ 7 8 /* Tegra30 Clock control functions */ 9 10 #include <common.h> 11 #include <errno.h> 12 #include <asm/io.h> 13 #include <asm/arch/clock.h> 14 #include <asm/arch/tegra.h> 15 #include <asm/arch-tegra/clk_rst.h> 16 #include <asm/arch-tegra/timer.h> 17 #include <div64.h> 18 #include <fdtdec.h> 19 20 /* 21 * Clock types that we can use as a source. The Tegra30 has muxes for the 22 * peripheral clocks, and in most cases there are four options for the clock 23 * source. This gives us a clock 'type' and exploits what commonality exists 24 * in the device. 25 * 26 * Letters are obvious, except for T which means CLK_M, and S which means the 27 * clock derived from 32KHz. Beware that CLK_M (also called OSC in the 28 * datasheet) and PLL_M are different things. The former is the basic 29 * clock supplied to the SOC from an external oscillator. The latter is the 30 * memory clock PLL. 31 * 32 * See definitions in clock_id in the header file. 33 */ 34 enum clock_type_id { 35 CLOCK_TYPE_AXPT, /* PLL_A, PLL_X, PLL_P, CLK_M */ 36 CLOCK_TYPE_MCPA, /* and so on */ 37 CLOCK_TYPE_MCPT, 38 CLOCK_TYPE_PCM, 39 CLOCK_TYPE_PCMT, 40 CLOCK_TYPE_PCMT16, 41 CLOCK_TYPE_PDCT, 42 CLOCK_TYPE_ACPT, 43 CLOCK_TYPE_ASPTE, 44 CLOCK_TYPE_PMDACD2T, 45 CLOCK_TYPE_PCST, 46 47 CLOCK_TYPE_COUNT, 48 CLOCK_TYPE_NONE = -1, /* invalid clock type */ 49 }; 50 51 enum { 52 CLOCK_MAX_MUX = 8 /* number of source options for each clock */ 53 }; 54 55 /* 56 * Clock source mux for each clock type. This just converts our enum into 57 * a list of mux sources for use by the code. 58 * 59 * Note: 60 * The extra column in each clock source array is used to store the mask 61 * bits in its register for the source. 62 */ 63 #define CLK(x) CLOCK_ID_ ## x 64 static enum clock_id clock_source[CLOCK_TYPE_COUNT][CLOCK_MAX_MUX+1] = { 65 { CLK(AUDIO), CLK(XCPU), CLK(PERIPH), CLK(OSC), 66 CLK(NONE), CLK(NONE), CLK(NONE), CLK(NONE), 67 MASK_BITS_31_30}, 68 { CLK(MEMORY), CLK(CGENERAL), CLK(PERIPH), CLK(AUDIO), 69 CLK(NONE), CLK(NONE), CLK(NONE), CLK(NONE), 70 MASK_BITS_31_30}, 71 { CLK(MEMORY), CLK(CGENERAL), CLK(PERIPH), CLK(OSC), 72 CLK(NONE), CLK(NONE), CLK(NONE), CLK(NONE), 73 MASK_BITS_31_30}, 74 { CLK(PERIPH), CLK(CGENERAL), CLK(MEMORY), CLK(NONE), 75 CLK(NONE), CLK(NONE), CLK(NONE), CLK(NONE), 76 MASK_BITS_31_30}, 77 { CLK(PERIPH), CLK(CGENERAL), CLK(MEMORY), CLK(OSC), 78 CLK(NONE), CLK(NONE), CLK(NONE), CLK(NONE), 79 MASK_BITS_31_30}, 80 { CLK(PERIPH), CLK(CGENERAL), CLK(MEMORY), CLK(OSC), 81 CLK(NONE), CLK(NONE), CLK(NONE), CLK(NONE), 82 MASK_BITS_31_30}, 83 { CLK(PERIPH), CLK(DISPLAY), CLK(CGENERAL), CLK(OSC), 84 CLK(NONE), CLK(NONE), CLK(NONE), CLK(NONE), 85 MASK_BITS_31_30}, 86 { CLK(AUDIO), CLK(CGENERAL), CLK(PERIPH), CLK(OSC), 87 CLK(NONE), CLK(NONE), CLK(NONE), CLK(NONE), 88 MASK_BITS_31_30}, 89 { CLK(AUDIO), CLK(SFROM32KHZ), CLK(PERIPH), CLK(OSC), 90 CLK(EPCI), CLK(NONE), CLK(NONE), CLK(NONE), 91 MASK_BITS_31_29}, 92 { CLK(PERIPH), CLK(MEMORY), CLK(DISPLAY), CLK(AUDIO), 93 CLK(CGENERAL), CLK(DISPLAY2), CLK(OSC), CLK(NONE), 94 MASK_BITS_31_29}, 95 { CLK(PERIPH), CLK(CGENERAL), CLK(SFROM32KHZ), CLK(OSC), 96 CLK(NONE), CLK(NONE), CLK(NONE), CLK(NONE), 97 MASK_BITS_31_28} 98 }; 99 100 /* 101 * Clock type for each peripheral clock source. We put the name in each 102 * record just so it is easy to match things up 103 */ 104 #define TYPE(name, type) type 105 static enum clock_type_id clock_periph_type[PERIPHC_COUNT] = { 106 /* 0x00 */ 107 TYPE(PERIPHC_I2S1, CLOCK_TYPE_AXPT), 108 TYPE(PERIPHC_I2S2, CLOCK_TYPE_AXPT), 109 TYPE(PERIPHC_SPDIF_OUT, CLOCK_TYPE_AXPT), 110 TYPE(PERIPHC_SPDIF_IN, CLOCK_TYPE_PCM), 111 TYPE(PERIPHC_PWM, CLOCK_TYPE_PCST), /* only PWM uses b29:28 */ 112 TYPE(PERIPHC_NONE, CLOCK_TYPE_NONE), 113 TYPE(PERIPHC_SBC2, CLOCK_TYPE_PCMT), 114 TYPE(PERIPHC_SBC3, CLOCK_TYPE_PCMT), 115 116 /* 0x08 */ 117 TYPE(PERIPHC_NONE, CLOCK_TYPE_NONE), 118 TYPE(PERIPHC_I2C1, CLOCK_TYPE_PCMT16), 119 TYPE(PERIPHC_DVC_I2C, CLOCK_TYPE_PCMT16), 120 TYPE(PERIPHC_NONE, CLOCK_TYPE_NONE), 121 TYPE(PERIPHC_NONE, CLOCK_TYPE_NONE), 122 TYPE(PERIPHC_SBC1, CLOCK_TYPE_PCMT), 123 TYPE(PERIPHC_DISP1, CLOCK_TYPE_PMDACD2T), 124 TYPE(PERIPHC_DISP2, CLOCK_TYPE_PMDACD2T), 125 126 /* 0x10 */ 127 TYPE(PERIPHC_CVE, CLOCK_TYPE_PDCT), 128 TYPE(PERIPHC_NONE, CLOCK_TYPE_NONE), 129 TYPE(PERIPHC_VI, CLOCK_TYPE_MCPA), 130 TYPE(PERIPHC_NONE, CLOCK_TYPE_NONE), 131 TYPE(PERIPHC_SDMMC1, CLOCK_TYPE_PCMT), 132 TYPE(PERIPHC_SDMMC2, CLOCK_TYPE_PCMT), 133 TYPE(PERIPHC_G3D, CLOCK_TYPE_MCPA), 134 TYPE(PERIPHC_G2D, CLOCK_TYPE_MCPA), 135 136 /* 0x18 */ 137 TYPE(PERIPHC_NDFLASH, CLOCK_TYPE_PCMT), 138 TYPE(PERIPHC_SDMMC4, CLOCK_TYPE_PCMT), 139 TYPE(PERIPHC_VFIR, CLOCK_TYPE_PCMT), 140 TYPE(PERIPHC_EPP, CLOCK_TYPE_MCPA), 141 TYPE(PERIPHC_MPE, CLOCK_TYPE_MCPA), 142 TYPE(PERIPHC_MIPI, CLOCK_TYPE_PCMT), /* MIPI base-band HSI */ 143 TYPE(PERIPHC_UART1, CLOCK_TYPE_PCMT), 144 TYPE(PERIPHC_UART2, CLOCK_TYPE_PCMT), 145 146 /* 0x20 */ 147 TYPE(PERIPHC_HOST1X, CLOCK_TYPE_MCPA), 148 TYPE(PERIPHC_NONE, CLOCK_TYPE_NONE), 149 TYPE(PERIPHC_TVO, CLOCK_TYPE_PDCT), 150 TYPE(PERIPHC_HDMI, CLOCK_TYPE_PMDACD2T), 151 TYPE(PERIPHC_NONE, CLOCK_TYPE_NONE), 152 TYPE(PERIPHC_TVDAC, CLOCK_TYPE_PDCT), 153 TYPE(PERIPHC_I2C2, CLOCK_TYPE_PCMT16), 154 TYPE(PERIPHC_EMC, CLOCK_TYPE_MCPT), 155 156 /* 0x28 */ 157 TYPE(PERIPHC_UART3, CLOCK_TYPE_PCMT), 158 TYPE(PERIPHC_NONE, CLOCK_TYPE_NONE), 159 TYPE(PERIPHC_VI, CLOCK_TYPE_MCPA), 160 TYPE(PERIPHC_NONE, CLOCK_TYPE_NONE), 161 TYPE(PERIPHC_NONE, CLOCK_TYPE_NONE), 162 TYPE(PERIPHC_SBC4, CLOCK_TYPE_PCMT), 163 TYPE(PERIPHC_I2C3, CLOCK_TYPE_PCMT16), 164 TYPE(PERIPHC_SDMMC3, CLOCK_TYPE_PCMT), 165 166 /* 0x30 */ 167 TYPE(PERIPHC_UART4, CLOCK_TYPE_PCMT), 168 TYPE(PERIPHC_UART5, CLOCK_TYPE_PCMT), 169 TYPE(PERIPHC_VDE, CLOCK_TYPE_PCMT), 170 TYPE(PERIPHC_OWR, CLOCK_TYPE_PCMT), 171 TYPE(PERIPHC_NOR, CLOCK_TYPE_PCMT), 172 TYPE(PERIPHC_CSITE, CLOCK_TYPE_PCMT), 173 TYPE(PERIPHC_I2S0, CLOCK_TYPE_AXPT), 174 TYPE(PERIPHC_NONE, CLOCK_TYPE_NONE), 175 176 /* 0x38h */ /* Jumps to reg offset 0x3B0h - new for T30 */ 177 TYPE(PERIPHC_G3D2, CLOCK_TYPE_MCPA), 178 TYPE(PERIPHC_MSELECT, CLOCK_TYPE_PCMT), 179 TYPE(PERIPHC_TSENSOR, CLOCK_TYPE_PCST), /* s/b PCTS */ 180 TYPE(PERIPHC_I2S3, CLOCK_TYPE_AXPT), 181 TYPE(PERIPHC_I2S4, CLOCK_TYPE_AXPT), 182 TYPE(PERIPHC_I2C4, CLOCK_TYPE_PCMT16), 183 TYPE(PERIPHC_SBC5, CLOCK_TYPE_PCMT), 184 TYPE(PERIPHC_SBC6, CLOCK_TYPE_PCMT), 185 186 /* 0x40 */ 187 TYPE(PERIPHC_AUDIO, CLOCK_TYPE_ACPT), 188 TYPE(PERIPHC_NONE, CLOCK_TYPE_NONE), 189 TYPE(PERIPHC_DAM0, CLOCK_TYPE_ACPT), 190 TYPE(PERIPHC_DAM1, CLOCK_TYPE_ACPT), 191 TYPE(PERIPHC_DAM2, CLOCK_TYPE_ACPT), 192 TYPE(PERIPHC_HDA2CODEC2X, CLOCK_TYPE_PCMT), 193 TYPE(PERIPHC_ACTMON, CLOCK_TYPE_PCST), /* MASK 31:30 */ 194 TYPE(PERIPHC_EXTPERIPH1, CLOCK_TYPE_ASPTE), 195 196 /* 0x48 */ 197 TYPE(PERIPHC_EXTPERIPH2, CLOCK_TYPE_ASPTE), 198 TYPE(PERIPHC_EXTPERIPH3, CLOCK_TYPE_ASPTE), 199 TYPE(PERIPHC_NANDSPEED, CLOCK_TYPE_PCMT), 200 TYPE(PERIPHC_I2CSLOW, CLOCK_TYPE_PCST), /* MASK 31:30 */ 201 TYPE(PERIPHC_SYS, CLOCK_TYPE_NONE), 202 TYPE(PERIPHC_SPEEDO, CLOCK_TYPE_PCMT), 203 TYPE(PERIPHC_NONE, CLOCK_TYPE_NONE), 204 TYPE(PERIPHC_NONE, CLOCK_TYPE_NONE), 205 206 /* 0x50 */ 207 TYPE(PERIPHC_NONE, CLOCK_TYPE_NONE), 208 TYPE(PERIPHC_NONE, CLOCK_TYPE_NONE), 209 TYPE(PERIPHC_NONE, CLOCK_TYPE_NONE), 210 TYPE(PERIPHC_NONE, CLOCK_TYPE_NONE), 211 TYPE(PERIPHC_SATAOOB, CLOCK_TYPE_PCMT), /* offset 0x420h */ 212 TYPE(PERIPHC_SATA, CLOCK_TYPE_PCMT), 213 TYPE(PERIPHC_HDA, CLOCK_TYPE_PCMT), 214 }; 215 216 /* 217 * This array translates a periph_id to a periphc_internal_id 218 * 219 * Not present/matched up: 220 * uint vi_sensor; _VI_SENSOR_0, 0x1A8 221 * SPDIF - which is both 0x08 and 0x0c 222 * 223 */ 224 #define NONE(name) (-1) 225 #define OFFSET(name, value) PERIPHC_ ## name 226 static s8 periph_id_to_internal_id[PERIPH_ID_COUNT] = { 227 /* Low word: 31:0 */ 228 NONE(CPU), 229 NONE(COP), 230 NONE(TRIGSYS), 231 NONE(RESERVED3), 232 NONE(RESERVED4), 233 NONE(TMR), 234 PERIPHC_UART1, 235 PERIPHC_UART2, /* and vfir 0x68 */ 236 237 /* 8 */ 238 NONE(GPIO), 239 PERIPHC_SDMMC2, 240 NONE(SPDIF), /* 0x08 and 0x0c, unclear which to use */ 241 PERIPHC_I2S1, 242 PERIPHC_I2C1, 243 PERIPHC_NDFLASH, 244 PERIPHC_SDMMC1, 245 PERIPHC_SDMMC4, 246 247 /* 16 */ 248 NONE(RESERVED16), 249 PERIPHC_PWM, 250 PERIPHC_I2S2, 251 PERIPHC_EPP, 252 PERIPHC_VI, 253 PERIPHC_G2D, 254 NONE(USBD), 255 NONE(ISP), 256 257 /* 24 */ 258 PERIPHC_G3D, 259 NONE(RESERVED25), 260 PERIPHC_DISP2, 261 PERIPHC_DISP1, 262 PERIPHC_HOST1X, 263 NONE(VCP), 264 PERIPHC_I2S0, 265 NONE(CACHE2), 266 267 /* Middle word: 63:32 */ 268 NONE(MEM), 269 NONE(AHBDMA), 270 NONE(APBDMA), 271 NONE(RESERVED35), 272 NONE(RESERVED36), 273 NONE(STAT_MON), 274 NONE(RESERVED38), 275 NONE(RESERVED39), 276 277 /* 40 */ 278 NONE(KFUSE), 279 PERIPHC_SBC1, 280 PERIPHC_NOR, 281 NONE(RESERVED43), 282 PERIPHC_SBC2, 283 NONE(RESERVED45), 284 PERIPHC_SBC3, 285 PERIPHC_DVC_I2C, 286 287 /* 48 */ 288 NONE(DSI), 289 PERIPHC_TVO, /* also CVE 0x40 */ 290 PERIPHC_MIPI, 291 PERIPHC_HDMI, 292 NONE(CSI), 293 PERIPHC_TVDAC, 294 PERIPHC_I2C2, 295 PERIPHC_UART3, 296 297 /* 56 */ 298 NONE(RESERVED56), 299 PERIPHC_EMC, 300 NONE(USB2), 301 NONE(USB3), 302 PERIPHC_MPE, 303 PERIPHC_VDE, 304 NONE(BSEA), 305 NONE(BSEV), 306 307 /* Upper word 95:64 */ 308 PERIPHC_SPEEDO, 309 PERIPHC_UART4, 310 PERIPHC_UART5, 311 PERIPHC_I2C3, 312 PERIPHC_SBC4, 313 PERIPHC_SDMMC3, 314 NONE(PCIE), 315 PERIPHC_OWR, 316 317 /* 72 */ 318 NONE(AFI), 319 PERIPHC_CSITE, 320 NONE(PCIEXCLK), 321 NONE(AVPUCQ), 322 NONE(RESERVED76), 323 NONE(RESERVED77), 324 NONE(RESERVED78), 325 NONE(DTV), 326 327 /* 80 */ 328 PERIPHC_NANDSPEED, 329 PERIPHC_I2CSLOW, 330 NONE(DSIB), 331 NONE(RESERVED83), 332 NONE(IRAMA), 333 NONE(IRAMB), 334 NONE(IRAMC), 335 NONE(IRAMD), 336 337 /* 88 */ 338 NONE(CRAM2), 339 NONE(RESERVED89), 340 NONE(MDOUBLER), 341 NONE(RESERVED91), 342 NONE(SUSOUT), 343 NONE(RESERVED93), 344 NONE(RESERVED94), 345 NONE(RESERVED95), 346 347 /* V word: 31:0 */ 348 NONE(CPUG), 349 NONE(CPULP), 350 PERIPHC_G3D2, 351 PERIPHC_MSELECT, 352 PERIPHC_TSENSOR, 353 PERIPHC_I2S3, 354 PERIPHC_I2S4, 355 PERIPHC_I2C4, 356 357 /* 08 */ 358 PERIPHC_SBC5, 359 PERIPHC_SBC6, 360 PERIPHC_AUDIO, 361 NONE(APBIF), 362 PERIPHC_DAM0, 363 PERIPHC_DAM1, 364 PERIPHC_DAM2, 365 PERIPHC_HDA2CODEC2X, 366 367 /* 16 */ 368 NONE(ATOMICS), 369 NONE(RESERVED17), 370 NONE(RESERVED18), 371 NONE(RESERVED19), 372 NONE(RESERVED20), 373 NONE(RESERVED21), 374 NONE(RESERVED22), 375 PERIPHC_ACTMON, 376 377 /* 24 */ 378 NONE(RESERVED24), 379 NONE(RESERVED25), 380 NONE(RESERVED26), 381 NONE(RESERVED27), 382 PERIPHC_SATA, 383 PERIPHC_HDA, 384 NONE(RESERVED30), 385 NONE(RESERVED31), 386 387 /* W word: 31:0 */ 388 NONE(HDA2HDMICODEC), 389 NONE(SATACOLD), 390 NONE(RESERVED0_PCIERX0), 391 NONE(RESERVED1_PCIERX1), 392 NONE(RESERVED2_PCIERX2), 393 NONE(RESERVED3_PCIERX3), 394 NONE(RESERVED4_PCIERX4), 395 NONE(RESERVED5_PCIERX5), 396 397 /* 40 */ 398 NONE(CEC), 399 NONE(RESERVED6_PCIE2), 400 NONE(RESERVED7_EMC), 401 NONE(RESERVED8_HDMI), 402 NONE(RESERVED9_SATA), 403 NONE(RESERVED10_MIPI), 404 NONE(EX_RESERVED46), 405 NONE(EX_RESERVED47), 406 }; 407 408 /* 409 * PLL divider shift/mask tables for all PLL IDs. 410 */ 411 struct clk_pll_info tegra_pll_info_table[CLOCK_ID_PLL_COUNT] = { 412 /* 413 * T30: some deviations from T2x. 414 * NOTE: If kcp_mask/kvco_mask == 0, they're not used in that PLL (PLLX, etc.) 415 * If lock_ena or lock_det are >31, they're not used in that PLL. 416 */ 417 418 { .m_shift = 0, .m_mask = 0xFF, .n_shift = 8, .n_mask = 0x3FF, .p_shift = 20, .p_mask = 0x0F, 419 .lock_ena = 24, .lock_det = 27, .kcp_shift = 28, .kcp_mask = 3, .kvco_shift = 27, .kvco_mask = 1 }, /* PLLC */ 420 { .m_shift = 0, .m_mask = 0xFF, .n_shift = 8, .n_mask = 0x3FF, .p_shift = 0, .p_mask = 0, 421 .lock_ena = 0, .lock_det = 27, .kcp_shift = 1, .kcp_mask = 3, .kvco_shift = 0, .kvco_mask = 1 }, /* PLLM */ 422 { .m_shift = 0, .m_mask = 0x1F, .n_shift = 8, .n_mask = 0x3FF, .p_shift = 20, .p_mask = 0x07, 423 .lock_ena = 18, .lock_det = 27, .kcp_shift = 8, .kcp_mask = 0xF, .kvco_shift = 4, .kvco_mask = 0xF }, /* PLLP */ 424 { .m_shift = 0, .m_mask = 0x1F, .n_shift = 8, .n_mask = 0x3FF, .p_shift = 20, .p_mask = 0x07, 425 .lock_ena = 18, .lock_det = 27, .kcp_shift = 8, .kcp_mask = 0xF, .kvco_shift = 4, .kvco_mask = 0xF }, /* PLLA */ 426 { .m_shift = 0, .m_mask = 0x1F, .n_shift = 8, .n_mask = 0x3FF, .p_shift = 20, .p_mask = 0x01, 427 .lock_ena = 22, .lock_det = 27, .kcp_shift = 8, .kcp_mask = 0xF, .kvco_shift = 4, .kvco_mask = 0xF }, /* PLLU */ 428 { .m_shift = 0, .m_mask = 0x1F, .n_shift = 8, .n_mask = 0x3FF, .p_shift = 20, .p_mask = 0x07, 429 .lock_ena = 22, .lock_det = 27, .kcp_shift = 8, .kcp_mask = 0xF, .kvco_shift = 4, .kvco_mask = 0xF }, /* PLLD */ 430 { .m_shift = 0, .m_mask = 0xFF, .n_shift = 8, .n_mask = 0xFF, .p_shift = 20, .p_mask = 0x0F, 431 .lock_ena = 18, .lock_det = 27, .kcp_shift = 8, .kcp_mask = 0xF, .kvco_shift = 0, .kvco_mask = 0 }, /* PLLX */ 432 { .m_shift = 0, .m_mask = 0xFF, .n_shift = 8, .n_mask = 0xFF, .p_shift = 0, .p_mask = 0, 433 .lock_ena = 9, .lock_det = 11, .kcp_shift = 6, .kcp_mask = 3, .kvco_shift = 0, .kvco_mask = 1 }, /* PLLE */ 434 { .m_shift = 0, .m_mask = 0x0F, .n_shift = 8, .n_mask = 0x3FF, .p_shift = 20, .p_mask = 0x07, 435 .lock_ena = 18, .lock_det = 27, .kcp_shift = 8, .kcp_mask = 0xF, .kvco_shift = 4, .kvco_mask = 0xF }, /* PLLS (RESERVED) */ 436 }; 437 438 /* 439 * Get the oscillator frequency, from the corresponding hardware configuration 440 * field. Note that T30 supports 3 new higher freqs, but we map back 441 * to the old T20 freqs. Support for the higher oscillators is TBD. 442 */ 443 enum clock_osc_freq clock_get_osc_freq(void) 444 { 445 struct clk_rst_ctlr *clkrst = 446 (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE; 447 u32 reg; 448 449 reg = readl(&clkrst->crc_osc_ctrl); 450 reg = (reg & OSC_FREQ_MASK) >> OSC_FREQ_SHIFT; 451 452 if (reg & 1) /* one of the newer freqs */ 453 printf("Warning: OSC_FREQ is unsupported! (%d)\n", reg); 454 455 return reg >> 2; /* Map to most common (T20) freqs */ 456 } 457 458 /* Returns a pointer to the clock source register for a peripheral */ 459 u32 *get_periph_source_reg(enum periph_id periph_id) 460 { 461 struct clk_rst_ctlr *clkrst = 462 (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE; 463 enum periphc_internal_id internal_id; 464 465 /* Coresight is a special case */ 466 if (periph_id == PERIPH_ID_CSI) 467 return &clkrst->crc_clk_src[PERIPH_ID_CSI+1]; 468 469 assert(periph_id >= PERIPH_ID_FIRST && periph_id < PERIPH_ID_COUNT); 470 internal_id = periph_id_to_internal_id[periph_id]; 471 assert(internal_id != -1); 472 if (internal_id >= PERIPHC_VW_FIRST) { 473 internal_id -= PERIPHC_VW_FIRST; 474 return &clkrst->crc_clk_src_vw[internal_id]; 475 } else 476 return &clkrst->crc_clk_src[internal_id]; 477 } 478 479 int get_periph_clock_info(enum periph_id periph_id, int *mux_bits, 480 int *divider_bits, int *type) 481 { 482 enum periphc_internal_id internal_id; 483 484 if (!clock_periph_id_isvalid(periph_id)) 485 return -1; 486 487 internal_id = periph_id_to_internal_id[periph_id]; 488 if (!periphc_internal_id_isvalid(internal_id)) 489 return -1; 490 491 *type = clock_periph_type[internal_id]; 492 if (!clock_type_id_isvalid(*type)) 493 return -1; 494 495 *mux_bits = clock_source[*type][CLOCK_MAX_MUX]; 496 497 if (*type == CLOCK_TYPE_PCMT16) 498 *divider_bits = 16; 499 else 500 *divider_bits = 8; 501 502 return 0; 503 } 504 505 enum clock_id get_periph_clock_id(enum periph_id periph_id, int source) 506 { 507 enum periphc_internal_id internal_id; 508 int type; 509 510 if (!clock_periph_id_isvalid(periph_id)) 511 return CLOCK_ID_NONE; 512 513 internal_id = periph_id_to_internal_id[periph_id]; 514 if (!periphc_internal_id_isvalid(internal_id)) 515 return CLOCK_ID_NONE; 516 517 type = clock_periph_type[internal_id]; 518 if (!clock_type_id_isvalid(type)) 519 return CLOCK_ID_NONE; 520 521 return clock_source[type][source]; 522 } 523 524 /** 525 * Given a peripheral ID and the required source clock, this returns which 526 * value should be programmed into the source mux for that peripheral. 527 * 528 * There is special code here to handle the one source type with 5 sources. 529 * 530 * @param periph_id peripheral to start 531 * @param source PLL id of required parent clock 532 * @param mux_bits Set to number of bits in mux register: 2 or 4 533 * @param divider_bits Set to number of divider bits (8 or 16) 534 * @return mux value (0-4, or -1 if not found) 535 */ 536 int get_periph_clock_source(enum periph_id periph_id, 537 enum clock_id parent, int *mux_bits, int *divider_bits) 538 { 539 enum clock_type_id type; 540 int mux, err; 541 542 err = get_periph_clock_info(periph_id, mux_bits, divider_bits, &type); 543 assert(!err); 544 545 for (mux = 0; mux < CLOCK_MAX_MUX; mux++) 546 if (clock_source[type][mux] == parent) 547 return mux; 548 549 /* if we get here, either us or the caller has made a mistake */ 550 printf("Caller requested bad clock: periph=%d, parent=%d\n", periph_id, 551 parent); 552 return -1; 553 } 554 555 void clock_set_enable(enum periph_id periph_id, int enable) 556 { 557 struct clk_rst_ctlr *clkrst = 558 (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE; 559 u32 *clk; 560 u32 reg; 561 562 /* Enable/disable the clock to this peripheral */ 563 assert(clock_periph_id_isvalid(periph_id)); 564 if ((int)periph_id < (int)PERIPH_ID_VW_FIRST) 565 clk = &clkrst->crc_clk_out_enb[PERIPH_REG(periph_id)]; 566 else 567 clk = &clkrst->crc_clk_out_enb_vw[PERIPH_REG(periph_id)]; 568 reg = readl(clk); 569 if (enable) 570 reg |= PERIPH_MASK(periph_id); 571 else 572 reg &= ~PERIPH_MASK(periph_id); 573 writel(reg, clk); 574 } 575 576 void reset_set_enable(enum periph_id periph_id, int enable) 577 { 578 struct clk_rst_ctlr *clkrst = 579 (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE; 580 u32 *reset; 581 u32 reg; 582 583 /* Enable/disable reset to the peripheral */ 584 assert(clock_periph_id_isvalid(periph_id)); 585 if (periph_id < PERIPH_ID_VW_FIRST) 586 reset = &clkrst->crc_rst_dev[PERIPH_REG(periph_id)]; 587 else 588 reset = &clkrst->crc_rst_dev_vw[PERIPH_REG(periph_id)]; 589 reg = readl(reset); 590 if (enable) 591 reg |= PERIPH_MASK(periph_id); 592 else 593 reg &= ~PERIPH_MASK(periph_id); 594 writel(reg, reset); 595 } 596 597 #if CONFIG_IS_ENABLED(OF_CONTROL) 598 /* 599 * Convert a device tree clock ID to our peripheral ID. They are mostly 600 * the same but we are very cautious so we check that a valid clock ID is 601 * provided. 602 * 603 * @param clk_id Clock ID according to tegra30 device tree binding 604 * @return peripheral ID, or PERIPH_ID_NONE if the clock ID is invalid 605 */ 606 enum periph_id clk_id_to_periph_id(int clk_id) 607 { 608 if (clk_id > PERIPH_ID_COUNT) 609 return PERIPH_ID_NONE; 610 611 switch (clk_id) { 612 case PERIPH_ID_RESERVED3: 613 case PERIPH_ID_RESERVED4: 614 case PERIPH_ID_RESERVED16: 615 case PERIPH_ID_RESERVED24: 616 case PERIPH_ID_RESERVED35: 617 case PERIPH_ID_RESERVED43: 618 case PERIPH_ID_RESERVED45: 619 case PERIPH_ID_RESERVED56: 620 case PERIPH_ID_PCIEXCLK: 621 case PERIPH_ID_RESERVED76: 622 case PERIPH_ID_RESERVED77: 623 case PERIPH_ID_RESERVED78: 624 case PERIPH_ID_RESERVED83: 625 case PERIPH_ID_RESERVED89: 626 case PERIPH_ID_RESERVED91: 627 case PERIPH_ID_RESERVED93: 628 case PERIPH_ID_RESERVED94: 629 case PERIPH_ID_RESERVED95: 630 return PERIPH_ID_NONE; 631 default: 632 return clk_id; 633 } 634 } 635 #endif /* CONFIG_IS_ENABLED(OF_CONTROL) */ 636 637 void clock_early_init(void) 638 { 639 tegra30_set_up_pllp(); 640 } 641 642 void arch_timer_init(void) 643 { 644 } 645 646 #define PMC_SATA_PWRGT 0x1ac 647 #define PMC_SATA_PWRGT_PLLE_IDDQ_OVERRIDE (1 << 5) 648 #define PMC_SATA_PWRGT_PLLE_IDDQ_SWCTL (1 << 4) 649 650 #define PLLE_SS_CNTL 0x68 651 #define PLLE_SS_CNTL_SSCINCINTRV(x) (((x) & 0x3f) << 24) 652 #define PLLE_SS_CNTL_SSCINC(x) (((x) & 0xff) << 16) 653 #define PLLE_SS_CNTL_SSCBYP (1 << 12) 654 #define PLLE_SS_CNTL_INTERP_RESET (1 << 11) 655 #define PLLE_SS_CNTL_BYPASS_SS (1 << 10) 656 #define PLLE_SS_CNTL_SSCMAX(x) (((x) & 0x1ff) << 0) 657 658 #define PLLE_BASE 0x0e8 659 #define PLLE_BASE_ENABLE_CML (1 << 31) 660 #define PLLE_BASE_ENABLE (1 << 30) 661 #define PLLE_BASE_PLDIV_CML(x) (((x) & 0xf) << 24) 662 #define PLLE_BASE_PLDIV(x) (((x) & 0x3f) << 16) 663 #define PLLE_BASE_NDIV(x) (((x) & 0xff) << 8) 664 #define PLLE_BASE_MDIV(x) (((x) & 0xff) << 0) 665 666 #define PLLE_MISC 0x0ec 667 #define PLLE_MISC_SETUP_BASE(x) (((x) & 0xffff) << 16) 668 #define PLLE_MISC_PLL_READY (1 << 15) 669 #define PLLE_MISC_LOCK (1 << 11) 670 #define PLLE_MISC_LOCK_ENABLE (1 << 9) 671 #define PLLE_MISC_SETUP_EXT(x) (((x) & 0x3) << 2) 672 673 static int tegra_plle_train(void) 674 { 675 unsigned int timeout = 2000; 676 unsigned long value; 677 678 value = readl(NV_PA_PMC_BASE + PMC_SATA_PWRGT); 679 value |= PMC_SATA_PWRGT_PLLE_IDDQ_OVERRIDE; 680 writel(value, NV_PA_PMC_BASE + PMC_SATA_PWRGT); 681 682 value = readl(NV_PA_PMC_BASE + PMC_SATA_PWRGT); 683 value |= PMC_SATA_PWRGT_PLLE_IDDQ_SWCTL; 684 writel(value, NV_PA_PMC_BASE + PMC_SATA_PWRGT); 685 686 value = readl(NV_PA_PMC_BASE + PMC_SATA_PWRGT); 687 value &= ~PMC_SATA_PWRGT_PLLE_IDDQ_OVERRIDE; 688 writel(value, NV_PA_PMC_BASE + PMC_SATA_PWRGT); 689 690 do { 691 value = readl(NV_PA_CLK_RST_BASE + PLLE_MISC); 692 if (value & PLLE_MISC_PLL_READY) 693 break; 694 695 udelay(100); 696 } while (--timeout); 697 698 if (timeout == 0) { 699 pr_err("timeout waiting for PLLE to become ready"); 700 return -ETIMEDOUT; 701 } 702 703 return 0; 704 } 705 706 int tegra_plle_enable(void) 707 { 708 unsigned int cpcon = 11, p = 18, n = 150, m = 1, timeout = 1000; 709 u32 value; 710 int err; 711 712 /* disable PLLE clock */ 713 value = readl(NV_PA_CLK_RST_BASE + PLLE_BASE); 714 value &= ~PLLE_BASE_ENABLE_CML; 715 value &= ~PLLE_BASE_ENABLE; 716 writel(value, NV_PA_CLK_RST_BASE + PLLE_BASE); 717 718 /* clear lock enable and setup field */ 719 value = readl(NV_PA_CLK_RST_BASE + PLLE_MISC); 720 value &= ~PLLE_MISC_LOCK_ENABLE; 721 value &= ~PLLE_MISC_SETUP_BASE(0xffff); 722 value &= ~PLLE_MISC_SETUP_EXT(0x3); 723 writel(value, NV_PA_CLK_RST_BASE + PLLE_MISC); 724 725 value = readl(NV_PA_CLK_RST_BASE + PLLE_MISC); 726 if ((value & PLLE_MISC_PLL_READY) == 0) { 727 err = tegra_plle_train(); 728 if (err < 0) { 729 pr_err("failed to train PLLE: %d", err); 730 return err; 731 } 732 } 733 734 /* configure PLLE */ 735 value = readl(NV_PA_CLK_RST_BASE + PLLE_BASE); 736 737 value &= ~PLLE_BASE_PLDIV_CML(0x0f); 738 value |= PLLE_BASE_PLDIV_CML(cpcon); 739 740 value &= ~PLLE_BASE_PLDIV(0x3f); 741 value |= PLLE_BASE_PLDIV(p); 742 743 value &= ~PLLE_BASE_NDIV(0xff); 744 value |= PLLE_BASE_NDIV(n); 745 746 value &= ~PLLE_BASE_MDIV(0xff); 747 value |= PLLE_BASE_MDIV(m); 748 749 writel(value, NV_PA_CLK_RST_BASE + PLLE_BASE); 750 751 value = readl(NV_PA_CLK_RST_BASE + PLLE_MISC); 752 value |= PLLE_MISC_SETUP_BASE(0x7); 753 value |= PLLE_MISC_LOCK_ENABLE; 754 value |= PLLE_MISC_SETUP_EXT(0); 755 writel(value, NV_PA_CLK_RST_BASE + PLLE_MISC); 756 757 value = readl(NV_PA_CLK_RST_BASE + PLLE_SS_CNTL); 758 value |= PLLE_SS_CNTL_SSCBYP | PLLE_SS_CNTL_INTERP_RESET | 759 PLLE_SS_CNTL_BYPASS_SS; 760 writel(value, NV_PA_CLK_RST_BASE + PLLE_SS_CNTL); 761 762 value = readl(NV_PA_CLK_RST_BASE + PLLE_BASE); 763 value |= PLLE_BASE_ENABLE_CML | PLLE_BASE_ENABLE; 764 writel(value, NV_PA_CLK_RST_BASE + PLLE_BASE); 765 766 do { 767 value = readl(NV_PA_CLK_RST_BASE + PLLE_MISC); 768 if (value & PLLE_MISC_LOCK) 769 break; 770 771 udelay(2); 772 } while (--timeout); 773 774 if (timeout == 0) { 775 pr_err("timeout waiting for PLLE to lock"); 776 return -ETIMEDOUT; 777 } 778 779 udelay(50); 780 781 value = readl(NV_PA_CLK_RST_BASE + PLLE_SS_CNTL); 782 value &= ~PLLE_SS_CNTL_SSCINCINTRV(0x3f); 783 value |= PLLE_SS_CNTL_SSCINCINTRV(0x18); 784 785 value &= ~PLLE_SS_CNTL_SSCINC(0xff); 786 value |= PLLE_SS_CNTL_SSCINC(0x01); 787 788 value &= ~PLLE_SS_CNTL_SSCBYP; 789 value &= ~PLLE_SS_CNTL_INTERP_RESET; 790 value &= ~PLLE_SS_CNTL_BYPASS_SS; 791 792 value &= ~PLLE_SS_CNTL_SSCMAX(0x1ff); 793 value |= PLLE_SS_CNTL_SSCMAX(0x24); 794 writel(value, NV_PA_CLK_RST_BASE + PLLE_SS_CNTL); 795 796 return 0; 797 } 798 799 struct periph_clk_init periph_clk_init_table[] = { 800 { PERIPH_ID_SBC1, CLOCK_ID_PERIPH }, 801 { PERIPH_ID_SBC2, CLOCK_ID_PERIPH }, 802 { PERIPH_ID_SBC3, CLOCK_ID_PERIPH }, 803 { PERIPH_ID_SBC4, CLOCK_ID_PERIPH }, 804 { PERIPH_ID_SBC5, CLOCK_ID_PERIPH }, 805 { PERIPH_ID_SBC6, CLOCK_ID_PERIPH }, 806 { PERIPH_ID_HOST1X, CLOCK_ID_PERIPH }, 807 { PERIPH_ID_DISP1, CLOCK_ID_CGENERAL }, 808 { PERIPH_ID_NDFLASH, CLOCK_ID_PERIPH }, 809 { PERIPH_ID_SDMMC1, CLOCK_ID_PERIPH }, 810 { PERIPH_ID_SDMMC2, CLOCK_ID_PERIPH }, 811 { PERIPH_ID_SDMMC3, CLOCK_ID_PERIPH }, 812 { PERIPH_ID_SDMMC4, CLOCK_ID_PERIPH }, 813 { PERIPH_ID_PWM, CLOCK_ID_SFROM32KHZ }, 814 { PERIPH_ID_DVC_I2C, CLOCK_ID_PERIPH }, 815 { PERIPH_ID_I2C1, CLOCK_ID_PERIPH }, 816 { PERIPH_ID_I2C2, CLOCK_ID_PERIPH }, 817 { PERIPH_ID_I2C3, CLOCK_ID_PERIPH }, 818 { PERIPH_ID_I2C4, CLOCK_ID_PERIPH }, 819 { -1, }, 820 }; 821