1 /*
2  * Copyright (c) 2014-2015, NVIDIA CORPORATION.  All rights reserved.
3  *
4  * SPDX-License-Identifier: GPL-2.0
5  */
6 
7 #define pr_fmt(fmt) "tegra-xusb-padctl: " fmt
8 
9 #include <common.h>
10 #include <errno.h>
11 #include <dm/of_access.h>
12 #include <dm/ofnode.h>
13 
14 #include "../xusb-padctl-common.h"
15 
16 #include <asm/arch/clock.h>
17 
18 #include <dt-bindings/pinctrl/pinctrl-tegra-xusb.h>
19 
20 DECLARE_GLOBAL_DATA_PTR;
21 
22 enum tegra210_function {
23 	TEGRA210_FUNC_SNPS,
24 	TEGRA210_FUNC_XUSB,
25 	TEGRA210_FUNC_UART,
26 	TEGRA210_FUNC_PCIE_X1,
27 	TEGRA210_FUNC_PCIE_X4,
28 	TEGRA210_FUNC_USB3,
29 	TEGRA210_FUNC_SATA,
30 	TEGRA210_FUNC_RSVD,
31 };
32 
33 static const char *const tegra210_functions[] = {
34 	"snps",
35 	"xusb",
36 	"uart",
37 	"pcie-x1",
38 	"pcie-x4",
39 	"usb3",
40 	"sata",
41 	"rsvd",
42 };
43 
44 static const unsigned int tegra210_otg_functions[] = {
45 	TEGRA210_FUNC_SNPS,
46 	TEGRA210_FUNC_XUSB,
47 	TEGRA210_FUNC_UART,
48 	TEGRA210_FUNC_RSVD,
49 };
50 
51 static const unsigned int tegra210_usb_functions[] = {
52 	TEGRA210_FUNC_SNPS,
53 	TEGRA210_FUNC_XUSB,
54 };
55 
56 static const unsigned int tegra210_pci_functions[] = {
57 	TEGRA210_FUNC_PCIE_X1,
58 	TEGRA210_FUNC_USB3,
59 	TEGRA210_FUNC_SATA,
60 	TEGRA210_FUNC_PCIE_X4,
61 };
62 
63 #define TEGRA210_LANE(_name, _offset, _shift, _mask, _iddq, _funcs)	\
64 	{								\
65 		.name = _name,						\
66 		.offset = _offset,					\
67 		.shift = _shift,					\
68 		.mask = _mask,						\
69 		.iddq = _iddq,						\
70 		.num_funcs = ARRAY_SIZE(tegra210_##_funcs##_functions),	\
71 		.funcs = tegra210_##_funcs##_functions,			\
72 	}
73 
74 static const struct tegra_xusb_padctl_lane tegra210_lanes[] = {
75 	TEGRA210_LANE("otg-0",     0x004,  0, 0x3, 0, otg),
76 	TEGRA210_LANE("otg-1",     0x004,  2, 0x3, 0, otg),
77 	TEGRA210_LANE("otg-2",     0x004,  4, 0x3, 0, otg),
78 	TEGRA210_LANE("otg-3",     0x004,  6, 0x3, 0, otg),
79 	TEGRA210_LANE("usb2-bias", 0x004, 18, 0x3, 0, otg),
80 	TEGRA210_LANE("hsic-0",    0x004, 14, 0x1, 0, usb),
81 	TEGRA210_LANE("hsic-1",    0x004, 15, 0x1, 0, usb),
82 	TEGRA210_LANE("pcie-0",    0x028, 12, 0x3, 1, pci),
83 	TEGRA210_LANE("pcie-1",    0x028, 14, 0x3, 2, pci),
84 	TEGRA210_LANE("pcie-2",    0x028, 16, 0x3, 3, pci),
85 	TEGRA210_LANE("pcie-3",    0x028, 18, 0x3, 4, pci),
86 	TEGRA210_LANE("pcie-4",    0x028, 20, 0x3, 5, pci),
87 	TEGRA210_LANE("pcie-5",    0x028, 22, 0x3, 6, pci),
88 	TEGRA210_LANE("pcie-6",    0x028, 24, 0x3, 7, pci),
89 	TEGRA210_LANE("sata-0",    0x028, 30, 0x3, 8, pci),
90 };
91 
92 #define XUSB_PADCTL_ELPG_PROGRAM 0x024
93 #define  XUSB_PADCTL_ELPG_PROGRAM_AUX_MUX_LP0_VCORE_DOWN (1 << 31)
94 #define  XUSB_PADCTL_ELPG_PROGRAM_AUX_MUX_LP0_CLAMP_EN_EARLY (1 << 30)
95 #define  XUSB_PADCTL_ELPG_PROGRAM_AUX_MUX_LP0_CLAMP_EN (1 << 29)
96 
97 static int tegra_xusb_padctl_enable(struct tegra_xusb_padctl *padctl)
98 {
99 	u32 value;
100 
101 	if (padctl->enable++ > 0)
102 		return 0;
103 
104 	value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM);
105 	value &= ~XUSB_PADCTL_ELPG_PROGRAM_AUX_MUX_LP0_CLAMP_EN;
106 	padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM);
107 
108 	udelay(100);
109 
110 	value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM);
111 	value &= ~XUSB_PADCTL_ELPG_PROGRAM_AUX_MUX_LP0_CLAMP_EN_EARLY;
112 	padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM);
113 
114 	udelay(100);
115 
116 	value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM);
117 	value &= ~XUSB_PADCTL_ELPG_PROGRAM_AUX_MUX_LP0_VCORE_DOWN;
118 	padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM);
119 
120 	return 0;
121 }
122 
123 static int tegra_xusb_padctl_disable(struct tegra_xusb_padctl *padctl)
124 {
125 	u32 value;
126 
127 	if (padctl->enable == 0) {
128 		pr_err("unbalanced enable/disable");
129 		return 0;
130 	}
131 
132 	if (--padctl->enable > 0)
133 		return 0;
134 
135 	value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM);
136 	value |= XUSB_PADCTL_ELPG_PROGRAM_AUX_MUX_LP0_VCORE_DOWN;
137 	padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM);
138 
139 	udelay(100);
140 
141 	value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM);
142 	value |= XUSB_PADCTL_ELPG_PROGRAM_AUX_MUX_LP0_CLAMP_EN_EARLY;
143 	padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM);
144 
145 	udelay(100);
146 
147 	value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM);
148 	value |= XUSB_PADCTL_ELPG_PROGRAM_AUX_MUX_LP0_CLAMP_EN;
149 	padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM);
150 
151 	return 0;
152 }
153 
154 static int phy_prepare(struct tegra_xusb_phy *phy)
155 {
156 	int err;
157 
158 	err = tegra_xusb_padctl_enable(phy->padctl);
159 	if (err < 0)
160 		return err;
161 
162 	reset_set_enable(PERIPH_ID_PEX_USB_UPHY, 0);
163 
164 	return 0;
165 }
166 
167 static int phy_unprepare(struct tegra_xusb_phy *phy)
168 {
169 	reset_set_enable(PERIPH_ID_PEX_USB_UPHY, 1);
170 
171 	return tegra_xusb_padctl_disable(phy->padctl);
172 }
173 
174 #define XUSB_PADCTL_UPHY_PLL_P0_CTL1 0x360
175 #define  XUSB_PADCTL_UPHY_PLL_P0_CTL1_FREQ_NDIV_MASK (0xff << 20)
176 #define  XUSB_PADCTL_UPHY_PLL_P0_CTL1_FREQ_NDIV(x) (((x) & 0xff) << 20)
177 #define  XUSB_PADCTL_UPHY_PLL_P0_CTL1_FREQ_MDIV_MASK (0x3 << 16)
178 #define  XUSB_PADCTL_UPHY_PLL_P0_CTL1_LOCKDET_STATUS (1 << 15)
179 #define  XUSB_PADCTL_UPHY_PLL_P0_CTL1_PWR_OVRD (1 << 4)
180 #define  XUSB_PADCTL_UPHY_PLL_P0_CTL1_ENABLE (1 << 3)
181 #define  XUSB_PADCTL_UPHY_PLL_P0_CTL1_SLEEP_MASK (0x3 << 1)
182 #define  XUSB_PADCTL_UPHY_PLL_P0_CTL1_SLEEP(x) (((x) & 0x3) << 1)
183 #define  XUSB_PADCTL_UPHY_PLL_P0_CTL1_IDDQ (1 << 0)
184 
185 #define XUSB_PADCTL_UPHY_PLL_P0_CTL2 0x364
186 #define  XUSB_PADCTL_UPHY_PLL_P0_CTL2_CAL_CTRL_MASK (0xffffff << 4)
187 #define  XUSB_PADCTL_UPHY_PLL_P0_CTL2_CAL_CTRL(x) (((x) & 0xffffff) << 4)
188 #define  XUSB_PADCTL_UPHY_PLL_P0_CTL2_CAL_OVRD (1 << 2)
189 #define  XUSB_PADCTL_UPHY_PLL_P0_CTL2_CAL_DONE (1 << 1)
190 #define  XUSB_PADCTL_UPHY_PLL_P0_CTL2_CAL_EN (1 << 0)
191 
192 #define XUSB_PADCTL_UPHY_PLL_P0_CTL4 0x36c
193 #define  XUSB_PADCTL_UPHY_PLL_P0_CTL4_TXCLKREF_EN (1 << 15)
194 #define  XUSB_PADCTL_UPHY_PLL_P0_CTL4_TXCLKREF_SEL_MASK (0x3 << 12)
195 #define  XUSB_PADCTL_UPHY_PLL_P0_CTL4_TXCLKREF_SEL(x) (((x) & 0x3) << 12)
196 #define  XUSB_PADCTL_UPHY_PLL_P0_CTL4_REFCLKBUF_EN (1 << 8)
197 #define  XUSB_PADCTL_UPHY_PLL_P0_CTL4_REFCLK_SEL_MASK (0xf << 4)
198 
199 #define XUSB_PADCTL_UPHY_PLL_P0_CTL5 0x370
200 #define  XUSB_PADCTL_UPHY_PLL_P0_CTL5_DCO_CTRL_MASK (0xff << 16)
201 #define  XUSB_PADCTL_UPHY_PLL_P0_CTL5_DCO_CTRL(x) (((x) & 0xff) << 16)
202 
203 #define XUSB_PADCTL_UPHY_PLL_P0_CTL8 0x37c
204 #define  XUSB_PADCTL_UPHY_PLL_P0_CTL8_RCAL_DONE (1 << 31)
205 #define  XUSB_PADCTL_UPHY_PLL_P0_CTL8_RCAL_OVRD (1 << 15)
206 #define  XUSB_PADCTL_UPHY_PLL_P0_CTL8_RCAL_CLK_EN (1 << 13)
207 #define  XUSB_PADCTL_UPHY_PLL_P0_CTL8_RCAL_EN (1 << 12)
208 
209 #define CLK_RST_XUSBIO_PLL_CFG0 0x51c
210 #define  CLK_RST_XUSBIO_PLL_CFG0_SEQ_ENABLE (1 << 24)
211 #define  CLK_RST_XUSBIO_PLL_CFG0_PADPLL_SLEEP_IDDQ (1 << 13)
212 #define  CLK_RST_XUSBIO_PLL_CFG0_PADPLL_USE_LOCKDET (1 << 6)
213 #define  CLK_RST_XUSBIO_PLL_CFG0_CLK_ENABLE_SWCTL (1 << 2)
214 #define  CLK_RST_XUSBIO_PLL_CFG0_PADPLL_RESET_SWCTL (1 << 0)
215 
216 static int pcie_phy_enable(struct tegra_xusb_phy *phy)
217 {
218 	struct tegra_xusb_padctl *padctl = phy->padctl;
219 	unsigned long start;
220 	u32 value;
221 
222 	debug("> %s(phy=%p)\n", __func__, phy);
223 
224 	value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL2);
225 	value &= ~XUSB_PADCTL_UPHY_PLL_P0_CTL2_CAL_CTRL_MASK;
226 	value |= XUSB_PADCTL_UPHY_PLL_P0_CTL2_CAL_CTRL(0x136);
227 	padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_P0_CTL2);
228 
229 	value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL5);
230 	value &= ~XUSB_PADCTL_UPHY_PLL_P0_CTL5_DCO_CTRL_MASK;
231 	value |= XUSB_PADCTL_UPHY_PLL_P0_CTL5_DCO_CTRL(0x2a);
232 	padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_P0_CTL5);
233 
234 	value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL1);
235 	value |= XUSB_PADCTL_UPHY_PLL_P0_CTL1_PWR_OVRD;
236 	padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_P0_CTL1);
237 
238 	value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL2);
239 	value |= XUSB_PADCTL_UPHY_PLL_P0_CTL2_CAL_OVRD;
240 	padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_P0_CTL2);
241 
242 	value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL8);
243 	value |= XUSB_PADCTL_UPHY_PLL_P0_CTL8_RCAL_OVRD;
244 	padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_P0_CTL8);
245 
246 	value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL4);
247 	value &= ~XUSB_PADCTL_UPHY_PLL_P0_CTL4_TXCLKREF_SEL_MASK;
248 	value &= ~XUSB_PADCTL_UPHY_PLL_P0_CTL4_REFCLK_SEL_MASK;
249 	value |= XUSB_PADCTL_UPHY_PLL_P0_CTL4_TXCLKREF_SEL(2);
250 	value |= XUSB_PADCTL_UPHY_PLL_P0_CTL4_TXCLKREF_EN;
251 	padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_P0_CTL4);
252 
253 	value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL1);
254 	value &= ~XUSB_PADCTL_UPHY_PLL_P0_CTL1_FREQ_MDIV_MASK;
255 	value &= ~XUSB_PADCTL_UPHY_PLL_P0_CTL1_FREQ_NDIV_MASK;
256 	value |= XUSB_PADCTL_UPHY_PLL_P0_CTL1_FREQ_NDIV(25);
257 	padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_P0_CTL1);
258 
259 	value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL1);
260 	value &= ~XUSB_PADCTL_UPHY_PLL_P0_CTL1_IDDQ;
261 	padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_P0_CTL1);
262 
263 	value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL1);
264 	value &= ~XUSB_PADCTL_UPHY_PLL_P0_CTL1_SLEEP_MASK;
265 	padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_P0_CTL1);
266 
267 	udelay(1);
268 
269 	value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL4);
270 	value |= XUSB_PADCTL_UPHY_PLL_P0_CTL4_REFCLKBUF_EN;
271 	padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_P0_CTL4);
272 
273 	value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL2);
274 	value |= XUSB_PADCTL_UPHY_PLL_P0_CTL2_CAL_EN;
275 	padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_P0_CTL2);
276 
277 	debug("  waiting for calibration\n");
278 
279 	start = get_timer(0);
280 
281 	while (get_timer(start) < 250) {
282 		value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL2);
283 		if (value & XUSB_PADCTL_UPHY_PLL_P0_CTL2_CAL_DONE)
284 			break;
285 	}
286 	if (!(value & XUSB_PADCTL_UPHY_PLL_P0_CTL2_CAL_DONE)) {
287 		debug("  timeout\n");
288 		return -ETIMEDOUT;
289 	}
290 	debug("  done\n");
291 
292 	value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL2);
293 	value &= ~XUSB_PADCTL_UPHY_PLL_P0_CTL2_CAL_EN;
294 	padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_P0_CTL2);
295 
296 	debug("  waiting for calibration to stop\n");
297 
298 	start = get_timer(0);
299 
300 	while (get_timer(start) < 250) {
301 		value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL2);
302 		if ((value & XUSB_PADCTL_UPHY_PLL_P0_CTL2_CAL_DONE) == 0)
303 			break;
304 	}
305 	if (value & XUSB_PADCTL_UPHY_PLL_P0_CTL2_CAL_DONE) {
306 		debug("  timeout\n");
307 		return -ETIMEDOUT;
308 	}
309 	debug("  done\n");
310 
311 	value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL1);
312 	value |= XUSB_PADCTL_UPHY_PLL_P0_CTL1_ENABLE;
313 	padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_P0_CTL1);
314 
315 	debug("  waiting for PLL to lock...\n");
316 	start = get_timer(0);
317 
318 	while (get_timer(start) < 250) {
319 		value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL1);
320 		if (value & XUSB_PADCTL_UPHY_PLL_P0_CTL1_LOCKDET_STATUS)
321 			break;
322 	}
323 	if (!(value & XUSB_PADCTL_UPHY_PLL_P0_CTL1_LOCKDET_STATUS)) {
324 		debug("  timeout\n");
325 		return -ETIMEDOUT;
326 	}
327 	debug("  done\n");
328 
329 	value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL8);
330 	value |= XUSB_PADCTL_UPHY_PLL_P0_CTL8_RCAL_CLK_EN;
331 	value |= XUSB_PADCTL_UPHY_PLL_P0_CTL8_RCAL_EN;
332 	padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_P0_CTL8);
333 
334 	debug("  waiting for register calibration...\n");
335 	start = get_timer(0);
336 
337 	while (get_timer(start) < 250) {
338 		value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL8);
339 		if (value & XUSB_PADCTL_UPHY_PLL_P0_CTL8_RCAL_DONE)
340 			break;
341 	}
342 	if (!(value & XUSB_PADCTL_UPHY_PLL_P0_CTL8_RCAL_DONE)) {
343 		debug("  timeout\n");
344 		return -ETIMEDOUT;
345 	}
346 	debug("  done\n");
347 
348 	value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL8);
349 	value &= ~XUSB_PADCTL_UPHY_PLL_P0_CTL8_RCAL_EN;
350 	padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_P0_CTL8);
351 
352 	debug("  waiting for register calibration to stop...\n");
353 	start = get_timer(0);
354 
355 	while (get_timer(start) < 250) {
356 		value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL8);
357 		if ((value & XUSB_PADCTL_UPHY_PLL_P0_CTL8_RCAL_DONE) == 0)
358 			break;
359 	}
360 	if (value & XUSB_PADCTL_UPHY_PLL_P0_CTL8_RCAL_DONE) {
361 		debug("  timeout\n");
362 		return -ETIMEDOUT;
363 	}
364 	debug("  done\n");
365 
366 	value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL8);
367 	value &= ~XUSB_PADCTL_UPHY_PLL_P0_CTL8_RCAL_CLK_EN;
368 	padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_P0_CTL8);
369 
370 	value = readl(NV_PA_CLK_RST_BASE + CLK_RST_XUSBIO_PLL_CFG0);
371 	value &= ~CLK_RST_XUSBIO_PLL_CFG0_PADPLL_RESET_SWCTL;
372 	value &= ~CLK_RST_XUSBIO_PLL_CFG0_CLK_ENABLE_SWCTL;
373 	value |= CLK_RST_XUSBIO_PLL_CFG0_PADPLL_USE_LOCKDET;
374 	value |= CLK_RST_XUSBIO_PLL_CFG0_PADPLL_SLEEP_IDDQ;
375 	writel(value, NV_PA_CLK_RST_BASE + CLK_RST_XUSBIO_PLL_CFG0);
376 
377 	value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL1);
378 	value &= ~XUSB_PADCTL_UPHY_PLL_P0_CTL1_PWR_OVRD;
379 	padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_P0_CTL1);
380 
381 	value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL2);
382 	value &= ~XUSB_PADCTL_UPHY_PLL_P0_CTL2_CAL_OVRD;
383 	padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_P0_CTL2);
384 
385 	value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL8);
386 	value &= ~XUSB_PADCTL_UPHY_PLL_P0_CTL8_RCAL_OVRD;
387 	padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_P0_CTL8);
388 
389 	udelay(1);
390 
391 	value = readl(NV_PA_CLK_RST_BASE + CLK_RST_XUSBIO_PLL_CFG0);
392 	value |= CLK_RST_XUSBIO_PLL_CFG0_SEQ_ENABLE;
393 	writel(value, NV_PA_CLK_RST_BASE + CLK_RST_XUSBIO_PLL_CFG0);
394 
395 	debug("< %s()\n", __func__);
396 	return 0;
397 }
398 
399 static int pcie_phy_disable(struct tegra_xusb_phy *phy)
400 {
401 	return 0;
402 }
403 
404 static const struct tegra_xusb_phy_ops pcie_phy_ops = {
405 	.prepare = phy_prepare,
406 	.enable = pcie_phy_enable,
407 	.disable = pcie_phy_disable,
408 	.unprepare = phy_unprepare,
409 };
410 
411 static struct tegra_xusb_phy tegra210_phys[] = {
412 	{
413 		.type = TEGRA_XUSB_PADCTL_PCIE,
414 		.ops = &pcie_phy_ops,
415 		.padctl = &padctl,
416 	},
417 };
418 
419 static const struct tegra_xusb_padctl_soc tegra210_socdata = {
420 	.lanes = tegra210_lanes,
421 	.num_lanes = ARRAY_SIZE(tegra210_lanes),
422 	.functions = tegra210_functions,
423 	.num_functions = ARRAY_SIZE(tegra210_functions),
424 	.phys = tegra210_phys,
425 	.num_phys = ARRAY_SIZE(tegra210_phys),
426 };
427 
428 void tegra_xusb_padctl_init(void)
429 {
430 	ofnode nodes[1];
431 	int count = 0;
432 	int ret;
433 
434 	debug("%s: start\n", __func__);
435 	if (of_live_active()) {
436 		struct device_node *np = of_find_compatible_node(NULL, NULL,
437 						"nvidia,tegra210-xusb-padctl");
438 
439 		debug("np=%p\n", np);
440 		if (np) {
441 			nodes[0] = np_to_ofnode(np);
442 			count = 1;
443 		}
444 	} else {
445 		int node_offsets[1];
446 		int i;
447 
448 		count = fdtdec_find_aliases_for_id(gd->fdt_blob, "padctl",
449 				COMPAT_NVIDIA_TEGRA210_XUSB_PADCTL,
450 				node_offsets, ARRAY_SIZE(node_offsets));
451 		for (i = 0; i < count; i++)
452 			nodes[i] = offset_to_ofnode(node_offsets[i]);
453 	}
454 
455 	ret = tegra_xusb_process_nodes(nodes, count, &tegra210_socdata);
456 	debug("%s: done, ret=%d\n", __func__, ret);
457 }
458