1 // SPDX-License-Identifier: GPL-2.0
2 /*
3  * Copyright (c) 2014-2015, NVIDIA CORPORATION.  All rights reserved.
4  */
5 
6 #define pr_fmt(fmt) "tegra-xusb-padctl: " fmt
7 
8 #include <common.h>
9 #include <errno.h>
10 #include <dm/of_access.h>
11 #include <dm/ofnode.h>
12 
13 #include "../xusb-padctl-common.h"
14 
15 #include <asm/arch/clock.h>
16 
17 #include <dt-bindings/pinctrl/pinctrl-tegra-xusb.h>
18 
19 DECLARE_GLOBAL_DATA_PTR;
20 
21 enum tegra210_function {
22 	TEGRA210_FUNC_SNPS,
23 	TEGRA210_FUNC_XUSB,
24 	TEGRA210_FUNC_UART,
25 	TEGRA210_FUNC_PCIE_X1,
26 	TEGRA210_FUNC_PCIE_X4,
27 	TEGRA210_FUNC_USB3,
28 	TEGRA210_FUNC_SATA,
29 	TEGRA210_FUNC_RSVD,
30 };
31 
32 static const char *const tegra210_functions[] = {
33 	"snps",
34 	"xusb",
35 	"uart",
36 	"pcie-x1",
37 	"pcie-x4",
38 	"usb3",
39 	"sata",
40 	"rsvd",
41 };
42 
43 static const unsigned int tegra210_otg_functions[] = {
44 	TEGRA210_FUNC_SNPS,
45 	TEGRA210_FUNC_XUSB,
46 	TEGRA210_FUNC_UART,
47 	TEGRA210_FUNC_RSVD,
48 };
49 
50 static const unsigned int tegra210_usb_functions[] = {
51 	TEGRA210_FUNC_SNPS,
52 	TEGRA210_FUNC_XUSB,
53 };
54 
55 static const unsigned int tegra210_pci_functions[] = {
56 	TEGRA210_FUNC_PCIE_X1,
57 	TEGRA210_FUNC_USB3,
58 	TEGRA210_FUNC_SATA,
59 	TEGRA210_FUNC_PCIE_X4,
60 };
61 
62 #define TEGRA210_LANE(_name, _offset, _shift, _mask, _iddq, _funcs)	\
63 	{								\
64 		.name = _name,						\
65 		.offset = _offset,					\
66 		.shift = _shift,					\
67 		.mask = _mask,						\
68 		.iddq = _iddq,						\
69 		.num_funcs = ARRAY_SIZE(tegra210_##_funcs##_functions),	\
70 		.funcs = tegra210_##_funcs##_functions,			\
71 	}
72 
73 static const struct tegra_xusb_padctl_lane tegra210_lanes[] = {
74 	TEGRA210_LANE("otg-0",     0x004,  0, 0x3, 0, otg),
75 	TEGRA210_LANE("otg-1",     0x004,  2, 0x3, 0, otg),
76 	TEGRA210_LANE("otg-2",     0x004,  4, 0x3, 0, otg),
77 	TEGRA210_LANE("otg-3",     0x004,  6, 0x3, 0, otg),
78 	TEGRA210_LANE("usb2-bias", 0x004, 18, 0x3, 0, otg),
79 	TEGRA210_LANE("hsic-0",    0x004, 14, 0x1, 0, usb),
80 	TEGRA210_LANE("hsic-1",    0x004, 15, 0x1, 0, usb),
81 	TEGRA210_LANE("pcie-0",    0x028, 12, 0x3, 1, pci),
82 	TEGRA210_LANE("pcie-1",    0x028, 14, 0x3, 2, pci),
83 	TEGRA210_LANE("pcie-2",    0x028, 16, 0x3, 3, pci),
84 	TEGRA210_LANE("pcie-3",    0x028, 18, 0x3, 4, pci),
85 	TEGRA210_LANE("pcie-4",    0x028, 20, 0x3, 5, pci),
86 	TEGRA210_LANE("pcie-5",    0x028, 22, 0x3, 6, pci),
87 	TEGRA210_LANE("pcie-6",    0x028, 24, 0x3, 7, pci),
88 	TEGRA210_LANE("sata-0",    0x028, 30, 0x3, 8, pci),
89 };
90 
91 #define XUSB_PADCTL_ELPG_PROGRAM 0x024
92 #define  XUSB_PADCTL_ELPG_PROGRAM_AUX_MUX_LP0_VCORE_DOWN (1 << 31)
93 #define  XUSB_PADCTL_ELPG_PROGRAM_AUX_MUX_LP0_CLAMP_EN_EARLY (1 << 30)
94 #define  XUSB_PADCTL_ELPG_PROGRAM_AUX_MUX_LP0_CLAMP_EN (1 << 29)
95 
96 static int tegra_xusb_padctl_enable(struct tegra_xusb_padctl *padctl)
97 {
98 	u32 value;
99 
100 	if (padctl->enable++ > 0)
101 		return 0;
102 
103 	value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM);
104 	value &= ~XUSB_PADCTL_ELPG_PROGRAM_AUX_MUX_LP0_CLAMP_EN;
105 	padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM);
106 
107 	udelay(100);
108 
109 	value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM);
110 	value &= ~XUSB_PADCTL_ELPG_PROGRAM_AUX_MUX_LP0_CLAMP_EN_EARLY;
111 	padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM);
112 
113 	udelay(100);
114 
115 	value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM);
116 	value &= ~XUSB_PADCTL_ELPG_PROGRAM_AUX_MUX_LP0_VCORE_DOWN;
117 	padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM);
118 
119 	return 0;
120 }
121 
122 static int tegra_xusb_padctl_disable(struct tegra_xusb_padctl *padctl)
123 {
124 	u32 value;
125 
126 	if (padctl->enable == 0) {
127 		pr_err("unbalanced enable/disable");
128 		return 0;
129 	}
130 
131 	if (--padctl->enable > 0)
132 		return 0;
133 
134 	value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM);
135 	value |= XUSB_PADCTL_ELPG_PROGRAM_AUX_MUX_LP0_VCORE_DOWN;
136 	padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM);
137 
138 	udelay(100);
139 
140 	value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM);
141 	value |= XUSB_PADCTL_ELPG_PROGRAM_AUX_MUX_LP0_CLAMP_EN_EARLY;
142 	padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM);
143 
144 	udelay(100);
145 
146 	value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM);
147 	value |= XUSB_PADCTL_ELPG_PROGRAM_AUX_MUX_LP0_CLAMP_EN;
148 	padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM);
149 
150 	return 0;
151 }
152 
153 static int phy_prepare(struct tegra_xusb_phy *phy)
154 {
155 	int err;
156 
157 	err = tegra_xusb_padctl_enable(phy->padctl);
158 	if (err < 0)
159 		return err;
160 
161 	reset_set_enable(PERIPH_ID_PEX_USB_UPHY, 0);
162 
163 	return 0;
164 }
165 
166 static int phy_unprepare(struct tegra_xusb_phy *phy)
167 {
168 	reset_set_enable(PERIPH_ID_PEX_USB_UPHY, 1);
169 
170 	return tegra_xusb_padctl_disable(phy->padctl);
171 }
172 
173 #define XUSB_PADCTL_UPHY_PLL_P0_CTL1 0x360
174 #define  XUSB_PADCTL_UPHY_PLL_P0_CTL1_FREQ_NDIV_MASK (0xff << 20)
175 #define  XUSB_PADCTL_UPHY_PLL_P0_CTL1_FREQ_NDIV(x) (((x) & 0xff) << 20)
176 #define  XUSB_PADCTL_UPHY_PLL_P0_CTL1_FREQ_MDIV_MASK (0x3 << 16)
177 #define  XUSB_PADCTL_UPHY_PLL_P0_CTL1_LOCKDET_STATUS (1 << 15)
178 #define  XUSB_PADCTL_UPHY_PLL_P0_CTL1_PWR_OVRD (1 << 4)
179 #define  XUSB_PADCTL_UPHY_PLL_P0_CTL1_ENABLE (1 << 3)
180 #define  XUSB_PADCTL_UPHY_PLL_P0_CTL1_SLEEP_MASK (0x3 << 1)
181 #define  XUSB_PADCTL_UPHY_PLL_P0_CTL1_SLEEP(x) (((x) & 0x3) << 1)
182 #define  XUSB_PADCTL_UPHY_PLL_P0_CTL1_IDDQ (1 << 0)
183 
184 #define XUSB_PADCTL_UPHY_PLL_P0_CTL2 0x364
185 #define  XUSB_PADCTL_UPHY_PLL_P0_CTL2_CAL_CTRL_MASK (0xffffff << 4)
186 #define  XUSB_PADCTL_UPHY_PLL_P0_CTL2_CAL_CTRL(x) (((x) & 0xffffff) << 4)
187 #define  XUSB_PADCTL_UPHY_PLL_P0_CTL2_CAL_OVRD (1 << 2)
188 #define  XUSB_PADCTL_UPHY_PLL_P0_CTL2_CAL_DONE (1 << 1)
189 #define  XUSB_PADCTL_UPHY_PLL_P0_CTL2_CAL_EN (1 << 0)
190 
191 #define XUSB_PADCTL_UPHY_PLL_P0_CTL4 0x36c
192 #define  XUSB_PADCTL_UPHY_PLL_P0_CTL4_TXCLKREF_EN (1 << 15)
193 #define  XUSB_PADCTL_UPHY_PLL_P0_CTL4_TXCLKREF_SEL_MASK (0x3 << 12)
194 #define  XUSB_PADCTL_UPHY_PLL_P0_CTL4_TXCLKREF_SEL(x) (((x) & 0x3) << 12)
195 #define  XUSB_PADCTL_UPHY_PLL_P0_CTL4_REFCLKBUF_EN (1 << 8)
196 #define  XUSB_PADCTL_UPHY_PLL_P0_CTL4_REFCLK_SEL_MASK (0xf << 4)
197 
198 #define XUSB_PADCTL_UPHY_PLL_P0_CTL5 0x370
199 #define  XUSB_PADCTL_UPHY_PLL_P0_CTL5_DCO_CTRL_MASK (0xff << 16)
200 #define  XUSB_PADCTL_UPHY_PLL_P0_CTL5_DCO_CTRL(x) (((x) & 0xff) << 16)
201 
202 #define XUSB_PADCTL_UPHY_PLL_P0_CTL8 0x37c
203 #define  XUSB_PADCTL_UPHY_PLL_P0_CTL8_RCAL_DONE (1 << 31)
204 #define  XUSB_PADCTL_UPHY_PLL_P0_CTL8_RCAL_OVRD (1 << 15)
205 #define  XUSB_PADCTL_UPHY_PLL_P0_CTL8_RCAL_CLK_EN (1 << 13)
206 #define  XUSB_PADCTL_UPHY_PLL_P0_CTL8_RCAL_EN (1 << 12)
207 
208 #define CLK_RST_XUSBIO_PLL_CFG0 0x51c
209 #define  CLK_RST_XUSBIO_PLL_CFG0_SEQ_ENABLE (1 << 24)
210 #define  CLK_RST_XUSBIO_PLL_CFG0_PADPLL_SLEEP_IDDQ (1 << 13)
211 #define  CLK_RST_XUSBIO_PLL_CFG0_PADPLL_USE_LOCKDET (1 << 6)
212 #define  CLK_RST_XUSBIO_PLL_CFG0_CLK_ENABLE_SWCTL (1 << 2)
213 #define  CLK_RST_XUSBIO_PLL_CFG0_PADPLL_RESET_SWCTL (1 << 0)
214 
215 static int pcie_phy_enable(struct tegra_xusb_phy *phy)
216 {
217 	struct tegra_xusb_padctl *padctl = phy->padctl;
218 	unsigned long start;
219 	u32 value;
220 
221 	debug("> %s(phy=%p)\n", __func__, phy);
222 
223 	value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL2);
224 	value &= ~XUSB_PADCTL_UPHY_PLL_P0_CTL2_CAL_CTRL_MASK;
225 	value |= XUSB_PADCTL_UPHY_PLL_P0_CTL2_CAL_CTRL(0x136);
226 	padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_P0_CTL2);
227 
228 	value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL5);
229 	value &= ~XUSB_PADCTL_UPHY_PLL_P0_CTL5_DCO_CTRL_MASK;
230 	value |= XUSB_PADCTL_UPHY_PLL_P0_CTL5_DCO_CTRL(0x2a);
231 	padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_P0_CTL5);
232 
233 	value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL1);
234 	value |= XUSB_PADCTL_UPHY_PLL_P0_CTL1_PWR_OVRD;
235 	padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_P0_CTL1);
236 
237 	value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL2);
238 	value |= XUSB_PADCTL_UPHY_PLL_P0_CTL2_CAL_OVRD;
239 	padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_P0_CTL2);
240 
241 	value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL8);
242 	value |= XUSB_PADCTL_UPHY_PLL_P0_CTL8_RCAL_OVRD;
243 	padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_P0_CTL8);
244 
245 	value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL4);
246 	value &= ~XUSB_PADCTL_UPHY_PLL_P0_CTL4_TXCLKREF_SEL_MASK;
247 	value &= ~XUSB_PADCTL_UPHY_PLL_P0_CTL4_REFCLK_SEL_MASK;
248 	value |= XUSB_PADCTL_UPHY_PLL_P0_CTL4_TXCLKREF_SEL(2);
249 	value |= XUSB_PADCTL_UPHY_PLL_P0_CTL4_TXCLKREF_EN;
250 	padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_P0_CTL4);
251 
252 	value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL1);
253 	value &= ~XUSB_PADCTL_UPHY_PLL_P0_CTL1_FREQ_MDIV_MASK;
254 	value &= ~XUSB_PADCTL_UPHY_PLL_P0_CTL1_FREQ_NDIV_MASK;
255 	value |= XUSB_PADCTL_UPHY_PLL_P0_CTL1_FREQ_NDIV(25);
256 	padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_P0_CTL1);
257 
258 	value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL1);
259 	value &= ~XUSB_PADCTL_UPHY_PLL_P0_CTL1_IDDQ;
260 	padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_P0_CTL1);
261 
262 	value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL1);
263 	value &= ~XUSB_PADCTL_UPHY_PLL_P0_CTL1_SLEEP_MASK;
264 	padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_P0_CTL1);
265 
266 	udelay(1);
267 
268 	value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL4);
269 	value |= XUSB_PADCTL_UPHY_PLL_P0_CTL4_REFCLKBUF_EN;
270 	padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_P0_CTL4);
271 
272 	value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL2);
273 	value |= XUSB_PADCTL_UPHY_PLL_P0_CTL2_CAL_EN;
274 	padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_P0_CTL2);
275 
276 	debug("  waiting for calibration\n");
277 
278 	start = get_timer(0);
279 
280 	while (get_timer(start) < 250) {
281 		value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL2);
282 		if (value & XUSB_PADCTL_UPHY_PLL_P0_CTL2_CAL_DONE)
283 			break;
284 	}
285 	if (!(value & XUSB_PADCTL_UPHY_PLL_P0_CTL2_CAL_DONE)) {
286 		debug("  timeout\n");
287 		return -ETIMEDOUT;
288 	}
289 	debug("  done\n");
290 
291 	value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL2);
292 	value &= ~XUSB_PADCTL_UPHY_PLL_P0_CTL2_CAL_EN;
293 	padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_P0_CTL2);
294 
295 	debug("  waiting for calibration to stop\n");
296 
297 	start = get_timer(0);
298 
299 	while (get_timer(start) < 250) {
300 		value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL2);
301 		if ((value & XUSB_PADCTL_UPHY_PLL_P0_CTL2_CAL_DONE) == 0)
302 			break;
303 	}
304 	if (value & XUSB_PADCTL_UPHY_PLL_P0_CTL2_CAL_DONE) {
305 		debug("  timeout\n");
306 		return -ETIMEDOUT;
307 	}
308 	debug("  done\n");
309 
310 	value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL1);
311 	value |= XUSB_PADCTL_UPHY_PLL_P0_CTL1_ENABLE;
312 	padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_P0_CTL1);
313 
314 	debug("  waiting for PLL to lock...\n");
315 	start = get_timer(0);
316 
317 	while (get_timer(start) < 250) {
318 		value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL1);
319 		if (value & XUSB_PADCTL_UPHY_PLL_P0_CTL1_LOCKDET_STATUS)
320 			break;
321 	}
322 	if (!(value & XUSB_PADCTL_UPHY_PLL_P0_CTL1_LOCKDET_STATUS)) {
323 		debug("  timeout\n");
324 		return -ETIMEDOUT;
325 	}
326 	debug("  done\n");
327 
328 	value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL8);
329 	value |= XUSB_PADCTL_UPHY_PLL_P0_CTL8_RCAL_CLK_EN;
330 	value |= XUSB_PADCTL_UPHY_PLL_P0_CTL8_RCAL_EN;
331 	padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_P0_CTL8);
332 
333 	debug("  waiting for register calibration...\n");
334 	start = get_timer(0);
335 
336 	while (get_timer(start) < 250) {
337 		value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL8);
338 		if (value & XUSB_PADCTL_UPHY_PLL_P0_CTL8_RCAL_DONE)
339 			break;
340 	}
341 	if (!(value & XUSB_PADCTL_UPHY_PLL_P0_CTL8_RCAL_DONE)) {
342 		debug("  timeout\n");
343 		return -ETIMEDOUT;
344 	}
345 	debug("  done\n");
346 
347 	value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL8);
348 	value &= ~XUSB_PADCTL_UPHY_PLL_P0_CTL8_RCAL_EN;
349 	padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_P0_CTL8);
350 
351 	debug("  waiting for register calibration to stop...\n");
352 	start = get_timer(0);
353 
354 	while (get_timer(start) < 250) {
355 		value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL8);
356 		if ((value & XUSB_PADCTL_UPHY_PLL_P0_CTL8_RCAL_DONE) == 0)
357 			break;
358 	}
359 	if (value & XUSB_PADCTL_UPHY_PLL_P0_CTL8_RCAL_DONE) {
360 		debug("  timeout\n");
361 		return -ETIMEDOUT;
362 	}
363 	debug("  done\n");
364 
365 	value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL8);
366 	value &= ~XUSB_PADCTL_UPHY_PLL_P0_CTL8_RCAL_CLK_EN;
367 	padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_P0_CTL8);
368 
369 	value = readl(NV_PA_CLK_RST_BASE + CLK_RST_XUSBIO_PLL_CFG0);
370 	value &= ~CLK_RST_XUSBIO_PLL_CFG0_PADPLL_RESET_SWCTL;
371 	value &= ~CLK_RST_XUSBIO_PLL_CFG0_CLK_ENABLE_SWCTL;
372 	value |= CLK_RST_XUSBIO_PLL_CFG0_PADPLL_USE_LOCKDET;
373 	value |= CLK_RST_XUSBIO_PLL_CFG0_PADPLL_SLEEP_IDDQ;
374 	writel(value, NV_PA_CLK_RST_BASE + CLK_RST_XUSBIO_PLL_CFG0);
375 
376 	value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL1);
377 	value &= ~XUSB_PADCTL_UPHY_PLL_P0_CTL1_PWR_OVRD;
378 	padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_P0_CTL1);
379 
380 	value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL2);
381 	value &= ~XUSB_PADCTL_UPHY_PLL_P0_CTL2_CAL_OVRD;
382 	padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_P0_CTL2);
383 
384 	value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL8);
385 	value &= ~XUSB_PADCTL_UPHY_PLL_P0_CTL8_RCAL_OVRD;
386 	padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_P0_CTL8);
387 
388 	udelay(1);
389 
390 	value = readl(NV_PA_CLK_RST_BASE + CLK_RST_XUSBIO_PLL_CFG0);
391 	value |= CLK_RST_XUSBIO_PLL_CFG0_SEQ_ENABLE;
392 	writel(value, NV_PA_CLK_RST_BASE + CLK_RST_XUSBIO_PLL_CFG0);
393 
394 	debug("< %s()\n", __func__);
395 	return 0;
396 }
397 
398 static int pcie_phy_disable(struct tegra_xusb_phy *phy)
399 {
400 	return 0;
401 }
402 
403 static const struct tegra_xusb_phy_ops pcie_phy_ops = {
404 	.prepare = phy_prepare,
405 	.enable = pcie_phy_enable,
406 	.disable = pcie_phy_disable,
407 	.unprepare = phy_unprepare,
408 };
409 
410 static struct tegra_xusb_phy tegra210_phys[] = {
411 	{
412 		.type = TEGRA_XUSB_PADCTL_PCIE,
413 		.ops = &pcie_phy_ops,
414 		.padctl = &padctl,
415 	},
416 };
417 
418 static const struct tegra_xusb_padctl_soc tegra210_socdata = {
419 	.lanes = tegra210_lanes,
420 	.num_lanes = ARRAY_SIZE(tegra210_lanes),
421 	.functions = tegra210_functions,
422 	.num_functions = ARRAY_SIZE(tegra210_functions),
423 	.phys = tegra210_phys,
424 	.num_phys = ARRAY_SIZE(tegra210_phys),
425 };
426 
427 void tegra_xusb_padctl_init(void)
428 {
429 	ofnode nodes[1];
430 	int count = 0;
431 	int ret;
432 
433 	debug("%s: start\n", __func__);
434 	if (of_live_active()) {
435 		struct device_node *np = of_find_compatible_node(NULL, NULL,
436 						"nvidia,tegra210-xusb-padctl");
437 
438 		debug("np=%p\n", np);
439 		if (np) {
440 			nodes[0] = np_to_ofnode(np);
441 			count = 1;
442 		}
443 	} else {
444 		int node_offsets[1];
445 		int i;
446 
447 		count = fdtdec_find_aliases_for_id(gd->fdt_blob, "padctl",
448 				COMPAT_NVIDIA_TEGRA210_XUSB_PADCTL,
449 				node_offsets, ARRAY_SIZE(node_offsets));
450 		for (i = 0; i < count; i++)
451 			nodes[i] = offset_to_ofnode(node_offsets[i]);
452 	}
453 
454 	ret = tegra_xusb_process_nodes(nodes, count, &tegra210_socdata);
455 	debug("%s: done, ret=%d\n", __func__, ret);
456 }
457