1 /* 2 * (C) Copyright 2013-2015 3 * NVIDIA Corporation <www.nvidia.com> 4 * 5 * SPDX-License-Identifier: GPL-2.0+ 6 */ 7 8 /* Tegra210 Clock control functions */ 9 10 #include <common.h> 11 #include <errno.h> 12 #include <asm/io.h> 13 #include <asm/arch/clock.h> 14 #include <asm/arch/sysctr.h> 15 #include <asm/arch/tegra.h> 16 #include <asm/arch-tegra/clk_rst.h> 17 #include <asm/arch-tegra/timer.h> 18 #include <div64.h> 19 #include <fdtdec.h> 20 21 /* 22 * Clock types that we can use as a source. The Tegra210 has muxes for the 23 * peripheral clocks, and in most cases there are four options for the clock 24 * source. This gives us a clock 'type' and exploits what commonality exists 25 * in the device. 26 * 27 * Letters are obvious, except for T which means CLK_M, and S which means the 28 * clock derived from 32KHz. Beware that CLK_M (also called OSC in the 29 * datasheet) and PLL_M are different things. The former is the basic 30 * clock supplied to the SOC from an external oscillator. The latter is the 31 * memory clock PLL. 32 * 33 * See definitions in clock_id in the header file. 34 */ 35 enum clock_type_id { 36 CLOCK_TYPE_AXPT, /* PLL_A, PLL_X, PLL_P, CLK_M */ 37 CLOCK_TYPE_MCPA, /* and so on */ 38 CLOCK_TYPE_MCPT, 39 CLOCK_TYPE_PCM, 40 CLOCK_TYPE_PCMT, 41 CLOCK_TYPE_PDCT, 42 CLOCK_TYPE_ACPT, 43 CLOCK_TYPE_ASPTE, 44 CLOCK_TYPE_PMDACD2T, 45 CLOCK_TYPE_PCST, 46 CLOCK_TYPE_DP, 47 48 CLOCK_TYPE_PC2CC3M, 49 CLOCK_TYPE_PC2CC3S_T, 50 CLOCK_TYPE_PC2CC3M_T, 51 CLOCK_TYPE_PC2CC3M_T16, /* PC2CC3M_T, but w/16-bit divisor (I2C) */ 52 CLOCK_TYPE_MC2CC3P_A, 53 CLOCK_TYPE_M, 54 CLOCK_TYPE_MCPTM2C2C3, 55 CLOCK_TYPE_PC2CC3T_S, 56 CLOCK_TYPE_AC2CC3P_TS2, 57 CLOCK_TYPE_PC01C00_C42C41TC40, 58 59 CLOCK_TYPE_COUNT, 60 CLOCK_TYPE_NONE = -1, /* invalid clock type */ 61 }; 62 63 enum { 64 CLOCK_MAX_MUX = 8 /* number of source options for each clock */ 65 }; 66 67 /* 68 * Clock source mux for each clock type. This just converts our enum into 69 * a list of mux sources for use by the code. 70 * 71 * Note: 72 * The extra column in each clock source array is used to store the mask 73 * bits in its register for the source. 74 */ 75 #define CLK(x) CLOCK_ID_ ## x 76 static enum clock_id clock_source[CLOCK_TYPE_COUNT][CLOCK_MAX_MUX+1] = { 77 { CLK(AUDIO), CLK(XCPU), CLK(PERIPH), CLK(OSC), 78 CLK(NONE), CLK(NONE), CLK(NONE), CLK(NONE), 79 MASK_BITS_31_30}, 80 { CLK(MEMORY), CLK(CGENERAL), CLK(PERIPH), CLK(AUDIO), 81 CLK(NONE), CLK(NONE), CLK(NONE), CLK(NONE), 82 MASK_BITS_31_30}, 83 { CLK(MEMORY), CLK(CGENERAL), CLK(PERIPH), CLK(OSC), 84 CLK(NONE), CLK(NONE), CLK(NONE), CLK(NONE), 85 MASK_BITS_31_30}, 86 { CLK(PERIPH), CLK(CGENERAL), CLK(MEMORY), CLK(NONE), 87 CLK(NONE), CLK(NONE), CLK(NONE), CLK(NONE), 88 MASK_BITS_31_30}, 89 { CLK(PERIPH), CLK(CGENERAL), CLK(MEMORY), CLK(OSC), 90 CLK(NONE), CLK(NONE), CLK(NONE), CLK(NONE), 91 MASK_BITS_31_30}, 92 { CLK(PERIPH), CLK(DISPLAY), CLK(CGENERAL), CLK(OSC), 93 CLK(NONE), CLK(NONE), CLK(NONE), CLK(NONE), 94 MASK_BITS_31_30}, 95 { CLK(AUDIO), CLK(CGENERAL), CLK(PERIPH), CLK(OSC), 96 CLK(NONE), CLK(NONE), CLK(NONE), CLK(NONE), 97 MASK_BITS_31_30}, 98 { CLK(AUDIO), CLK(SFROM32KHZ), CLK(PERIPH), CLK(OSC), 99 CLK(EPCI), CLK(NONE), CLK(NONE), CLK(NONE), 100 MASK_BITS_31_29}, 101 { CLK(PERIPH), CLK(MEMORY), CLK(DISPLAY), CLK(AUDIO), 102 CLK(CGENERAL), CLK(DISPLAY2), CLK(OSC), CLK(NONE), 103 MASK_BITS_31_29}, 104 { CLK(PERIPH), CLK(CGENERAL), CLK(SFROM32KHZ), CLK(OSC), 105 CLK(NONE), CLK(NONE), CLK(NONE), CLK(NONE), 106 MASK_BITS_31_28}, 107 /* CLOCK_TYPE_DP */ 108 { CLK(NONE), CLK(NONE), CLK(NONE), CLK(NONE), 109 CLK(NONE), CLK(NONE), CLK(NONE), CLK(NONE), 110 MASK_BITS_31_28}, 111 112 /* Additional clock types on Tegra114+ */ 113 /* CLOCK_TYPE_PC2CC3M */ 114 { CLK(PERIPH), CLK(CGENERAL2), CLK(CGENERAL), CLK(CGENERAL3), 115 CLK(MEMORY), CLK(NONE), CLK(NONE), CLK(NONE), 116 MASK_BITS_31_29}, 117 /* CLOCK_TYPE_PC2CC3S_T */ 118 { CLK(PERIPH), CLK(CGENERAL2), CLK(CGENERAL), CLK(CGENERAL3), 119 CLK(SFROM32KHZ), CLK(NONE), CLK(OSC), CLK(NONE), 120 MASK_BITS_31_29}, 121 /* CLOCK_TYPE_PC2CC3M_T */ 122 { CLK(PERIPH), CLK(CGENERAL2), CLK(CGENERAL), CLK(CGENERAL3), 123 CLK(MEMORY), CLK(NONE), CLK(OSC), CLK(NONE), 124 MASK_BITS_31_29}, 125 /* CLOCK_TYPE_PC2CC3M_T, w/16-bit divisor (I2C) */ 126 { CLK(PERIPH), CLK(CGENERAL2), CLK(CGENERAL), CLK(CGENERAL3), 127 CLK(MEMORY), CLK(NONE), CLK(OSC), CLK(NONE), 128 MASK_BITS_31_29}, 129 /* CLOCK_TYPE_MC2CC3P_A */ 130 { CLK(MEMORY), CLK(CGENERAL2), CLK(CGENERAL), CLK(CGENERAL3), 131 CLK(PERIPH), CLK(NONE), CLK(AUDIO), CLK(NONE), 132 MASK_BITS_31_29}, 133 /* CLOCK_TYPE_M */ 134 { CLK(MEMORY), CLK(NONE), CLK(NONE), CLK(NONE), 135 CLK(NONE), CLK(NONE), CLK(NONE), CLK(NONE), 136 MASK_BITS_31_30}, 137 /* CLOCK_TYPE_MCPTM2C2C3 */ 138 { CLK(MEMORY), CLK(CGENERAL), CLK(PERIPH), CLK(OSC), 139 CLK(MEMORY2), CLK(CGENERAL2), CLK(CGENERAL3), CLK(NONE), 140 MASK_BITS_31_29}, 141 /* CLOCK_TYPE_PC2CC3T_S */ 142 { CLK(PERIPH), CLK(CGENERAL2), CLK(CGENERAL), CLK(CGENERAL3), 143 CLK(OSC), CLK(NONE), CLK(SFROM32KHZ), CLK(NONE), 144 MASK_BITS_31_29}, 145 /* CLOCK_TYPE_AC2CC3P_TS2 */ 146 { CLK(AUDIO), CLK(CGENERAL2), CLK(CGENERAL), CLK(CGENERAL3), 147 CLK(PERIPH), CLK(NONE), CLK(OSC), CLK(SRC2), 148 MASK_BITS_31_29}, 149 /* CLOCK_TYPE_PC01C00_C42C41TC40 */ 150 { CLK(PERIPH), CLK(CGENERAL_1), CLK(CGENERAL_0), CLK(NONE), 151 CLK(CGENERAL4_2), CLK(CGENERAL4_1), CLK(OSC), CLK(CGENERAL4_0), 152 MASK_BITS_31_29}, 153 }; 154 155 /* 156 * Clock type for each peripheral clock source. We put the name in each 157 * record just so it is easy to match things up 158 */ 159 #define TYPE(name, type) type 160 static enum clock_type_id clock_periph_type[PERIPHC_COUNT] = { 161 /* 0x00 */ 162 TYPE(PERIPHC_I2S2, CLOCK_TYPE_AXPT), 163 TYPE(PERIPHC_I2S3, CLOCK_TYPE_AXPT), 164 TYPE(PERIPHC_SPDIF_OUT, CLOCK_TYPE_AXPT), 165 TYPE(PERIPHC_SPDIF_IN, CLOCK_TYPE_PC2CC3M), 166 TYPE(PERIPHC_PWM, CLOCK_TYPE_PC2CC3S_T), 167 TYPE(PERIPHC_05h, CLOCK_TYPE_NONE), 168 TYPE(PERIPHC_SBC2, CLOCK_TYPE_PC2CC3M_T), 169 TYPE(PERIPHC_SBC3, CLOCK_TYPE_PC2CC3M_T), 170 171 /* 0x08 */ 172 TYPE(PERIPHC_08h, CLOCK_TYPE_NONE), 173 TYPE(PERIPHC_I2C1, CLOCK_TYPE_PC2CC3M_T16), 174 TYPE(PERIPHC_I2C5, CLOCK_TYPE_PC2CC3M_T16), 175 TYPE(PERIPHC_0bh, CLOCK_TYPE_NONE), 176 TYPE(PERIPHC_0ch, CLOCK_TYPE_NONE), 177 TYPE(PERIPHC_SBC1, CLOCK_TYPE_PC2CC3M_T), 178 TYPE(PERIPHC_DISP1, CLOCK_TYPE_PMDACD2T), 179 TYPE(PERIPHC_DISP2, CLOCK_TYPE_PMDACD2T), 180 181 /* 0x10 */ 182 TYPE(PERIPHC_10h, CLOCK_TYPE_NONE), 183 TYPE(PERIPHC_11h, CLOCK_TYPE_NONE), 184 TYPE(PERIPHC_VI, CLOCK_TYPE_MC2CC3P_A), 185 TYPE(PERIPHC_13h, CLOCK_TYPE_NONE), 186 TYPE(PERIPHC_SDMMC1, CLOCK_TYPE_PC2CC3M_T), 187 TYPE(PERIPHC_SDMMC2, CLOCK_TYPE_PC2CC3M_T), 188 TYPE(PERIPHC_16h, CLOCK_TYPE_NONE), 189 TYPE(PERIPHC_17h, CLOCK_TYPE_NONE), 190 191 /* 0x18 */ 192 TYPE(PERIPHC_18h, CLOCK_TYPE_NONE), 193 TYPE(PERIPHC_SDMMC4, CLOCK_TYPE_PC2CC3M_T), 194 TYPE(PERIPHC_VFIR, CLOCK_TYPE_PC2CC3M_T), 195 TYPE(PERIPHC_1Bh, CLOCK_TYPE_NONE), 196 TYPE(PERIPHC_1Ch, CLOCK_TYPE_NONE), 197 TYPE(PERIPHC_HSI, CLOCK_TYPE_PC2CC3M_T), 198 TYPE(PERIPHC_UART1, CLOCK_TYPE_PC2CC3M_T), 199 TYPE(PERIPHC_UART2, CLOCK_TYPE_PC2CC3M_T), 200 201 /* 0x20 */ 202 TYPE(PERIPHC_HOST1X, CLOCK_TYPE_MC2CC3P_A), 203 TYPE(PERIPHC_21h, CLOCK_TYPE_NONE), 204 TYPE(PERIPHC_22h, CLOCK_TYPE_NONE), 205 TYPE(PERIPHC_23h, CLOCK_TYPE_NONE), 206 TYPE(PERIPHC_24h, CLOCK_TYPE_NONE), 207 TYPE(PERIPHC_25h, CLOCK_TYPE_NONE), 208 TYPE(PERIPHC_I2C2, CLOCK_TYPE_PC2CC3M_T16), 209 TYPE(PERIPHC_EMC, CLOCK_TYPE_MCPTM2C2C3), 210 211 /* 0x28 */ 212 TYPE(PERIPHC_UART3, CLOCK_TYPE_PC2CC3M_T), 213 TYPE(PERIPHC_29h, CLOCK_TYPE_NONE), 214 TYPE(PERIPHC_VI_SENSOR, CLOCK_TYPE_MC2CC3P_A), 215 TYPE(PERIPHC_2bh, CLOCK_TYPE_NONE), 216 TYPE(PERIPHC_2ch, CLOCK_TYPE_NONE), 217 TYPE(PERIPHC_SBC4, CLOCK_TYPE_PC2CC3M_T), 218 TYPE(PERIPHC_I2C3, CLOCK_TYPE_PC2CC3M_T16), 219 TYPE(PERIPHC_SDMMC3, CLOCK_TYPE_PC2CC3M_T), 220 221 /* 0x30 */ 222 TYPE(PERIPHC_UART4, CLOCK_TYPE_PC2CC3M_T), 223 TYPE(PERIPHC_UART5, CLOCK_TYPE_PC2CC3M_T), 224 TYPE(PERIPHC_VDE, CLOCK_TYPE_PC2CC3M_T), 225 TYPE(PERIPHC_OWR, CLOCK_TYPE_PC2CC3M_T), 226 TYPE(PERIPHC_NOR, CLOCK_TYPE_PC2CC3M_T), 227 TYPE(PERIPHC_CSITE, CLOCK_TYPE_PC2CC3M_T), 228 TYPE(PERIPHC_I2S1, CLOCK_TYPE_AXPT), 229 TYPE(PERIPHC_DTV, CLOCK_TYPE_NONE), 230 231 /* 0x38 */ 232 TYPE(PERIPHC_38h, CLOCK_TYPE_NONE), 233 TYPE(PERIPHC_39h, CLOCK_TYPE_NONE), 234 TYPE(PERIPHC_3ah, CLOCK_TYPE_NONE), 235 TYPE(PERIPHC_3bh, CLOCK_TYPE_NONE), 236 TYPE(PERIPHC_MSENC, CLOCK_TYPE_MC2CC3P_A), 237 TYPE(PERIPHC_TSEC, CLOCK_TYPE_PC2CC3M_T), 238 TYPE(PERIPHC_3eh, CLOCK_TYPE_NONE), 239 TYPE(PERIPHC_OSC, CLOCK_TYPE_NONE), 240 241 /* 0x40 */ 242 TYPE(PERIPHC_40h, CLOCK_TYPE_NONE), /* start with 0x3b0 */ 243 TYPE(PERIPHC_MSELECT, CLOCK_TYPE_PC2CC3M_T), 244 TYPE(PERIPHC_TSENSOR, CLOCK_TYPE_PC2CC3T_S), 245 TYPE(PERIPHC_I2S4, CLOCK_TYPE_AXPT), 246 TYPE(PERIPHC_I2S5, CLOCK_TYPE_AXPT), 247 TYPE(PERIPHC_I2C4, CLOCK_TYPE_PC2CC3M_T16), 248 TYPE(PERIPHC_SBC5, CLOCK_TYPE_PC2CC3M_T), 249 TYPE(PERIPHC_SBC6, CLOCK_TYPE_PC2CC3M_T), 250 251 /* 0x48 */ 252 TYPE(PERIPHC_AUDIO, CLOCK_TYPE_AC2CC3P_TS2), 253 TYPE(PERIPHC_49h, CLOCK_TYPE_NONE), 254 TYPE(PERIPHC_4ah, CLOCK_TYPE_NONE), 255 TYPE(PERIPHC_4bh, CLOCK_TYPE_NONE), 256 TYPE(PERIPHC_4ch, CLOCK_TYPE_NONE), 257 TYPE(PERIPHC_HDA2CODEC2X, CLOCK_TYPE_PC2CC3M_T), 258 TYPE(PERIPHC_ACTMON, CLOCK_TYPE_PC2CC3S_T), 259 TYPE(PERIPHC_EXTPERIPH1, CLOCK_TYPE_ASPTE), 260 261 /* 0x50 */ 262 TYPE(PERIPHC_EXTPERIPH2, CLOCK_TYPE_ASPTE), 263 TYPE(PERIPHC_EXTPERIPH3, CLOCK_TYPE_ASPTE), 264 TYPE(PERIPHC_52h, CLOCK_TYPE_NONE), 265 TYPE(PERIPHC_I2CSLOW, CLOCK_TYPE_PC2CC3S_T), 266 TYPE(PERIPHC_SYS, CLOCK_TYPE_NONE), 267 TYPE(PERIPHC_55h, CLOCK_TYPE_NONE), 268 TYPE(PERIPHC_56h, CLOCK_TYPE_NONE), 269 TYPE(PERIPHC_57h, CLOCK_TYPE_NONE), 270 271 /* 0x58 */ 272 TYPE(PERIPHC_58h, CLOCK_TYPE_NONE), 273 TYPE(PERIPHC_59h, CLOCK_TYPE_NONE), 274 TYPE(PERIPHC_5ah, CLOCK_TYPE_NONE), 275 TYPE(PERIPHC_5bh, CLOCK_TYPE_NONE), 276 TYPE(PERIPHC_SATAOOB, CLOCK_TYPE_PCMT), 277 TYPE(PERIPHC_SATA, CLOCK_TYPE_PCMT), 278 TYPE(PERIPHC_HDA, CLOCK_TYPE_PC2CC3M_T), 279 TYPE(PERIPHC_5fh, CLOCK_TYPE_NONE), 280 281 /* 0x60 */ 282 TYPE(PERIPHC_XUSB_CORE_HOST, CLOCK_TYPE_NONE), 283 TYPE(PERIPHC_XUSB_FALCON, CLOCK_TYPE_NONE), 284 TYPE(PERIPHC_XUSB_FS, CLOCK_TYPE_NONE), 285 TYPE(PERIPHC_XUSB_CORE_DEV, CLOCK_TYPE_NONE), 286 TYPE(PERIPHC_XUSB_SS, CLOCK_TYPE_NONE), 287 TYPE(PERIPHC_CILAB, CLOCK_TYPE_NONE), 288 TYPE(PERIPHC_CILCD, CLOCK_TYPE_NONE), 289 TYPE(PERIPHC_CILE, CLOCK_TYPE_NONE), 290 291 /* 0x68 */ 292 TYPE(PERIPHC_DSIA_LP, CLOCK_TYPE_NONE), 293 TYPE(PERIPHC_DSIB_LP, CLOCK_TYPE_NONE), 294 TYPE(PERIPHC_ENTROPY, CLOCK_TYPE_NONE), 295 TYPE(PERIPHC_DVFS_REF, CLOCK_TYPE_NONE), 296 TYPE(PERIPHC_DVFS_SOC, CLOCK_TYPE_NONE), 297 TYPE(PERIPHC_TRACECLKIN, CLOCK_TYPE_NONE), 298 TYPE(PERIPHC_6eh, CLOCK_TYPE_NONE), 299 TYPE(PERIPHC_6fh, CLOCK_TYPE_NONE), 300 301 /* 0x70 */ 302 TYPE(PERIPHC_EMC_LATENCY, CLOCK_TYPE_NONE), 303 TYPE(PERIPHC_SOC_THERM, CLOCK_TYPE_NONE), 304 TYPE(PERIPHC_72h, CLOCK_TYPE_NONE), 305 TYPE(PERIPHC_73h, CLOCK_TYPE_NONE), 306 TYPE(PERIPHC_74h, CLOCK_TYPE_NONE), 307 TYPE(PERIPHC_75h, CLOCK_TYPE_NONE), 308 TYPE(PERIPHC_VI_SENSOR2, CLOCK_TYPE_NONE), 309 TYPE(PERIPHC_I2C6, CLOCK_TYPE_PC2CC3M_T16), 310 311 /* 0x78 */ 312 TYPE(PERIPHC_78h, CLOCK_TYPE_NONE), 313 TYPE(PERIPHC_EMC_DLL, CLOCK_TYPE_MCPTM2C2C3), 314 TYPE(PERIPHC_7ah, CLOCK_TYPE_NONE), 315 TYPE(PERIPHC_CLK72MHZ, CLOCK_TYPE_NONE), 316 TYPE(PERIPHC_7ch, CLOCK_TYPE_NONE), 317 TYPE(PERIPHC_7dh, CLOCK_TYPE_NONE), 318 TYPE(PERIPHC_VIC, CLOCK_TYPE_NONE), 319 TYPE(PERIPHC_7Fh, CLOCK_TYPE_NONE), 320 321 /* 0x80 */ 322 TYPE(PERIPHC_SDMMC_LEGACY_TM, CLOCK_TYPE_NONE), 323 TYPE(PERIPHC_NVDEC, CLOCK_TYPE_NONE), 324 TYPE(PERIPHC_NVJPG, CLOCK_TYPE_NONE), 325 TYPE(PERIPHC_NVENC, CLOCK_TYPE_NONE), 326 TYPE(PERIPHC_84h, CLOCK_TYPE_NONE), 327 TYPE(PERIPHC_85h, CLOCK_TYPE_NONE), 328 TYPE(PERIPHC_86h, CLOCK_TYPE_NONE), 329 TYPE(PERIPHC_87h, CLOCK_TYPE_NONE), 330 331 /* 0x88 */ 332 TYPE(PERIPHC_88h, CLOCK_TYPE_NONE), 333 TYPE(PERIPHC_89h, CLOCK_TYPE_NONE), 334 TYPE(PERIPHC_DMIC3, CLOCK_TYPE_NONE), 335 TYPE(PERIPHC_APE, CLOCK_TYPE_NONE), 336 TYPE(PERIPHC_QSPI, CLOCK_TYPE_PC01C00_C42C41TC40), 337 TYPE(PERIPHC_VI_I2C, CLOCK_TYPE_NONE), 338 TYPE(PERIPHC_USB2_HSIC_TRK, CLOCK_TYPE_NONE), 339 TYPE(PERIPHC_PEX_SATA_USB_RX_BYP, CLOCK_TYPE_NONE), 340 341 /* 0x90 */ 342 TYPE(PERIPHC_MAUD, CLOCK_TYPE_NONE), 343 TYPE(PERIPHC_TSECB, CLOCK_TYPE_NONE), 344 }; 345 346 /* 347 * This array translates a periph_id to a periphc_internal_id 348 * 349 * Not present/matched up: 350 * uint vi_sensor; _VI_SENSOR_0, 0x1A8 351 * SPDIF - which is both 0x08 and 0x0c 352 * 353 */ 354 #define NONE(name) (-1) 355 #define OFFSET(name, value) PERIPHC_ ## name 356 #define INTERNAL_ID(id) (id & 0x000000ff) 357 static s8 periph_id_to_internal_id[PERIPH_ID_COUNT] = { 358 /* Low word: 31:0 */ 359 NONE(CPU), 360 NONE(COP), 361 NONE(TRIGSYS), 362 NONE(ISPB), 363 NONE(RESERVED4), 364 NONE(TMR), 365 PERIPHC_UART1, 366 PERIPHC_UART2, /* and vfir 0x68 */ 367 368 /* 8 */ 369 NONE(GPIO), 370 PERIPHC_SDMMC2, 371 PERIPHC_SPDIF_IN, 372 PERIPHC_I2S2, 373 PERIPHC_I2C1, 374 NONE(RESERVED13), 375 PERIPHC_SDMMC1, 376 PERIPHC_SDMMC4, 377 378 /* 16 */ 379 NONE(TCW), 380 PERIPHC_PWM, 381 PERIPHC_I2S3, 382 NONE(RESERVED19), 383 PERIPHC_VI, 384 NONE(RESERVED21), 385 NONE(USBD), 386 NONE(ISP), 387 388 /* 24 */ 389 NONE(RESERVED24), 390 NONE(RESERVED25), 391 PERIPHC_DISP2, 392 PERIPHC_DISP1, 393 PERIPHC_HOST1X, 394 NONE(VCP), 395 PERIPHC_I2S1, 396 NONE(CACHE2), 397 398 /* Middle word: 63:32 */ 399 NONE(MEM), 400 NONE(AHBDMA), 401 NONE(APBDMA), 402 NONE(RESERVED35), 403 NONE(RESERVED36), 404 NONE(STAT_MON), 405 NONE(RESERVED38), 406 NONE(FUSE), 407 408 /* 40 */ 409 NONE(KFUSE), 410 PERIPHC_SBC1, /* SBCx = SPIx */ 411 PERIPHC_NOR, 412 NONE(RESERVED43), 413 PERIPHC_SBC2, 414 NONE(XIO), 415 PERIPHC_SBC3, 416 PERIPHC_I2C5, 417 418 /* 48 */ 419 NONE(DSI), 420 NONE(RESERVED49), 421 PERIPHC_HSI, 422 NONE(RESERVED51), 423 NONE(CSI), 424 NONE(RESERVED53), 425 PERIPHC_I2C2, 426 PERIPHC_UART3, 427 428 /* 56 */ 429 NONE(MIPI_CAL), 430 PERIPHC_EMC, 431 NONE(USB2), 432 NONE(USB3), 433 NONE(RESERVED60), 434 PERIPHC_VDE, 435 NONE(BSEA), 436 NONE(BSEV), 437 438 /* Upper word 95:64 */ 439 NONE(RESERVED64), 440 PERIPHC_UART4, 441 PERIPHC_UART5, 442 PERIPHC_I2C3, 443 PERIPHC_SBC4, 444 PERIPHC_SDMMC3, 445 NONE(PCIE), 446 PERIPHC_OWR, 447 448 /* 72 */ 449 NONE(AFI), 450 PERIPHC_CSITE, 451 NONE(PCIEXCLK), 452 NONE(AVPUCQ), 453 NONE(LA), 454 NONE(TRACECLKIN), 455 NONE(SOC_THERM), 456 NONE(DTV), 457 458 /* 80 */ 459 NONE(RESERVED80), 460 PERIPHC_I2CSLOW, 461 NONE(DSIB), 462 PERIPHC_TSEC, 463 NONE(RESERVED84), 464 NONE(RESERVED85), 465 NONE(RESERVED86), 466 NONE(EMUCIF), 467 468 /* 88 */ 469 NONE(RESERVED88), 470 NONE(XUSB_HOST), 471 NONE(RESERVED90), 472 PERIPHC_MSENC, 473 NONE(RESERVED92), 474 NONE(RESERVED93), 475 NONE(RESERVED94), 476 NONE(XUSB_DEV), 477 478 /* V word: 31:0 */ 479 NONE(CPUG), 480 NONE(CPULP), 481 NONE(V_RESERVED2), 482 PERIPHC_MSELECT, 483 NONE(V_RESERVED4), 484 PERIPHC_I2S4, 485 PERIPHC_I2S5, 486 PERIPHC_I2C4, 487 488 /* 104 */ 489 PERIPHC_SBC5, 490 PERIPHC_SBC6, 491 PERIPHC_AUDIO, 492 NONE(APBIF), 493 NONE(V_RESERVED12), 494 NONE(V_RESERVED13), 495 NONE(V_RESERVED14), 496 PERIPHC_HDA2CODEC2X, 497 498 /* 112 */ 499 NONE(ATOMICS), 500 NONE(V_RESERVED17), 501 NONE(V_RESERVED18), 502 NONE(V_RESERVED19), 503 NONE(V_RESERVED20), 504 NONE(V_RESERVED21), 505 NONE(V_RESERVED22), 506 PERIPHC_ACTMON, 507 508 /* 120 */ 509 NONE(EXTPERIPH1), 510 NONE(EXTPERIPH2), 511 NONE(EXTPERIPH3), 512 NONE(OOB), 513 PERIPHC_SATA, 514 PERIPHC_HDA, 515 NONE(TZRAM), 516 NONE(SE), 517 518 /* W word: 31:0 */ 519 NONE(HDA2HDMICODEC), 520 NONE(SATACOLD), 521 NONE(W_RESERVED2), 522 NONE(W_RESERVED3), 523 NONE(W_RESERVED4), 524 NONE(W_RESERVED5), 525 NONE(W_RESERVED6), 526 NONE(W_RESERVED7), 527 528 /* 136 */ 529 NONE(CEC), 530 NONE(W_RESERVED9), 531 NONE(W_RESERVED10), 532 NONE(W_RESERVED11), 533 NONE(W_RESERVED12), 534 NONE(W_RESERVED13), 535 NONE(XUSB_PADCTL), 536 NONE(W_RESERVED15), 537 538 /* 144 */ 539 NONE(W_RESERVED16), 540 NONE(W_RESERVED17), 541 NONE(W_RESERVED18), 542 NONE(W_RESERVED19), 543 NONE(W_RESERVED20), 544 NONE(ENTROPY), 545 NONE(DDS), 546 NONE(W_RESERVED23), 547 548 /* 152 */ 549 NONE(W_RESERVED24), 550 NONE(W_RESERVED25), 551 NONE(W_RESERVED26), 552 NONE(DVFS), 553 NONE(XUSB_SS), 554 NONE(W_RESERVED29), 555 NONE(W_RESERVED30), 556 NONE(W_RESERVED31), 557 558 /* X word: 31:0 */ 559 NONE(SPARE), 560 NONE(X_RESERVED1), 561 NONE(X_RESERVED2), 562 NONE(X_RESERVED3), 563 NONE(CAM_MCLK), 564 NONE(CAM_MCLK2), 565 PERIPHC_I2C6, 566 NONE(X_RESERVED7), 567 568 /* 168 */ 569 NONE(X_RESERVED8), 570 NONE(X_RESERVED9), 571 NONE(X_RESERVED10), 572 NONE(VIM2_CLK), 573 NONE(X_RESERVED12), 574 NONE(X_RESERVED13), 575 NONE(EMC_DLL), 576 NONE(X_RESERVED15), 577 578 /* 176 */ 579 NONE(X_RESERVED16), 580 NONE(CLK72MHZ), 581 NONE(VIC), 582 NONE(X_RESERVED19), 583 NONE(X_RESERVED20), 584 NONE(DPAUX), 585 NONE(SOR0), 586 NONE(X_RESERVED23), 587 588 /* 184 */ 589 NONE(GPU), 590 NONE(X_RESERVED25), 591 NONE(X_RESERVED26), 592 NONE(X_RESERVED27), 593 NONE(X_RESERVED28), 594 NONE(X_RESERVED29), 595 NONE(X_RESERVED30), 596 NONE(X_RESERVED31), 597 598 /* Y: 192 (192 - 223) */ 599 NONE(Y_RESERVED0), 600 PERIPHC_SDMMC_LEGACY_TM, 601 PERIPHC_NVDEC, 602 PERIPHC_NVJPG, 603 NONE(Y_RESERVED4), 604 PERIPHC_DMIC3, /* 197 */ 605 PERIPHC_APE, /* 198 */ 606 NONE(Y_RESERVED7), 607 608 /* 200 */ 609 NONE(Y_RESERVED8), 610 NONE(Y_RESERVED9), 611 NONE(Y_RESERVED10), 612 NONE(Y_RESERVED11), 613 NONE(Y_RESERVED12), 614 NONE(Y_RESERVED13), 615 NONE(Y_RESERVED14), 616 NONE(Y_RESERVED15), 617 618 /* 208 */ 619 PERIPHC_VI_I2C, /* 208 */ 620 NONE(Y_RESERVED17), 621 NONE(Y_RESERVED18), 622 PERIPHC_QSPI, /* 211 */ 623 NONE(Y_RESERVED20), 624 NONE(Y_RESERVED21), 625 NONE(Y_RESERVED22), 626 NONE(Y_RESERVED23), 627 628 /* 216 */ 629 NONE(Y_RESERVED24), 630 NONE(Y_RESERVED25), 631 NONE(Y_RESERVED26), 632 PERIPHC_NVENC, /* 219 */ 633 NONE(Y_RESERVED28), 634 NONE(Y_RESERVED29), 635 NONE(Y_RESERVED30), 636 NONE(Y_RESERVED31), 637 }; 638 639 /* 640 * PLL divider shift/mask tables for all PLL IDs. 641 */ 642 struct clk_pll_info tegra_pll_info_table[CLOCK_ID_PLL_COUNT] = { 643 /* 644 * NOTE: If kcp_mask/kvco_mask == 0, they're not used in that PLL (PLLC, etc.) 645 * If lock_ena or lock_det are >31, they're not used in that PLL (PLLC, etc.) 646 */ 647 { .m_shift = 0, .m_mask = 0xFF, .n_shift = 10, .n_mask = 0xFF, .p_shift = 20, .p_mask = 0x1F, 648 .lock_ena = 32, .lock_det = 27, .kcp_shift = 0, .kcp_mask = 0, .kvco_shift = 0, .kvco_mask = 0 }, /* PLLC */ 649 { .m_shift = 0, .m_mask = 0xFF, .n_shift = 8, .n_mask = 0xFF, .p_shift = 20, .p_mask = 0x1F, 650 .lock_ena = 4, .lock_det = 27, .kcp_shift = 1, .kcp_mask = 3, .kvco_shift = 0, .kvco_mask = 1 }, /* PLLM */ 651 { .m_shift = 0, .m_mask = 0xFF, .n_shift = 10, .n_mask = 0xFF, .p_shift = 20, .p_mask = 0x1F, 652 .lock_ena = 18, .lock_det = 27, .kcp_shift = 0, .kcp_mask = 3, .kvco_shift = 2, .kvco_mask = 1 }, /* PLLP */ 653 { .m_shift = 0, .m_mask = 0xFF, .n_shift = 8, .n_mask = 0xFF, .p_shift = 20, .p_mask = 0x1F, 654 .lock_ena = 28, .lock_det = 27, .kcp_shift = 25, .kcp_mask = 3, .kvco_shift = 24, .kvco_mask = 1 }, /* PLLA */ 655 { .m_shift = 0, .m_mask = 0xFF, .n_shift = 8, .n_mask = 0xFF, .p_shift = 16, .p_mask = 0x1F, 656 .lock_ena = 29, .lock_det = 27, .kcp_shift = 25, .kcp_mask = 3, .kvco_shift = 24, .kvco_mask = 1 }, /* PLLU */ 657 { .m_shift = 0, .m_mask = 0xFF, .n_shift = 11, .n_mask = 0xFF, .p_shift = 20, .p_mask = 0x07, 658 .lock_ena = 18, .lock_det = 27, .kcp_shift = 23, .kcp_mask = 3, .kvco_shift = 22, .kvco_mask = 1 }, /* PLLD */ 659 { .m_shift = 0, .m_mask = 0xFF, .n_shift = 8, .n_mask = 0xFF, .p_shift = 20, .p_mask = 0x1F, 660 .lock_ena = 18, .lock_det = 27, .kcp_shift = 1, .kcp_mask = 3, .kvco_shift = 0, .kvco_mask = 1 }, /* PLLX */ 661 { .m_shift = 0, .m_mask = 0xFF, .n_shift = 8, .n_mask = 0xFF, .p_shift = 0, .p_mask = 0, 662 .lock_ena = 9, .lock_det = 11, .kcp_shift = 6, .kcp_mask = 3, .kvco_shift = 0, .kvco_mask = 1 }, /* PLLE */ 663 { .m_shift = 0, .m_mask = 0, .n_shift = 0, .n_mask = 0, .p_shift = 0, .p_mask = 0, 664 .lock_ena = 0, .lock_det = 0, .kcp_shift = 0, .kcp_mask = 0, .kvco_shift = 0, .kvco_mask = 0 }, /* PLLS (gone)*/ 665 { .m_shift = 0, .m_mask = 0xFF, .n_shift = 8, .n_mask = 0xFF, .p_shift = 19, .p_mask = 0x1F, 666 .lock_ena = 30, .lock_det = 27, .kcp_shift = 25, .kcp_mask = 3, .kvco_shift = 24, .kvco_mask = 1 }, /* PLLDP */ 667 }; 668 669 /* 670 * Get the oscillator frequency, from the corresponding hardware configuration 671 * field. Note that Tegra30+ support 3 new higher freqs, but we map back 672 * to the old T20 freqs. Support for the higher oscillators is TBD. 673 */ 674 enum clock_osc_freq clock_get_osc_freq(void) 675 { 676 struct clk_rst_ctlr *clkrst = 677 (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE; 678 u32 reg; 679 680 reg = readl(&clkrst->crc_osc_ctrl); 681 reg = (reg & OSC_FREQ_MASK) >> OSC_FREQ_SHIFT; 682 /* 683 * 0 = 13MHz, 1 = 16.8MHz, 4 = 19.2MHz, 5 = 38.4MHz, 684 * 8 = 12MHz, 9 = 48MHz, 12 = 26MHz 685 */ 686 if (reg == 5) { 687 debug("OSC_FREQ is 38.4MHz (%d) ...\n", reg); 688 /* Map it to the 5th CLOCK_OSC_ enum, i.e. 4 */ 689 return 4; 690 } 691 692 /* 693 * Map to most common (T20) freqs (except 38.4, handled above): 694 * 13/16.8 = 0, 19.2 = 1, 12/48 = 2, 26 = 3 695 */ 696 return reg >> 2; 697 } 698 699 /* Returns a pointer to the clock source register for a peripheral */ 700 u32 *get_periph_source_reg(enum periph_id periph_id) 701 { 702 struct clk_rst_ctlr *clkrst = 703 (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE; 704 enum periphc_internal_id internal_id; 705 706 /* Coresight is a special case */ 707 if (periph_id == PERIPH_ID_CSI) 708 return &clkrst->crc_clk_src[PERIPH_ID_CSI+1]; 709 710 assert(periph_id >= PERIPH_ID_FIRST && periph_id < PERIPH_ID_COUNT); 711 internal_id = INTERNAL_ID(periph_id_to_internal_id[periph_id]); 712 assert(internal_id != -1); 713 714 if (internal_id < PERIPHC_VW_FIRST) 715 /* L, H, U */ 716 return &clkrst->crc_clk_src[internal_id]; 717 718 if (internal_id < PERIPHC_X_FIRST) { 719 /* VW */ 720 internal_id -= PERIPHC_VW_FIRST; 721 return &clkrst->crc_clk_src_vw[internal_id]; 722 } 723 724 if (internal_id < PERIPHC_Y_FIRST) { 725 /* X */ 726 internal_id -= PERIPHC_X_FIRST; 727 return &clkrst->crc_clk_src_x[internal_id]; 728 } 729 730 /* Y */ 731 internal_id -= PERIPHC_Y_FIRST; 732 return &clkrst->crc_clk_src_y[internal_id]; 733 } 734 735 /** 736 * Given a peripheral ID and the required source clock, this returns which 737 * value should be programmed into the source mux for that peripheral. 738 * 739 * There is special code here to handle the one source type with 5 sources. 740 * 741 * @param periph_id peripheral to start 742 * @param source PLL id of required parent clock 743 * @param mux_bits Set to number of bits in mux register: 2 or 4 744 * @param divider_bits Set to number of divider bits (8 or 16) 745 * @return mux value (0-4, or -1 if not found) 746 */ 747 int get_periph_clock_source(enum periph_id periph_id, 748 enum clock_id parent, int *mux_bits, int *divider_bits) 749 { 750 enum clock_type_id type; 751 enum periphc_internal_id internal_id; 752 int mux; 753 754 assert(clock_periph_id_isvalid(periph_id)); 755 756 internal_id = INTERNAL_ID(periph_id_to_internal_id[periph_id]); 757 assert(periphc_internal_id_isvalid(internal_id)); 758 759 type = clock_periph_type[internal_id]; 760 assert(clock_type_id_isvalid(type)); 761 762 *mux_bits = clock_source[type][CLOCK_MAX_MUX]; 763 764 if (type == CLOCK_TYPE_PC2CC3M_T16) 765 *divider_bits = 16; 766 else 767 *divider_bits = 8; 768 769 for (mux = 0; mux < CLOCK_MAX_MUX; mux++) 770 if (clock_source[type][mux] == parent) 771 return mux; 772 773 /* if we get here, either us or the caller has made a mistake */ 774 printf("Caller requested bad clock: periph=%d, parent=%d\n", periph_id, 775 parent); 776 return -1; 777 } 778 779 void clock_set_enable(enum periph_id periph_id, int enable) 780 { 781 struct clk_rst_ctlr *clkrst = 782 (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE; 783 u32 *clk; 784 u32 reg; 785 786 /* Enable/disable the clock to this peripheral */ 787 assert(clock_periph_id_isvalid(periph_id)); 788 if ((int)periph_id < (int)PERIPH_ID_VW_FIRST) 789 clk = &clkrst->crc_clk_out_enb[PERIPH_REG(periph_id)]; 790 else if ((int)periph_id < (int)PERIPH_ID_X_FIRST) 791 clk = &clkrst->crc_clk_out_enb_vw[PERIPH_REG(periph_id)]; 792 else if ((int)periph_id < (int)PERIPH_ID_Y_FIRST) 793 clk = &clkrst->crc_clk_out_enb_x; 794 else 795 clk = &clkrst->crc_clk_out_enb_y; 796 797 reg = readl(clk); 798 if (enable) 799 reg |= PERIPH_MASK(periph_id); 800 else 801 reg &= ~PERIPH_MASK(periph_id); 802 writel(reg, clk); 803 } 804 805 void reset_set_enable(enum periph_id periph_id, int enable) 806 { 807 struct clk_rst_ctlr *clkrst = 808 (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE; 809 u32 *reset; 810 u32 reg; 811 812 /* Enable/disable reset to the peripheral */ 813 assert(clock_periph_id_isvalid(periph_id)); 814 if (periph_id < PERIPH_ID_VW_FIRST) 815 reset = &clkrst->crc_rst_dev[PERIPH_REG(periph_id)]; 816 else if ((int)periph_id < (int)PERIPH_ID_X_FIRST) 817 reset = &clkrst->crc_rst_dev_vw[PERIPH_REG(periph_id)]; 818 else if ((int)periph_id < (int)PERIPH_ID_Y_FIRST) 819 reset = &clkrst->crc_rst_devices_x; 820 else 821 reset = &clkrst->crc_rst_devices_y; 822 823 reg = readl(reset); 824 if (enable) 825 reg |= PERIPH_MASK(periph_id); 826 else 827 reg &= ~PERIPH_MASK(periph_id); 828 writel(reg, reset); 829 } 830 831 #ifdef CONFIG_OF_CONTROL 832 /* 833 * Convert a device tree clock ID to our peripheral ID. They are mostly 834 * the same but we are very cautious so we check that a valid clock ID is 835 * provided. 836 * 837 * @param clk_id Clock ID according to tegra210 device tree binding 838 * @return peripheral ID, or PERIPH_ID_NONE if the clock ID is invalid 839 */ 840 enum periph_id clk_id_to_periph_id(int clk_id) 841 { 842 if (clk_id > PERIPH_ID_COUNT) 843 return PERIPH_ID_NONE; 844 845 switch (clk_id) { 846 case PERIPH_ID_RESERVED4: 847 case PERIPH_ID_RESERVED25: 848 case PERIPH_ID_RESERVED35: 849 case PERIPH_ID_RESERVED36: 850 case PERIPH_ID_RESERVED38: 851 case PERIPH_ID_RESERVED43: 852 case PERIPH_ID_RESERVED49: 853 case PERIPH_ID_RESERVED53: 854 case PERIPH_ID_RESERVED64: 855 case PERIPH_ID_RESERVED84: 856 case PERIPH_ID_RESERVED85: 857 case PERIPH_ID_RESERVED86: 858 case PERIPH_ID_RESERVED88: 859 case PERIPH_ID_RESERVED90: 860 case PERIPH_ID_RESERVED92: 861 case PERIPH_ID_RESERVED93: 862 case PERIPH_ID_RESERVED94: 863 case PERIPH_ID_V_RESERVED2: 864 case PERIPH_ID_V_RESERVED4: 865 case PERIPH_ID_V_RESERVED17: 866 case PERIPH_ID_V_RESERVED18: 867 case PERIPH_ID_V_RESERVED19: 868 case PERIPH_ID_V_RESERVED20: 869 case PERIPH_ID_V_RESERVED21: 870 case PERIPH_ID_V_RESERVED22: 871 case PERIPH_ID_W_RESERVED2: 872 case PERIPH_ID_W_RESERVED3: 873 case PERIPH_ID_W_RESERVED4: 874 case PERIPH_ID_W_RESERVED5: 875 case PERIPH_ID_W_RESERVED6: 876 case PERIPH_ID_W_RESERVED7: 877 case PERIPH_ID_W_RESERVED9: 878 case PERIPH_ID_W_RESERVED10: 879 case PERIPH_ID_W_RESERVED11: 880 case PERIPH_ID_W_RESERVED12: 881 case PERIPH_ID_W_RESERVED13: 882 case PERIPH_ID_W_RESERVED15: 883 case PERIPH_ID_W_RESERVED16: 884 case PERIPH_ID_W_RESERVED17: 885 case PERIPH_ID_W_RESERVED18: 886 case PERIPH_ID_W_RESERVED19: 887 case PERIPH_ID_W_RESERVED20: 888 case PERIPH_ID_W_RESERVED23: 889 case PERIPH_ID_W_RESERVED29: 890 case PERIPH_ID_W_RESERVED30: 891 case PERIPH_ID_W_RESERVED31: 892 return PERIPH_ID_NONE; 893 default: 894 return clk_id; 895 } 896 } 897 #endif /* CONFIG_OF_CONTROL */ 898 899 /* 900 * T210 redefines PLLP_OUT2 as PLLP_VCO/DIVP, so do different OUT1-4 setup here. 901 * PLLP_BASE/MISC/etc. is already set up for 408MHz in the BootROM. 902 */ 903 void tegra210_setup_pllp(void) 904 { 905 struct clk_rst_ctlr *clkrst = (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE; 906 u32 reg; 907 908 /* Set PLLP_OUT1, 3 & 4 freqs to 9.6, 102 & 204MHz */ 909 910 /* OUT1 */ 911 /* Assert RSTN before enable */ 912 reg = PLLP_OUT1_RSTN_EN; 913 writel(reg, &clkrst->crc_pll[CLOCK_ID_PERIPH].pll_out[0]); 914 /* Set divisor and reenable */ 915 reg = (IN_408_OUT_9_6_DIVISOR << PLLP_OUT1_RATIO) 916 | PLLP_OUT1_OVR | PLLP_OUT1_CLKEN | PLLP_OUT1_RSTN_DIS; 917 writel(reg, &clkrst->crc_pll[CLOCK_ID_PERIPH].pll_out[0]); 918 919 /* OUT3, 4 */ 920 /* Assert RSTN before enable */ 921 reg = PLLP_OUT4_RSTN_EN | PLLP_OUT3_RSTN_EN; 922 writel(reg, &clkrst->crc_pll[CLOCK_ID_PERIPH].pll_out[1]); 923 /* Set divisor and reenable */ 924 reg = (IN_408_OUT_204_DIVISOR << PLLP_OUT4_RATIO) 925 | PLLP_OUT4_OVR | PLLP_OUT4_CLKEN | PLLP_OUT4_RSTN_DIS 926 | (IN_408_OUT_102_DIVISOR << PLLP_OUT3_RATIO) 927 | PLLP_OUT3_OVR | PLLP_OUT3_CLKEN | PLLP_OUT3_RSTN_DIS; 928 writel(reg, &clkrst->crc_pll[CLOCK_ID_PERIPH].pll_out[1]); 929 930 /* 931 * NOTE: If you want to change PLLP_OUT2 away from 204MHz, 932 * you can change PLLP_BASE DIVP here. Currently defaults 933 * to 1, which is 2^1, or 2, so PLLP_OUT2 is 204MHz. 934 * See Table 13 in section 5.1.4 in T210 TRM for more info. 935 */ 936 } 937 938 void clock_early_init(void) 939 { 940 struct clk_rst_ctlr *clkrst = 941 (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE; 942 struct clk_pll_info *pllinfo = &tegra_pll_info_table[CLOCK_ID_DISPLAY]; 943 u32 data; 944 945 tegra210_setup_pllp(); 946 947 /* 948 * PLLC output frequency set to 600Mhz 949 * PLLD output frequency set to 925Mhz 950 */ 951 switch (clock_get_osc_freq()) { 952 case CLOCK_OSC_FREQ_12_0: /* OSC is 12Mhz */ 953 clock_set_rate(CLOCK_ID_CGENERAL, 600, 12, 0, 8); 954 clock_set_rate(CLOCK_ID_DISPLAY, 925, 12, 0, 12); 955 break; 956 957 case CLOCK_OSC_FREQ_26_0: /* OSC is 26Mhz */ 958 clock_set_rate(CLOCK_ID_CGENERAL, 600, 26, 0, 8); 959 clock_set_rate(CLOCK_ID_DISPLAY, 925, 26, 0, 12); 960 break; 961 962 case CLOCK_OSC_FREQ_13_0: /* OSC is 13Mhz */ 963 clock_set_rate(CLOCK_ID_CGENERAL, 600, 13, 0, 8); 964 clock_set_rate(CLOCK_ID_DISPLAY, 925, 13, 0, 12); 965 break; 966 case CLOCK_OSC_FREQ_19_2: 967 clock_set_rate(CLOCK_ID_CGENERAL, 125, 4, 0, 0); 968 clock_set_rate(CLOCK_ID_DISPLAY, 96, 2, 0, 12); 969 break; 970 case CLOCK_OSC_FREQ_38_4: 971 clock_set_rate(CLOCK_ID_CGENERAL, 125, 8, 0, 0); 972 clock_set_rate(CLOCK_ID_DISPLAY, 96, 4, 0, 0); 973 break; 974 default: 975 /* 976 * These are not supported. It is too early to print a 977 * message and the UART likely won't work anyway due to the 978 * oscillator being wrong. 979 */ 980 break; 981 } 982 983 /* PLLC_MISC1: Turn IDDQ off. NOTE: T210 PLLC_MISC_1 maps to pll_misc */ 984 clrbits_le32(&clkrst->crc_pll[CLOCK_ID_CGENERAL].pll_misc, 985 (1 << PLLC_IDDQ)); 986 udelay(2); 987 988 /* 989 * PLLC_MISC: Take PLLC out of reset. NOTE: T210 PLLC_MISC maps 990 * to pll_out[1] 991 */ 992 clrbits_le32(&clkrst->crc_pll[CLOCK_ID_CGENERAL].pll_out[1], 993 (1 << PLLC_RESET)); 994 udelay(2); 995 996 /* PLLD_MISC: Set CLKENABLE and LOCK_DETECT bits */ 997 data = (1 << PLLD_ENABLE_CLK) | (1 << pllinfo->lock_ena); 998 writel(data, &clkrst->crc_pll[CLOCK_ID_DISPLAY].pll_misc); 999 udelay(2); 1000 } 1001 1002 unsigned int clk_m_get_rate(unsigned parent_rate) 1003 { 1004 struct clk_rst_ctlr *clkrst = (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE; 1005 u32 value, div; 1006 1007 value = readl(&clkrst->crc_spare_reg0); 1008 div = ((value >> 2) & 0x3) + 1; 1009 1010 return parent_rate / div; 1011 } 1012 1013 void arch_timer_init(void) 1014 { 1015 struct sysctr_ctlr *sysctr = (struct sysctr_ctlr *)NV_PA_TSC_BASE; 1016 u32 freq, val; 1017 1018 freq = clock_get_rate(CLOCK_ID_CLK_M); 1019 debug("%s: clk_m freq is %dHz [0x%08X]\n", __func__, freq, freq); 1020 1021 if (current_el() == 3) 1022 asm("msr cntfrq_el0, %0\n" : : "r" (freq)); 1023 1024 /* Only Tegra114+ has the System Counter regs */ 1025 debug("%s: setting CNTFID0 to 0x%08X\n", __func__, freq); 1026 writel(freq, &sysctr->cntfid0); 1027 1028 val = readl(&sysctr->cntcr); 1029 val |= TSC_CNTCR_ENABLE | TSC_CNTCR_HDBG; 1030 writel(val, &sysctr->cntcr); 1031 debug("%s: TSC CNTCR = 0x%08X\n", __func__, val); 1032 } 1033 1034 #define PLLREFE_MISC 0x4c8 1035 #define PLLREFE_MISC_LOCK BIT(27) 1036 #define PLLREFE_MISC_IDDQ BIT(24) 1037 1038 #define PLLREFE_BASE 0x4c4 1039 #define PLLREFE_BASE_BYPASS BIT(31) 1040 #define PLLREFE_BASE_ENABLE BIT(30) 1041 #define PLLREFE_BASE_REF_DIS BIT(29) 1042 #define PLLREFE_BASE_KCP(kcp) (((kcp) & 0x3) << 27) 1043 #define PLLREFE_BASE_KVCO BIT(26) 1044 #define PLLREFE_BASE_DIVP(p) (((p) & 0x1f) << 16) 1045 #define PLLREFE_BASE_DIVN(n) (((n) & 0xff) << 8) 1046 #define PLLREFE_BASE_DIVM(m) (((m) & 0xff) << 0) 1047 1048 static int tegra_pllref_enable(void) 1049 { 1050 u32 value; 1051 unsigned long start; 1052 1053 /* 1054 * This sequence comes from Tegra X1 TRM section "Cold Boot, with no 1055 * Recovery Mode or Boot from USB", sub-section "PLLREFE". 1056 */ 1057 1058 value = readl(NV_PA_CLK_RST_BASE + PLLREFE_MISC); 1059 value &= ~PLLREFE_MISC_IDDQ; 1060 writel(value, NV_PA_CLK_RST_BASE + PLLREFE_MISC); 1061 1062 udelay(5); 1063 1064 value = PLLREFE_BASE_ENABLE | 1065 PLLREFE_BASE_KCP(0) | 1066 PLLREFE_BASE_DIVP(0) | 1067 PLLREFE_BASE_DIVN(0x41) | 1068 PLLREFE_BASE_DIVM(4); 1069 writel(value, NV_PA_CLK_RST_BASE + PLLREFE_BASE); 1070 1071 debug("waiting for pllrefe lock\n"); 1072 start = get_timer(0); 1073 while (get_timer(start) < 250) { 1074 value = readl(NV_PA_CLK_RST_BASE + PLLREFE_MISC); 1075 if (value & PLLREFE_MISC_LOCK) 1076 break; 1077 } 1078 if (!(value & PLLREFE_MISC_LOCK)) { 1079 debug(" timeout\n"); 1080 return -ETIMEDOUT; 1081 } 1082 debug(" done\n"); 1083 1084 return 0; 1085 } 1086 1087 #define PLLE_SS_CNTL 0x68 1088 #define PLLE_SS_CNTL_SSCINCINTR(x) (((x) & 0x3f) << 24) 1089 #define PLLE_SS_CNTL_SSCINC(x) (((x) & 0xff) << 16) 1090 #define PLLE_SS_CNTL_SSCINVERT (1 << 15) 1091 #define PLLE_SS_CNTL_SSCCENTER (1 << 14) 1092 #define PLLE_SS_CNTL_SSCBYP (1 << 12) 1093 #define PLLE_SS_CNTL_INTERP_RESET (1 << 11) 1094 #define PLLE_SS_CNTL_BYPASS_SS (1 << 10) 1095 #define PLLE_SS_CNTL_SSCMAX(x) (((x) & 0x1ff) << 0) 1096 1097 #define PLLE_BASE 0x0e8 1098 #define PLLE_BASE_ENABLE (1 << 31) 1099 #define PLLE_BASE_PLDIV_CML(x) (((x) & 0x1f) << 24) 1100 #define PLLE_BASE_NDIV(x) (((x) & 0xff) << 8) 1101 #define PLLE_BASE_MDIV(x) (((x) & 0xff) << 0) 1102 1103 #define PLLE_MISC 0x0ec 1104 #define PLLE_MISC_IDDQ_SWCTL (1 << 14) 1105 #define PLLE_MISC_IDDQ_OVERRIDE_VALUE (1 << 13) 1106 #define PLLE_MISC_LOCK (1 << 11) 1107 #define PLLE_MISC_KCP(x) (((x) & 0x3) << 6) 1108 #define PLLE_MISC_VREG_CTRL(x) (((x) & 0x3) << 2) 1109 #define PLLE_MISC_KVCO (1 << 0) 1110 1111 #define PLLE_AUX 0x48c 1112 #define PLLE_AUX_SS_SEQ_INCLUDE (1 << 31) 1113 #define PLLE_AUX_REF_SEL_PLLREFE (1 << 28) 1114 #define PLLE_AUX_SEQ_ENABLE (1 << 24) 1115 #define PLLE_AUX_SS_SWCTL (1 << 6) 1116 #define PLLE_AUX_ENABLE_SWCTL (1 << 4) 1117 #define PLLE_AUX_USE_LOCKDET (1 << 3) 1118 1119 int tegra_plle_enable(void) 1120 { 1121 u32 value; 1122 unsigned long start; 1123 1124 /* PLLREF feeds PLLE */ 1125 tegra_pllref_enable(); 1126 1127 /* 1128 * This sequence comes from Tegra X1 TRM section "Cold Boot, with no 1129 * Recovery Mode or Boot from USB", sub-section "PLLEs". 1130 */ 1131 1132 /* 1. Select XTAL as the source */ 1133 1134 value = readl(NV_PA_CLK_RST_BASE + PLLE_AUX); 1135 value &= ~PLLE_AUX_REF_SEL_PLLREFE; 1136 writel(value, NV_PA_CLK_RST_BASE + PLLE_AUX); 1137 1138 value = readl(NV_PA_CLK_RST_BASE + PLLE_MISC); 1139 value &= ~PLLE_MISC_IDDQ_OVERRIDE_VALUE; 1140 writel(value, NV_PA_CLK_RST_BASE + PLLE_MISC); 1141 1142 /* 2. Wait 5 us */ 1143 udelay(5); 1144 1145 /* 1146 * 3. Program the following registers to generate a low jitter 100MHz 1147 * clock. 1148 */ 1149 1150 value = readl(NV_PA_CLK_RST_BASE + PLLE_BASE); 1151 value &= ~PLLE_BASE_PLDIV_CML(0x1f); 1152 value &= ~PLLE_BASE_NDIV(0xff); 1153 value &= ~PLLE_BASE_MDIV(0xff); 1154 value |= PLLE_BASE_PLDIV_CML(0xe); 1155 value |= PLLE_BASE_NDIV(0x7d); 1156 value |= PLLE_BASE_MDIV(2); 1157 writel(value, NV_PA_CLK_RST_BASE + PLLE_BASE); 1158 1159 value = readl(NV_PA_CLK_RST_BASE + PLLE_MISC); 1160 value &= ~PLLE_MISC_KCP(3); 1161 value &= ~PLLE_MISC_VREG_CTRL(3); 1162 value &= ~PLLE_MISC_KVCO; 1163 writel(value, NV_PA_CLK_RST_BASE + PLLE_MISC); 1164 1165 value = readl(NV_PA_CLK_RST_BASE + PLLE_BASE); 1166 value |= PLLE_BASE_ENABLE; 1167 writel(value, NV_PA_CLK_RST_BASE + PLLE_BASE); 1168 1169 /* 4. Wait for LOCK */ 1170 1171 debug("waiting for plle lock\n"); 1172 start = get_timer(0); 1173 while (get_timer(start) < 250) { 1174 value = readl(NV_PA_CLK_RST_BASE + PLLE_MISC); 1175 if (value & PLLE_MISC_LOCK) 1176 break; 1177 } 1178 if (!(value & PLLE_MISC_LOCK)) { 1179 debug(" timeout\n"); 1180 return -ETIMEDOUT; 1181 } 1182 debug(" done\n"); 1183 1184 /* 5. Enable SSA */ 1185 1186 value = readl(NV_PA_CLK_RST_BASE + PLLE_SS_CNTL); 1187 value &= ~PLLE_SS_CNTL_SSCINC(0xff); 1188 value |= PLLE_SS_CNTL_SSCINC(1); 1189 value &= ~PLLE_SS_CNTL_SSCINCINTR(0x3f); 1190 value |= PLLE_SS_CNTL_SSCINCINTR(0x23); 1191 value &= ~PLLE_SS_CNTL_SSCMAX(0x1fff); 1192 value |= PLLE_SS_CNTL_SSCMAX(0x21); 1193 value &= ~PLLE_SS_CNTL_SSCINVERT; 1194 value &= ~PLLE_SS_CNTL_SSCCENTER; 1195 value &= ~PLLE_SS_CNTL_BYPASS_SS; 1196 value &= ~PLLE_SS_CNTL_SSCBYP; 1197 writel(value, NV_PA_CLK_RST_BASE + PLLE_SS_CNTL); 1198 1199 /* 6. Wait 300 ns */ 1200 1201 udelay(1); 1202 value &= ~PLLE_SS_CNTL_INTERP_RESET; 1203 writel(value, NV_PA_CLK_RST_BASE + PLLE_SS_CNTL); 1204 1205 /* 7. Enable HW power sequencer for PLLE */ 1206 1207 value = readl(NV_PA_CLK_RST_BASE + PLLE_MISC); 1208 value &= ~PLLE_MISC_IDDQ_SWCTL; 1209 writel(value, NV_PA_CLK_RST_BASE + PLLE_MISC); 1210 1211 value = readl(NV_PA_CLK_RST_BASE + PLLE_AUX); 1212 value &= ~PLLE_AUX_SS_SWCTL; 1213 value &= ~PLLE_AUX_ENABLE_SWCTL; 1214 value |= PLLE_AUX_SS_SEQ_INCLUDE; 1215 value |= PLLE_AUX_USE_LOCKDET; 1216 writel(value, NV_PA_CLK_RST_BASE + PLLE_AUX); 1217 1218 /* 8. Wait 1 us */ 1219 1220 udelay(1); 1221 value |= PLLE_AUX_SEQ_ENABLE; 1222 writel(value, NV_PA_CLK_RST_BASE + PLLE_AUX); 1223 1224 return 0; 1225 } 1226