1 /* 2 * (C) Copyright 2013-2015 3 * NVIDIA Corporation <www.nvidia.com> 4 * 5 * SPDX-License-Identifier: GPL-2.0+ 6 */ 7 8 /* Tegra210 Clock control functions */ 9 10 #include <common.h> 11 #include <asm/io.h> 12 #include <asm/arch/clock.h> 13 #include <asm/arch/sysctr.h> 14 #include <asm/arch/tegra.h> 15 #include <asm/arch-tegra/clk_rst.h> 16 #include <asm/arch-tegra/timer.h> 17 #include <div64.h> 18 #include <fdtdec.h> 19 20 /* 21 * Clock types that we can use as a source. The Tegra210 has muxes for the 22 * peripheral clocks, and in most cases there are four options for the clock 23 * source. This gives us a clock 'type' and exploits what commonality exists 24 * in the device. 25 * 26 * Letters are obvious, except for T which means CLK_M, and S which means the 27 * clock derived from 32KHz. Beware that CLK_M (also called OSC in the 28 * datasheet) and PLL_M are different things. The former is the basic 29 * clock supplied to the SOC from an external oscillator. The latter is the 30 * memory clock PLL. 31 * 32 * See definitions in clock_id in the header file. 33 */ 34 enum clock_type_id { 35 CLOCK_TYPE_AXPT, /* PLL_A, PLL_X, PLL_P, CLK_M */ 36 CLOCK_TYPE_MCPA, /* and so on */ 37 CLOCK_TYPE_MCPT, 38 CLOCK_TYPE_PCM, 39 CLOCK_TYPE_PCMT, 40 CLOCK_TYPE_PDCT, 41 CLOCK_TYPE_ACPT, 42 CLOCK_TYPE_ASPTE, 43 CLOCK_TYPE_PMDACD2T, 44 CLOCK_TYPE_PCST, 45 CLOCK_TYPE_DP, 46 47 CLOCK_TYPE_PC2CC3M, 48 CLOCK_TYPE_PC2CC3S_T, 49 CLOCK_TYPE_PC2CC3M_T, 50 CLOCK_TYPE_PC2CC3M_T16, /* PC2CC3M_T, but w/16-bit divisor (I2C) */ 51 CLOCK_TYPE_MC2CC3P_A, 52 CLOCK_TYPE_M, 53 CLOCK_TYPE_MCPTM2C2C3, 54 CLOCK_TYPE_PC2CC3T_S, 55 CLOCK_TYPE_AC2CC3P_TS2, 56 CLOCK_TYPE_PC01C00_C42C41TC40, 57 58 CLOCK_TYPE_COUNT, 59 CLOCK_TYPE_NONE = -1, /* invalid clock type */ 60 }; 61 62 enum { 63 CLOCK_MAX_MUX = 8 /* number of source options for each clock */ 64 }; 65 66 /* 67 * Clock source mux for each clock type. This just converts our enum into 68 * a list of mux sources for use by the code. 69 * 70 * Note: 71 * The extra column in each clock source array is used to store the mask 72 * bits in its register for the source. 73 */ 74 #define CLK(x) CLOCK_ID_ ## x 75 static enum clock_id clock_source[CLOCK_TYPE_COUNT][CLOCK_MAX_MUX+1] = { 76 { CLK(AUDIO), CLK(XCPU), CLK(PERIPH), CLK(OSC), 77 CLK(NONE), CLK(NONE), CLK(NONE), CLK(NONE), 78 MASK_BITS_31_30}, 79 { CLK(MEMORY), CLK(CGENERAL), CLK(PERIPH), CLK(AUDIO), 80 CLK(NONE), CLK(NONE), CLK(NONE), CLK(NONE), 81 MASK_BITS_31_30}, 82 { CLK(MEMORY), CLK(CGENERAL), CLK(PERIPH), CLK(OSC), 83 CLK(NONE), CLK(NONE), CLK(NONE), CLK(NONE), 84 MASK_BITS_31_30}, 85 { CLK(PERIPH), CLK(CGENERAL), CLK(MEMORY), CLK(NONE), 86 CLK(NONE), CLK(NONE), CLK(NONE), CLK(NONE), 87 MASK_BITS_31_30}, 88 { CLK(PERIPH), CLK(CGENERAL), CLK(MEMORY), CLK(OSC), 89 CLK(NONE), CLK(NONE), CLK(NONE), CLK(NONE), 90 MASK_BITS_31_30}, 91 { CLK(PERIPH), CLK(DISPLAY), CLK(CGENERAL), CLK(OSC), 92 CLK(NONE), CLK(NONE), CLK(NONE), CLK(NONE), 93 MASK_BITS_31_30}, 94 { CLK(AUDIO), CLK(CGENERAL), CLK(PERIPH), CLK(OSC), 95 CLK(NONE), CLK(NONE), CLK(NONE), CLK(NONE), 96 MASK_BITS_31_30}, 97 { CLK(AUDIO), CLK(SFROM32KHZ), CLK(PERIPH), CLK(OSC), 98 CLK(EPCI), CLK(NONE), CLK(NONE), CLK(NONE), 99 MASK_BITS_31_29}, 100 { CLK(PERIPH), CLK(MEMORY), CLK(DISPLAY), CLK(AUDIO), 101 CLK(CGENERAL), CLK(DISPLAY2), CLK(OSC), CLK(NONE), 102 MASK_BITS_31_29}, 103 { CLK(PERIPH), CLK(CGENERAL), CLK(SFROM32KHZ), CLK(OSC), 104 CLK(NONE), CLK(NONE), CLK(NONE), CLK(NONE), 105 MASK_BITS_31_28}, 106 /* CLOCK_TYPE_DP */ 107 { CLK(NONE), CLK(NONE), CLK(NONE), CLK(NONE), 108 CLK(NONE), CLK(NONE), CLK(NONE), CLK(NONE), 109 MASK_BITS_31_28}, 110 111 /* Additional clock types on Tegra114+ */ 112 /* CLOCK_TYPE_PC2CC3M */ 113 { CLK(PERIPH), CLK(CGENERAL2), CLK(CGENERAL), CLK(CGENERAL3), 114 CLK(MEMORY), CLK(NONE), CLK(NONE), CLK(NONE), 115 MASK_BITS_31_29}, 116 /* CLOCK_TYPE_PC2CC3S_T */ 117 { CLK(PERIPH), CLK(CGENERAL2), CLK(CGENERAL), CLK(CGENERAL3), 118 CLK(SFROM32KHZ), CLK(NONE), CLK(OSC), CLK(NONE), 119 MASK_BITS_31_29}, 120 /* CLOCK_TYPE_PC2CC3M_T */ 121 { CLK(PERIPH), CLK(CGENERAL2), CLK(CGENERAL), CLK(CGENERAL3), 122 CLK(MEMORY), CLK(NONE), CLK(OSC), CLK(NONE), 123 MASK_BITS_31_29}, 124 /* CLOCK_TYPE_PC2CC3M_T, w/16-bit divisor (I2C) */ 125 { CLK(PERIPH), CLK(CGENERAL2), CLK(CGENERAL), CLK(CGENERAL3), 126 CLK(MEMORY), CLK(NONE), CLK(OSC), CLK(NONE), 127 MASK_BITS_31_29}, 128 /* CLOCK_TYPE_MC2CC3P_A */ 129 { CLK(MEMORY), CLK(CGENERAL2), CLK(CGENERAL), CLK(CGENERAL3), 130 CLK(PERIPH), CLK(NONE), CLK(AUDIO), CLK(NONE), 131 MASK_BITS_31_29}, 132 /* CLOCK_TYPE_M */ 133 { CLK(MEMORY), CLK(NONE), CLK(NONE), CLK(NONE), 134 CLK(NONE), CLK(NONE), CLK(NONE), CLK(NONE), 135 MASK_BITS_31_30}, 136 /* CLOCK_TYPE_MCPTM2C2C3 */ 137 { CLK(MEMORY), CLK(CGENERAL), CLK(PERIPH), CLK(OSC), 138 CLK(MEMORY2), CLK(CGENERAL2), CLK(CGENERAL3), CLK(NONE), 139 MASK_BITS_31_29}, 140 /* CLOCK_TYPE_PC2CC3T_S */ 141 { CLK(PERIPH), CLK(CGENERAL2), CLK(CGENERAL), CLK(CGENERAL3), 142 CLK(OSC), CLK(NONE), CLK(SFROM32KHZ), CLK(NONE), 143 MASK_BITS_31_29}, 144 /* CLOCK_TYPE_AC2CC3P_TS2 */ 145 { CLK(AUDIO), CLK(CGENERAL2), CLK(CGENERAL), CLK(CGENERAL3), 146 CLK(PERIPH), CLK(NONE), CLK(OSC), CLK(SRC2), 147 MASK_BITS_31_29}, 148 /* CLOCK_TYPE_PC01C00_C42C41TC40 */ 149 { CLK(PERIPH), CLK(CGENERAL_1), CLK(CGENERAL_0), CLK(NONE), 150 CLK(CGENERAL4_2), CLK(CGENERAL4_1), CLK(OSC), CLK(CGENERAL4_0), 151 MASK_BITS_31_29}, 152 }; 153 154 /* 155 * Clock type for each peripheral clock source. We put the name in each 156 * record just so it is easy to match things up 157 */ 158 #define TYPE(name, type) type 159 static enum clock_type_id clock_periph_type[PERIPHC_COUNT] = { 160 /* 0x00 */ 161 TYPE(PERIPHC_I2S2, CLOCK_TYPE_AXPT), 162 TYPE(PERIPHC_I2S3, CLOCK_TYPE_AXPT), 163 TYPE(PERIPHC_SPDIF_OUT, CLOCK_TYPE_AXPT), 164 TYPE(PERIPHC_SPDIF_IN, CLOCK_TYPE_PC2CC3M), 165 TYPE(PERIPHC_PWM, CLOCK_TYPE_PC2CC3S_T), 166 TYPE(PERIPHC_05h, CLOCK_TYPE_NONE), 167 TYPE(PERIPHC_SBC2, CLOCK_TYPE_PC2CC3M_T), 168 TYPE(PERIPHC_SBC3, CLOCK_TYPE_PC2CC3M_T), 169 170 /* 0x08 */ 171 TYPE(PERIPHC_08h, CLOCK_TYPE_NONE), 172 TYPE(PERIPHC_I2C1, CLOCK_TYPE_PC2CC3M_T16), 173 TYPE(PERIPHC_I2C5, CLOCK_TYPE_PC2CC3M_T16), 174 TYPE(PERIPHC_0bh, CLOCK_TYPE_NONE), 175 TYPE(PERIPHC_0ch, CLOCK_TYPE_NONE), 176 TYPE(PERIPHC_SBC1, CLOCK_TYPE_PC2CC3M_T), 177 TYPE(PERIPHC_DISP1, CLOCK_TYPE_PMDACD2T), 178 TYPE(PERIPHC_DISP2, CLOCK_TYPE_PMDACD2T), 179 180 /* 0x10 */ 181 TYPE(PERIPHC_10h, CLOCK_TYPE_NONE), 182 TYPE(PERIPHC_11h, CLOCK_TYPE_NONE), 183 TYPE(PERIPHC_VI, CLOCK_TYPE_MC2CC3P_A), 184 TYPE(PERIPHC_13h, CLOCK_TYPE_NONE), 185 TYPE(PERIPHC_SDMMC1, CLOCK_TYPE_PC2CC3M_T), 186 TYPE(PERIPHC_SDMMC2, CLOCK_TYPE_PC2CC3M_T), 187 TYPE(PERIPHC_16h, CLOCK_TYPE_NONE), 188 TYPE(PERIPHC_17h, CLOCK_TYPE_NONE), 189 190 /* 0x18 */ 191 TYPE(PERIPHC_18h, CLOCK_TYPE_NONE), 192 TYPE(PERIPHC_SDMMC4, CLOCK_TYPE_PC2CC3M_T), 193 TYPE(PERIPHC_VFIR, CLOCK_TYPE_PC2CC3M_T), 194 TYPE(PERIPHC_1Bh, CLOCK_TYPE_NONE), 195 TYPE(PERIPHC_1Ch, CLOCK_TYPE_NONE), 196 TYPE(PERIPHC_HSI, CLOCK_TYPE_PC2CC3M_T), 197 TYPE(PERIPHC_UART1, CLOCK_TYPE_PC2CC3M_T), 198 TYPE(PERIPHC_UART2, CLOCK_TYPE_PC2CC3M_T), 199 200 /* 0x20 */ 201 TYPE(PERIPHC_HOST1X, CLOCK_TYPE_MC2CC3P_A), 202 TYPE(PERIPHC_21h, CLOCK_TYPE_NONE), 203 TYPE(PERIPHC_22h, CLOCK_TYPE_NONE), 204 TYPE(PERIPHC_23h, CLOCK_TYPE_NONE), 205 TYPE(PERIPHC_24h, CLOCK_TYPE_NONE), 206 TYPE(PERIPHC_25h, CLOCK_TYPE_NONE), 207 TYPE(PERIPHC_I2C2, CLOCK_TYPE_PC2CC3M_T16), 208 TYPE(PERIPHC_EMC, CLOCK_TYPE_MCPTM2C2C3), 209 210 /* 0x28 */ 211 TYPE(PERIPHC_UART3, CLOCK_TYPE_PC2CC3M_T), 212 TYPE(PERIPHC_29h, CLOCK_TYPE_NONE), 213 TYPE(PERIPHC_VI_SENSOR, CLOCK_TYPE_MC2CC3P_A), 214 TYPE(PERIPHC_2bh, CLOCK_TYPE_NONE), 215 TYPE(PERIPHC_2ch, CLOCK_TYPE_NONE), 216 TYPE(PERIPHC_SBC4, CLOCK_TYPE_PC2CC3M_T), 217 TYPE(PERIPHC_I2C3, CLOCK_TYPE_PC2CC3M_T16), 218 TYPE(PERIPHC_SDMMC3, CLOCK_TYPE_PC2CC3M_T), 219 220 /* 0x30 */ 221 TYPE(PERIPHC_UART4, CLOCK_TYPE_PC2CC3M_T), 222 TYPE(PERIPHC_UART5, CLOCK_TYPE_PC2CC3M_T), 223 TYPE(PERIPHC_VDE, CLOCK_TYPE_PC2CC3M_T), 224 TYPE(PERIPHC_OWR, CLOCK_TYPE_PC2CC3M_T), 225 TYPE(PERIPHC_NOR, CLOCK_TYPE_PC2CC3M_T), 226 TYPE(PERIPHC_CSITE, CLOCK_TYPE_PC2CC3M_T), 227 TYPE(PERIPHC_I2S1, CLOCK_TYPE_AXPT), 228 TYPE(PERIPHC_DTV, CLOCK_TYPE_NONE), 229 230 /* 0x38 */ 231 TYPE(PERIPHC_38h, CLOCK_TYPE_NONE), 232 TYPE(PERIPHC_39h, CLOCK_TYPE_NONE), 233 TYPE(PERIPHC_3ah, CLOCK_TYPE_NONE), 234 TYPE(PERIPHC_3bh, CLOCK_TYPE_NONE), 235 TYPE(PERIPHC_MSENC, CLOCK_TYPE_MC2CC3P_A), 236 TYPE(PERIPHC_TSEC, CLOCK_TYPE_PC2CC3M_T), 237 TYPE(PERIPHC_3eh, CLOCK_TYPE_NONE), 238 TYPE(PERIPHC_OSC, CLOCK_TYPE_NONE), 239 240 /* 0x40 */ 241 TYPE(PERIPHC_40h, CLOCK_TYPE_NONE), /* start with 0x3b0 */ 242 TYPE(PERIPHC_MSELECT, CLOCK_TYPE_PC2CC3M_T), 243 TYPE(PERIPHC_TSENSOR, CLOCK_TYPE_PC2CC3T_S), 244 TYPE(PERIPHC_I2S4, CLOCK_TYPE_AXPT), 245 TYPE(PERIPHC_I2S5, CLOCK_TYPE_AXPT), 246 TYPE(PERIPHC_I2C4, CLOCK_TYPE_PC2CC3M_T16), 247 TYPE(PERIPHC_SBC5, CLOCK_TYPE_PC2CC3M_T), 248 TYPE(PERIPHC_SBC6, CLOCK_TYPE_PC2CC3M_T), 249 250 /* 0x48 */ 251 TYPE(PERIPHC_AUDIO, CLOCK_TYPE_AC2CC3P_TS2), 252 TYPE(PERIPHC_49h, CLOCK_TYPE_NONE), 253 TYPE(PERIPHC_4ah, CLOCK_TYPE_NONE), 254 TYPE(PERIPHC_4bh, CLOCK_TYPE_NONE), 255 TYPE(PERIPHC_4ch, CLOCK_TYPE_NONE), 256 TYPE(PERIPHC_HDA2CODEC2X, CLOCK_TYPE_PC2CC3M_T), 257 TYPE(PERIPHC_ACTMON, CLOCK_TYPE_PC2CC3S_T), 258 TYPE(PERIPHC_EXTPERIPH1, CLOCK_TYPE_ASPTE), 259 260 /* 0x50 */ 261 TYPE(PERIPHC_EXTPERIPH2, CLOCK_TYPE_ASPTE), 262 TYPE(PERIPHC_EXTPERIPH3, CLOCK_TYPE_ASPTE), 263 TYPE(PERIPHC_52h, CLOCK_TYPE_NONE), 264 TYPE(PERIPHC_I2CSLOW, CLOCK_TYPE_PC2CC3S_T), 265 TYPE(PERIPHC_SYS, CLOCK_TYPE_NONE), 266 TYPE(PERIPHC_55h, CLOCK_TYPE_NONE), 267 TYPE(PERIPHC_56h, CLOCK_TYPE_NONE), 268 TYPE(PERIPHC_57h, CLOCK_TYPE_NONE), 269 270 /* 0x58 */ 271 TYPE(PERIPHC_58h, CLOCK_TYPE_NONE), 272 TYPE(PERIPHC_59h, CLOCK_TYPE_NONE), 273 TYPE(PERIPHC_5ah, CLOCK_TYPE_NONE), 274 TYPE(PERIPHC_5bh, CLOCK_TYPE_NONE), 275 TYPE(PERIPHC_SATAOOB, CLOCK_TYPE_PCMT), 276 TYPE(PERIPHC_SATA, CLOCK_TYPE_PCMT), 277 TYPE(PERIPHC_HDA, CLOCK_TYPE_PC2CC3M_T), 278 TYPE(PERIPHC_5fh, CLOCK_TYPE_NONE), 279 280 /* 0x60 */ 281 TYPE(PERIPHC_XUSB_CORE_HOST, CLOCK_TYPE_NONE), 282 TYPE(PERIPHC_XUSB_FALCON, CLOCK_TYPE_NONE), 283 TYPE(PERIPHC_XUSB_FS, CLOCK_TYPE_NONE), 284 TYPE(PERIPHC_XUSB_CORE_DEV, CLOCK_TYPE_NONE), 285 TYPE(PERIPHC_XUSB_SS, CLOCK_TYPE_NONE), 286 TYPE(PERIPHC_CILAB, CLOCK_TYPE_NONE), 287 TYPE(PERIPHC_CILCD, CLOCK_TYPE_NONE), 288 TYPE(PERIPHC_CILE, CLOCK_TYPE_NONE), 289 290 /* 0x68 */ 291 TYPE(PERIPHC_DSIA_LP, CLOCK_TYPE_NONE), 292 TYPE(PERIPHC_DSIB_LP, CLOCK_TYPE_NONE), 293 TYPE(PERIPHC_ENTROPY, CLOCK_TYPE_NONE), 294 TYPE(PERIPHC_DVFS_REF, CLOCK_TYPE_NONE), 295 TYPE(PERIPHC_DVFS_SOC, CLOCK_TYPE_NONE), 296 TYPE(PERIPHC_TRACECLKIN, CLOCK_TYPE_NONE), 297 TYPE(PERIPHC_6eh, CLOCK_TYPE_NONE), 298 TYPE(PERIPHC_6fh, CLOCK_TYPE_NONE), 299 300 /* 0x70 */ 301 TYPE(PERIPHC_EMC_LATENCY, CLOCK_TYPE_NONE), 302 TYPE(PERIPHC_SOC_THERM, CLOCK_TYPE_NONE), 303 TYPE(PERIPHC_72h, CLOCK_TYPE_NONE), 304 TYPE(PERIPHC_73h, CLOCK_TYPE_NONE), 305 TYPE(PERIPHC_74h, CLOCK_TYPE_NONE), 306 TYPE(PERIPHC_75h, CLOCK_TYPE_NONE), 307 TYPE(PERIPHC_VI_SENSOR2, CLOCK_TYPE_NONE), 308 TYPE(PERIPHC_I2C6, CLOCK_TYPE_PC2CC3M_T16), 309 310 /* 0x78 */ 311 TYPE(PERIPHC_78h, CLOCK_TYPE_NONE), 312 TYPE(PERIPHC_EMC_DLL, CLOCK_TYPE_MCPTM2C2C3), 313 TYPE(PERIPHC_7ah, CLOCK_TYPE_NONE), 314 TYPE(PERIPHC_CLK72MHZ, CLOCK_TYPE_NONE), 315 TYPE(PERIPHC_7ch, CLOCK_TYPE_NONE), 316 TYPE(PERIPHC_7dh, CLOCK_TYPE_NONE), 317 TYPE(PERIPHC_VIC, CLOCK_TYPE_NONE), 318 TYPE(PERIPHC_7Fh, CLOCK_TYPE_NONE), 319 320 /* 0x80 */ 321 TYPE(PERIPHC_SDMMC_LEGACY_TM, CLOCK_TYPE_NONE), 322 TYPE(PERIPHC_NVDEC, CLOCK_TYPE_NONE), 323 TYPE(PERIPHC_NVJPG, CLOCK_TYPE_NONE), 324 TYPE(PERIPHC_NVENC, CLOCK_TYPE_NONE), 325 TYPE(PERIPHC_84h, CLOCK_TYPE_NONE), 326 TYPE(PERIPHC_85h, CLOCK_TYPE_NONE), 327 TYPE(PERIPHC_86h, CLOCK_TYPE_NONE), 328 TYPE(PERIPHC_87h, CLOCK_TYPE_NONE), 329 330 /* 0x88 */ 331 TYPE(PERIPHC_88h, CLOCK_TYPE_NONE), 332 TYPE(PERIPHC_89h, CLOCK_TYPE_NONE), 333 TYPE(PERIPHC_DMIC3, CLOCK_TYPE_NONE), 334 TYPE(PERIPHC_APE, CLOCK_TYPE_NONE), 335 TYPE(PERIPHC_QSPI, CLOCK_TYPE_PC01C00_C42C41TC40), 336 TYPE(PERIPHC_VI_I2C, CLOCK_TYPE_NONE), 337 TYPE(PERIPHC_USB2_HSIC_TRK, CLOCK_TYPE_NONE), 338 TYPE(PERIPHC_PEX_SATA_USB_RX_BYP, CLOCK_TYPE_NONE), 339 340 /* 0x90 */ 341 TYPE(PERIPHC_MAUD, CLOCK_TYPE_NONE), 342 TYPE(PERIPHC_TSECB, CLOCK_TYPE_NONE), 343 }; 344 345 /* 346 * This array translates a periph_id to a periphc_internal_id 347 * 348 * Not present/matched up: 349 * uint vi_sensor; _VI_SENSOR_0, 0x1A8 350 * SPDIF - which is both 0x08 and 0x0c 351 * 352 */ 353 #define NONE(name) (-1) 354 #define OFFSET(name, value) PERIPHC_ ## name 355 #define INTERNAL_ID(id) (id & 0x000000ff) 356 static s8 periph_id_to_internal_id[PERIPH_ID_COUNT] = { 357 /* Low word: 31:0 */ 358 NONE(CPU), 359 NONE(COP), 360 NONE(TRIGSYS), 361 NONE(ISPB), 362 NONE(RESERVED4), 363 NONE(TMR), 364 PERIPHC_UART1, 365 PERIPHC_UART2, /* and vfir 0x68 */ 366 367 /* 8 */ 368 NONE(GPIO), 369 PERIPHC_SDMMC2, 370 PERIPHC_SPDIF_IN, 371 PERIPHC_I2S2, 372 PERIPHC_I2C1, 373 NONE(RESERVED13), 374 PERIPHC_SDMMC1, 375 PERIPHC_SDMMC4, 376 377 /* 16 */ 378 NONE(TCW), 379 PERIPHC_PWM, 380 PERIPHC_I2S3, 381 NONE(RESERVED19), 382 PERIPHC_VI, 383 NONE(RESERVED21), 384 NONE(USBD), 385 NONE(ISP), 386 387 /* 24 */ 388 NONE(RESERVED24), 389 NONE(RESERVED25), 390 PERIPHC_DISP2, 391 PERIPHC_DISP1, 392 PERIPHC_HOST1X, 393 NONE(VCP), 394 PERIPHC_I2S1, 395 NONE(CACHE2), 396 397 /* Middle word: 63:32 */ 398 NONE(MEM), 399 NONE(AHBDMA), 400 NONE(APBDMA), 401 NONE(RESERVED35), 402 NONE(RESERVED36), 403 NONE(STAT_MON), 404 NONE(RESERVED38), 405 NONE(FUSE), 406 407 /* 40 */ 408 NONE(KFUSE), 409 PERIPHC_SBC1, /* SBCx = SPIx */ 410 PERIPHC_NOR, 411 NONE(RESERVED43), 412 PERIPHC_SBC2, 413 NONE(XIO), 414 PERIPHC_SBC3, 415 PERIPHC_I2C5, 416 417 /* 48 */ 418 NONE(DSI), 419 NONE(RESERVED49), 420 PERIPHC_HSI, 421 NONE(RESERVED51), 422 NONE(CSI), 423 NONE(RESERVED53), 424 PERIPHC_I2C2, 425 PERIPHC_UART3, 426 427 /* 56 */ 428 NONE(MIPI_CAL), 429 PERIPHC_EMC, 430 NONE(USB2), 431 NONE(USB3), 432 NONE(RESERVED60), 433 PERIPHC_VDE, 434 NONE(BSEA), 435 NONE(BSEV), 436 437 /* Upper word 95:64 */ 438 NONE(RESERVED64), 439 PERIPHC_UART4, 440 PERIPHC_UART5, 441 PERIPHC_I2C3, 442 PERIPHC_SBC4, 443 PERIPHC_SDMMC3, 444 NONE(PCIE), 445 PERIPHC_OWR, 446 447 /* 72 */ 448 NONE(AFI), 449 PERIPHC_CSITE, 450 NONE(PCIEXCLK), 451 NONE(AVPUCQ), 452 NONE(LA), 453 NONE(TRACECLKIN), 454 NONE(SOC_THERM), 455 NONE(DTV), 456 457 /* 80 */ 458 NONE(RESERVED80), 459 PERIPHC_I2CSLOW, 460 NONE(DSIB), 461 PERIPHC_TSEC, 462 NONE(RESERVED84), 463 NONE(RESERVED85), 464 NONE(RESERVED86), 465 NONE(EMUCIF), 466 467 /* 88 */ 468 NONE(RESERVED88), 469 NONE(XUSB_HOST), 470 NONE(RESERVED90), 471 PERIPHC_MSENC, 472 NONE(RESERVED92), 473 NONE(RESERVED93), 474 NONE(RESERVED94), 475 NONE(XUSB_DEV), 476 477 /* V word: 31:0 */ 478 NONE(CPUG), 479 NONE(CPULP), 480 NONE(V_RESERVED2), 481 PERIPHC_MSELECT, 482 NONE(V_RESERVED4), 483 PERIPHC_I2S4, 484 PERIPHC_I2S5, 485 PERIPHC_I2C4, 486 487 /* 104 */ 488 PERIPHC_SBC5, 489 PERIPHC_SBC6, 490 PERIPHC_AUDIO, 491 NONE(APBIF), 492 NONE(V_RESERVED12), 493 NONE(V_RESERVED13), 494 NONE(V_RESERVED14), 495 PERIPHC_HDA2CODEC2X, 496 497 /* 112 */ 498 NONE(ATOMICS), 499 NONE(V_RESERVED17), 500 NONE(V_RESERVED18), 501 NONE(V_RESERVED19), 502 NONE(V_RESERVED20), 503 NONE(V_RESERVED21), 504 NONE(V_RESERVED22), 505 PERIPHC_ACTMON, 506 507 /* 120 */ 508 NONE(EXTPERIPH1), 509 NONE(EXTPERIPH2), 510 NONE(EXTPERIPH3), 511 NONE(OOB), 512 PERIPHC_SATA, 513 PERIPHC_HDA, 514 NONE(TZRAM), 515 NONE(SE), 516 517 /* W word: 31:0 */ 518 NONE(HDA2HDMICODEC), 519 NONE(SATACOLD), 520 NONE(W_RESERVED2), 521 NONE(W_RESERVED3), 522 NONE(W_RESERVED4), 523 NONE(W_RESERVED5), 524 NONE(W_RESERVED6), 525 NONE(W_RESERVED7), 526 527 /* 136 */ 528 NONE(CEC), 529 NONE(W_RESERVED9), 530 NONE(W_RESERVED10), 531 NONE(W_RESERVED11), 532 NONE(W_RESERVED12), 533 NONE(W_RESERVED13), 534 NONE(XUSB_PADCTL), 535 NONE(W_RESERVED15), 536 537 /* 144 */ 538 NONE(W_RESERVED16), 539 NONE(W_RESERVED17), 540 NONE(W_RESERVED18), 541 NONE(W_RESERVED19), 542 NONE(W_RESERVED20), 543 NONE(ENTROPY), 544 NONE(DDS), 545 NONE(W_RESERVED23), 546 547 /* 152 */ 548 NONE(W_RESERVED24), 549 NONE(W_RESERVED25), 550 NONE(W_RESERVED26), 551 NONE(DVFS), 552 NONE(XUSB_SS), 553 NONE(W_RESERVED29), 554 NONE(W_RESERVED30), 555 NONE(W_RESERVED31), 556 557 /* X word: 31:0 */ 558 NONE(SPARE), 559 NONE(X_RESERVED1), 560 NONE(X_RESERVED2), 561 NONE(X_RESERVED3), 562 NONE(CAM_MCLK), 563 NONE(CAM_MCLK2), 564 PERIPHC_I2C6, 565 NONE(X_RESERVED7), 566 567 /* 168 */ 568 NONE(X_RESERVED8), 569 NONE(X_RESERVED9), 570 NONE(X_RESERVED10), 571 NONE(VIM2_CLK), 572 NONE(X_RESERVED12), 573 NONE(X_RESERVED13), 574 NONE(EMC_DLL), 575 NONE(X_RESERVED15), 576 577 /* 176 */ 578 NONE(X_RESERVED16), 579 NONE(CLK72MHZ), 580 NONE(VIC), 581 NONE(X_RESERVED19), 582 NONE(X_RESERVED20), 583 NONE(DPAUX), 584 NONE(SOR0), 585 NONE(X_RESERVED23), 586 587 /* 184 */ 588 NONE(GPU), 589 NONE(X_RESERVED25), 590 NONE(X_RESERVED26), 591 NONE(X_RESERVED27), 592 NONE(X_RESERVED28), 593 NONE(X_RESERVED29), 594 NONE(X_RESERVED30), 595 NONE(X_RESERVED31), 596 597 /* Y: 192 (192 - 223) */ 598 NONE(Y_RESERVED0), 599 PERIPHC_SDMMC_LEGACY_TM, 600 PERIPHC_NVDEC, 601 PERIPHC_NVJPG, 602 NONE(Y_RESERVED4), 603 PERIPHC_DMIC3, /* 197 */ 604 PERIPHC_APE, /* 198 */ 605 NONE(Y_RESERVED7), 606 607 /* 200 */ 608 NONE(Y_RESERVED8), 609 NONE(Y_RESERVED9), 610 NONE(Y_RESERVED10), 611 NONE(Y_RESERVED11), 612 NONE(Y_RESERVED12), 613 NONE(Y_RESERVED13), 614 NONE(Y_RESERVED14), 615 NONE(Y_RESERVED15), 616 617 /* 208 */ 618 PERIPHC_VI_I2C, /* 208 */ 619 NONE(Y_RESERVED17), 620 NONE(Y_RESERVED18), 621 PERIPHC_QSPI, /* 211 */ 622 NONE(Y_RESERVED20), 623 NONE(Y_RESERVED21), 624 NONE(Y_RESERVED22), 625 NONE(Y_RESERVED23), 626 627 /* 216 */ 628 NONE(Y_RESERVED24), 629 NONE(Y_RESERVED25), 630 NONE(Y_RESERVED26), 631 PERIPHC_NVENC, /* 219 */ 632 NONE(Y_RESERVED28), 633 NONE(Y_RESERVED29), 634 NONE(Y_RESERVED30), 635 NONE(Y_RESERVED31), 636 }; 637 638 /* 639 * PLL divider shift/mask tables for all PLL IDs. 640 */ 641 struct clk_pll_info tegra_pll_info_table[CLOCK_ID_PLL_COUNT] = { 642 /* 643 * NOTE: If kcp_mask/kvco_mask == 0, they're not used in that PLL (PLLC, etc.) 644 * If lock_ena or lock_det are >31, they're not used in that PLL (PLLC, etc.) 645 */ 646 { .m_shift = 0, .m_mask = 0xFF, .n_shift = 10, .n_mask = 0xFF, .p_shift = 20, .p_mask = 0x1F, 647 .lock_ena = 32, .lock_det = 27, .kcp_shift = 0, .kcp_mask = 0, .kvco_shift = 0, .kvco_mask = 0 }, /* PLLC */ 648 { .m_shift = 0, .m_mask = 0xFF, .n_shift = 8, .n_mask = 0xFF, .p_shift = 20, .p_mask = 0x1F, 649 .lock_ena = 4, .lock_det = 27, .kcp_shift = 1, .kcp_mask = 3, .kvco_shift = 0, .kvco_mask = 1 }, /* PLLM */ 650 { .m_shift = 0, .m_mask = 0xFF, .n_shift = 10, .n_mask = 0xFF, .p_shift = 20, .p_mask = 0x1F, 651 .lock_ena = 18, .lock_det = 27, .kcp_shift = 0, .kcp_mask = 3, .kvco_shift = 2, .kvco_mask = 1 }, /* PLLP */ 652 { .m_shift = 0, .m_mask = 0xFF, .n_shift = 8, .n_mask = 0xFF, .p_shift = 20, .p_mask = 0x1F, 653 .lock_ena = 28, .lock_det = 27, .kcp_shift = 25, .kcp_mask = 3, .kvco_shift = 24, .kvco_mask = 1 }, /* PLLA */ 654 { .m_shift = 0, .m_mask = 0xFF, .n_shift = 8, .n_mask = 0xFF, .p_shift = 16, .p_mask = 0x1F, 655 .lock_ena = 29, .lock_det = 27, .kcp_shift = 25, .kcp_mask = 3, .kvco_shift = 24, .kvco_mask = 1 }, /* PLLU */ 656 { .m_shift = 0, .m_mask = 0xFF, .n_shift = 11, .n_mask = 0xFF, .p_shift = 20, .p_mask = 0x07, 657 .lock_ena = 18, .lock_det = 27, .kcp_shift = 23, .kcp_mask = 3, .kvco_shift = 22, .kvco_mask = 1 }, /* PLLD */ 658 { .m_shift = 0, .m_mask = 0xFF, .n_shift = 8, .n_mask = 0xFF, .p_shift = 20, .p_mask = 0x1F, 659 .lock_ena = 18, .lock_det = 27, .kcp_shift = 1, .kcp_mask = 3, .kvco_shift = 0, .kvco_mask = 1 }, /* PLLX */ 660 { .m_shift = 0, .m_mask = 0xFF, .n_shift = 8, .n_mask = 0xFF, .p_shift = 0, .p_mask = 0, 661 .lock_ena = 9, .lock_det = 11, .kcp_shift = 6, .kcp_mask = 3, .kvco_shift = 0, .kvco_mask = 1 }, /* PLLE */ 662 { .m_shift = 0, .m_mask = 0, .n_shift = 0, .n_mask = 0, .p_shift = 0, .p_mask = 0, 663 .lock_ena = 0, .lock_det = 0, .kcp_shift = 0, .kcp_mask = 0, .kvco_shift = 0, .kvco_mask = 0 }, /* PLLS (gone)*/ 664 { .m_shift = 0, .m_mask = 0xFF, .n_shift = 8, .n_mask = 0xFF, .p_shift = 19, .p_mask = 0x1F, 665 .lock_ena = 30, .lock_det = 27, .kcp_shift = 25, .kcp_mask = 3, .kvco_shift = 24, .kvco_mask = 1 }, /* PLLDP */ 666 }; 667 668 /* 669 * Get the oscillator frequency, from the corresponding hardware configuration 670 * field. Note that Tegra30+ support 3 new higher freqs, but we map back 671 * to the old T20 freqs. Support for the higher oscillators is TBD. 672 */ 673 enum clock_osc_freq clock_get_osc_freq(void) 674 { 675 struct clk_rst_ctlr *clkrst = 676 (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE; 677 u32 reg; 678 679 reg = readl(&clkrst->crc_osc_ctrl); 680 reg = (reg & OSC_FREQ_MASK) >> OSC_FREQ_SHIFT; 681 /* 682 * 0 = 13MHz, 1 = 16.8MHz, 4 = 19.2MHz, 5 = 38.4MHz, 683 * 8 = 12MHz, 9 = 48MHz, 12 = 26MHz 684 */ 685 if (reg == 5) { 686 debug("OSC_FREQ is 38.4MHz (%d) ...\n", reg); 687 /* Map it to the 5th CLOCK_OSC_ enum, i.e. 4 */ 688 return 4; 689 } 690 691 /* 692 * Map to most common (T20) freqs (except 38.4, handled above): 693 * 13/16.8 = 0, 19.2 = 1, 12/48 = 2, 26 = 3 694 */ 695 return reg >> 2; 696 } 697 698 /* Returns a pointer to the clock source register for a peripheral */ 699 u32 *get_periph_source_reg(enum periph_id periph_id) 700 { 701 struct clk_rst_ctlr *clkrst = 702 (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE; 703 enum periphc_internal_id internal_id; 704 705 /* Coresight is a special case */ 706 if (periph_id == PERIPH_ID_CSI) 707 return &clkrst->crc_clk_src[PERIPH_ID_CSI+1]; 708 709 assert(periph_id >= PERIPH_ID_FIRST && periph_id < PERIPH_ID_COUNT); 710 internal_id = INTERNAL_ID(periph_id_to_internal_id[periph_id]); 711 assert(internal_id != -1); 712 713 if (internal_id < PERIPHC_VW_FIRST) 714 /* L, H, U */ 715 return &clkrst->crc_clk_src[internal_id]; 716 717 if (internal_id < PERIPHC_X_FIRST) { 718 /* VW */ 719 internal_id -= PERIPHC_VW_FIRST; 720 return &clkrst->crc_clk_src_vw[internal_id]; 721 } 722 723 if (internal_id < PERIPHC_Y_FIRST) { 724 /* X */ 725 internal_id -= PERIPHC_X_FIRST; 726 return &clkrst->crc_clk_src_x[internal_id]; 727 } 728 729 /* Y */ 730 internal_id -= PERIPHC_Y_FIRST; 731 return &clkrst->crc_clk_src_y[internal_id]; 732 } 733 734 /** 735 * Given a peripheral ID and the required source clock, this returns which 736 * value should be programmed into the source mux for that peripheral. 737 * 738 * There is special code here to handle the one source type with 5 sources. 739 * 740 * @param periph_id peripheral to start 741 * @param source PLL id of required parent clock 742 * @param mux_bits Set to number of bits in mux register: 2 or 4 743 * @param divider_bits Set to number of divider bits (8 or 16) 744 * @return mux value (0-4, or -1 if not found) 745 */ 746 int get_periph_clock_source(enum periph_id periph_id, 747 enum clock_id parent, int *mux_bits, int *divider_bits) 748 { 749 enum clock_type_id type; 750 enum periphc_internal_id internal_id; 751 int mux; 752 753 assert(clock_periph_id_isvalid(periph_id)); 754 755 internal_id = INTERNAL_ID(periph_id_to_internal_id[periph_id]); 756 assert(periphc_internal_id_isvalid(internal_id)); 757 758 type = clock_periph_type[internal_id]; 759 assert(clock_type_id_isvalid(type)); 760 761 *mux_bits = clock_source[type][CLOCK_MAX_MUX]; 762 763 if (type == CLOCK_TYPE_PC2CC3M_T16) 764 *divider_bits = 16; 765 else 766 *divider_bits = 8; 767 768 for (mux = 0; mux < CLOCK_MAX_MUX; mux++) 769 if (clock_source[type][mux] == parent) 770 return mux; 771 772 /* if we get here, either us or the caller has made a mistake */ 773 printf("Caller requested bad clock: periph=%d, parent=%d\n", periph_id, 774 parent); 775 return -1; 776 } 777 778 void clock_set_enable(enum periph_id periph_id, int enable) 779 { 780 struct clk_rst_ctlr *clkrst = 781 (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE; 782 u32 *clk; 783 u32 reg; 784 785 /* Enable/disable the clock to this peripheral */ 786 assert(clock_periph_id_isvalid(periph_id)); 787 if ((int)periph_id < (int)PERIPH_ID_VW_FIRST) 788 clk = &clkrst->crc_clk_out_enb[PERIPH_REG(periph_id)]; 789 else if ((int)periph_id < (int)PERIPH_ID_X_FIRST) 790 clk = &clkrst->crc_clk_out_enb_vw[PERIPH_REG(periph_id)]; 791 else if ((int)periph_id < (int)PERIPH_ID_Y_FIRST) 792 clk = &clkrst->crc_clk_out_enb_x; 793 else 794 clk = &clkrst->crc_clk_out_enb_y; 795 796 reg = readl(clk); 797 if (enable) 798 reg |= PERIPH_MASK(periph_id); 799 else 800 reg &= ~PERIPH_MASK(periph_id); 801 writel(reg, clk); 802 } 803 804 void reset_set_enable(enum periph_id periph_id, int enable) 805 { 806 struct clk_rst_ctlr *clkrst = 807 (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE; 808 u32 *reset; 809 u32 reg; 810 811 /* Enable/disable reset to the peripheral */ 812 assert(clock_periph_id_isvalid(periph_id)); 813 if (periph_id < PERIPH_ID_VW_FIRST) 814 reset = &clkrst->crc_rst_dev[PERIPH_REG(periph_id)]; 815 else if ((int)periph_id < (int)PERIPH_ID_X_FIRST) 816 reset = &clkrst->crc_rst_dev_vw[PERIPH_REG(periph_id)]; 817 else if ((int)periph_id < (int)PERIPH_ID_Y_FIRST) 818 reset = &clkrst->crc_rst_devices_x; 819 else 820 reset = &clkrst->crc_rst_devices_y; 821 822 reg = readl(reset); 823 if (enable) 824 reg |= PERIPH_MASK(periph_id); 825 else 826 reg &= ~PERIPH_MASK(periph_id); 827 writel(reg, reset); 828 } 829 830 #ifdef CONFIG_OF_CONTROL 831 /* 832 * Convert a device tree clock ID to our peripheral ID. They are mostly 833 * the same but we are very cautious so we check that a valid clock ID is 834 * provided. 835 * 836 * @param clk_id Clock ID according to tegra210 device tree binding 837 * @return peripheral ID, or PERIPH_ID_NONE if the clock ID is invalid 838 */ 839 enum periph_id clk_id_to_periph_id(int clk_id) 840 { 841 if (clk_id > PERIPH_ID_COUNT) 842 return PERIPH_ID_NONE; 843 844 switch (clk_id) { 845 case PERIPH_ID_RESERVED4: 846 case PERIPH_ID_RESERVED25: 847 case PERIPH_ID_RESERVED35: 848 case PERIPH_ID_RESERVED36: 849 case PERIPH_ID_RESERVED38: 850 case PERIPH_ID_RESERVED43: 851 case PERIPH_ID_RESERVED49: 852 case PERIPH_ID_RESERVED53: 853 case PERIPH_ID_RESERVED64: 854 case PERIPH_ID_RESERVED84: 855 case PERIPH_ID_RESERVED85: 856 case PERIPH_ID_RESERVED86: 857 case PERIPH_ID_RESERVED88: 858 case PERIPH_ID_RESERVED90: 859 case PERIPH_ID_RESERVED92: 860 case PERIPH_ID_RESERVED93: 861 case PERIPH_ID_RESERVED94: 862 case PERIPH_ID_V_RESERVED2: 863 case PERIPH_ID_V_RESERVED4: 864 case PERIPH_ID_V_RESERVED17: 865 case PERIPH_ID_V_RESERVED18: 866 case PERIPH_ID_V_RESERVED19: 867 case PERIPH_ID_V_RESERVED20: 868 case PERIPH_ID_V_RESERVED21: 869 case PERIPH_ID_V_RESERVED22: 870 case PERIPH_ID_W_RESERVED2: 871 case PERIPH_ID_W_RESERVED3: 872 case PERIPH_ID_W_RESERVED4: 873 case PERIPH_ID_W_RESERVED5: 874 case PERIPH_ID_W_RESERVED6: 875 case PERIPH_ID_W_RESERVED7: 876 case PERIPH_ID_W_RESERVED9: 877 case PERIPH_ID_W_RESERVED10: 878 case PERIPH_ID_W_RESERVED11: 879 case PERIPH_ID_W_RESERVED12: 880 case PERIPH_ID_W_RESERVED13: 881 case PERIPH_ID_W_RESERVED15: 882 case PERIPH_ID_W_RESERVED16: 883 case PERIPH_ID_W_RESERVED17: 884 case PERIPH_ID_W_RESERVED18: 885 case PERIPH_ID_W_RESERVED19: 886 case PERIPH_ID_W_RESERVED20: 887 case PERIPH_ID_W_RESERVED23: 888 case PERIPH_ID_W_RESERVED29: 889 case PERIPH_ID_W_RESERVED30: 890 case PERIPH_ID_W_RESERVED31: 891 return PERIPH_ID_NONE; 892 default: 893 return clk_id; 894 } 895 } 896 #endif /* CONFIG_OF_CONTROL */ 897 898 /* 899 * T210 redefines PLLP_OUT2 as PLLP_VCO/DIVP, so do different OUT1-4 setup here. 900 * PLLP_BASE/MISC/etc. is already set up for 408MHz in the BootROM. 901 */ 902 void tegra210_setup_pllp(void) 903 { 904 struct clk_rst_ctlr *clkrst = (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE; 905 u32 reg; 906 907 /* Set PLLP_OUT1, 3 & 4 freqs to 9.6, 102 & 204MHz */ 908 909 /* OUT1 */ 910 /* Assert RSTN before enable */ 911 reg = PLLP_OUT1_RSTN_EN; 912 writel(reg, &clkrst->crc_pll[CLOCK_ID_PERIPH].pll_out[0]); 913 /* Set divisor and reenable */ 914 reg = (IN_408_OUT_9_6_DIVISOR << PLLP_OUT1_RATIO) 915 | PLLP_OUT1_OVR | PLLP_OUT1_CLKEN | PLLP_OUT1_RSTN_DIS; 916 writel(reg, &clkrst->crc_pll[CLOCK_ID_PERIPH].pll_out[0]); 917 918 /* OUT3, 4 */ 919 /* Assert RSTN before enable */ 920 reg = PLLP_OUT4_RSTN_EN | PLLP_OUT3_RSTN_EN; 921 writel(reg, &clkrst->crc_pll[CLOCK_ID_PERIPH].pll_out[1]); 922 /* Set divisor and reenable */ 923 reg = (IN_408_OUT_204_DIVISOR << PLLP_OUT4_RATIO) 924 | PLLP_OUT4_OVR | PLLP_OUT4_CLKEN | PLLP_OUT4_RSTN_DIS 925 | (IN_408_OUT_102_DIVISOR << PLLP_OUT3_RATIO) 926 | PLLP_OUT3_OVR | PLLP_OUT3_CLKEN | PLLP_OUT3_RSTN_DIS; 927 writel(reg, &clkrst->crc_pll[CLOCK_ID_PERIPH].pll_out[1]); 928 929 /* 930 * NOTE: If you want to change PLLP_OUT2 away from 204MHz, 931 * you can change PLLP_BASE DIVP here. Currently defaults 932 * to 1, which is 2^1, or 2, so PLLP_OUT2 is 204MHz. 933 * See Table 13 in section 5.1.4 in T210 TRM for more info. 934 */ 935 } 936 937 void clock_early_init(void) 938 { 939 struct clk_rst_ctlr *clkrst = 940 (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE; 941 struct clk_pll_info *pllinfo = &tegra_pll_info_table[CLOCK_ID_DISPLAY]; 942 u32 data; 943 944 tegra210_setup_pllp(); 945 946 /* 947 * PLLC output frequency set to 600Mhz 948 * PLLD output frequency set to 925Mhz 949 */ 950 switch (clock_get_osc_freq()) { 951 case CLOCK_OSC_FREQ_12_0: /* OSC is 12Mhz */ 952 clock_set_rate(CLOCK_ID_CGENERAL, 600, 12, 0, 8); 953 clock_set_rate(CLOCK_ID_DISPLAY, 925, 12, 0, 12); 954 break; 955 956 case CLOCK_OSC_FREQ_26_0: /* OSC is 26Mhz */ 957 clock_set_rate(CLOCK_ID_CGENERAL, 600, 26, 0, 8); 958 clock_set_rate(CLOCK_ID_DISPLAY, 925, 26, 0, 12); 959 break; 960 961 case CLOCK_OSC_FREQ_13_0: /* OSC is 13Mhz */ 962 clock_set_rate(CLOCK_ID_CGENERAL, 600, 13, 0, 8); 963 clock_set_rate(CLOCK_ID_DISPLAY, 925, 13, 0, 12); 964 break; 965 case CLOCK_OSC_FREQ_19_2: 966 clock_set_rate(CLOCK_ID_CGENERAL, 125, 4, 0, 0); 967 clock_set_rate(CLOCK_ID_DISPLAY, 96, 2, 0, 12); 968 break; 969 case CLOCK_OSC_FREQ_38_4: 970 clock_set_rate(CLOCK_ID_CGENERAL, 125, 8, 0, 0); 971 clock_set_rate(CLOCK_ID_DISPLAY, 96, 4, 0, 0); 972 break; 973 default: 974 /* 975 * These are not supported. It is too early to print a 976 * message and the UART likely won't work anyway due to the 977 * oscillator being wrong. 978 */ 979 break; 980 } 981 982 /* PLLC_MISC1: Turn IDDQ off. NOTE: T210 PLLC_MISC_1 maps to pll_misc */ 983 clrbits_le32(&clkrst->crc_pll[CLOCK_ID_CGENERAL].pll_misc, 984 (1 << PLLC_IDDQ)); 985 udelay(2); 986 987 /* 988 * PLLC_MISC: Take PLLC out of reset. NOTE: T210 PLLC_MISC maps 989 * to pll_out[1] 990 */ 991 clrbits_le32(&clkrst->crc_pll[CLOCK_ID_CGENERAL].pll_out[1], 992 (1 << PLLC_RESET)); 993 udelay(2); 994 995 /* PLLD_MISC: Set CLKENABLE and LOCK_DETECT bits */ 996 data = (1 << PLLD_ENABLE_CLK) | (1 << pllinfo->lock_ena); 997 writel(data, &clkrst->crc_pll[CLOCK_ID_DISPLAY].pll_misc); 998 udelay(2); 999 } 1000 1001 void arch_timer_init(void) 1002 { 1003 struct sysctr_ctlr *sysctr = (struct sysctr_ctlr *)NV_PA_TSC_BASE; 1004 u32 freq, val; 1005 1006 freq = clock_get_rate(CLOCK_ID_OSC); 1007 debug("%s: osc freq is %dHz [0x%08X]\n", __func__, freq, freq); 1008 1009 /* ARM CNTFRQ */ 1010 #ifndef CONFIG_ARM64 1011 asm("mcr p15, 0, %0, c14, c0, 0\n" : : "r" (freq)); 1012 #endif 1013 1014 /* Only Tegra114+ has the System Counter regs */ 1015 debug("%s: setting CNTFID0 to 0x%08X\n", __func__, freq); 1016 writel(freq, &sysctr->cntfid0); 1017 1018 val = readl(&sysctr->cntcr); 1019 val |= TSC_CNTCR_ENABLE | TSC_CNTCR_HDBG; 1020 writel(val, &sysctr->cntcr); 1021 debug("%s: TSC CNTCR = 0x%08X\n", __func__, val); 1022 } 1023 1024 #define PLLE_SS_CNTL 0x68 1025 #define PLLE_SS_CNTL_SSCINCINTR(x) (((x) & 0x3f) << 24) 1026 #define PLLE_SS_CNTL_SSCINC(x) (((x) & 0xff) << 16) 1027 #define PLLE_SS_CNTL_SSCINVERT (1 << 15) 1028 #define PLLE_SS_CNTL_SSCCENTER (1 << 14) 1029 #define PLLE_SS_CNTL_SSCBYP (1 << 12) 1030 #define PLLE_SS_CNTL_INTERP_RESET (1 << 11) 1031 #define PLLE_SS_CNTL_BYPASS_SS (1 << 10) 1032 #define PLLE_SS_CNTL_SSCMAX(x) (((x) & 0x1ff) << 0) 1033 1034 #define PLLE_BASE 0x0e8 1035 #define PLLE_BASE_ENABLE (1 << 30) 1036 #define PLLE_BASE_LOCK_OVERRIDE (1 << 29) 1037 #define PLLE_BASE_PLDIV_CML(x) (((x) & 0xf) << 24) 1038 #define PLLE_BASE_NDIV(x) (((x) & 0xff) << 8) 1039 #define PLLE_BASE_MDIV(x) (((x) & 0xff) << 0) 1040 1041 #define PLLE_MISC 0x0ec 1042 #define PLLE_MISC_IDDQ_SWCTL (1 << 14) 1043 #define PLLE_MISC_IDDQ_OVERRIDE (1 << 13) 1044 #define PLLE_MISC_LOCK_ENABLE (1 << 9) 1045 #define PLLE_MISC_PTS (1 << 8) 1046 #define PLLE_MISC_VREG_BG_CTRL(x) (((x) & 0x3) << 4) 1047 #define PLLE_MISC_VREG_CTRL(x) (((x) & 0x3) << 2) 1048 1049 #define PLLE_AUX 0x48c 1050 #define PLLE_AUX_SEQ_ENABLE (1 << 24) 1051 #define PLLE_AUX_ENABLE_SWCTL (1 << 4) 1052 1053 int tegra_plle_enable(void) 1054 { 1055 unsigned int m = 1, n = 200, cpcon = 13; 1056 u32 value; 1057 1058 value = readl(NV_PA_CLK_RST_BASE + PLLE_BASE); 1059 value &= ~PLLE_BASE_LOCK_OVERRIDE; 1060 writel(value, NV_PA_CLK_RST_BASE + PLLE_BASE); 1061 1062 value = readl(NV_PA_CLK_RST_BASE + PLLE_AUX); 1063 value |= PLLE_AUX_ENABLE_SWCTL; 1064 value &= ~PLLE_AUX_SEQ_ENABLE; 1065 writel(value, NV_PA_CLK_RST_BASE + PLLE_AUX); 1066 1067 udelay(1); 1068 1069 value = readl(NV_PA_CLK_RST_BASE + PLLE_MISC); 1070 value |= PLLE_MISC_IDDQ_SWCTL; 1071 value &= ~PLLE_MISC_IDDQ_OVERRIDE; 1072 value |= PLLE_MISC_LOCK_ENABLE; 1073 value |= PLLE_MISC_PTS; 1074 value |= PLLE_MISC_VREG_BG_CTRL(3); 1075 value |= PLLE_MISC_VREG_CTRL(2); 1076 writel(value, NV_PA_CLK_RST_BASE + PLLE_MISC); 1077 1078 udelay(5); 1079 1080 value = readl(NV_PA_CLK_RST_BASE + PLLE_SS_CNTL); 1081 value |= PLLE_SS_CNTL_SSCBYP | PLLE_SS_CNTL_INTERP_RESET | 1082 PLLE_SS_CNTL_BYPASS_SS; 1083 writel(value, NV_PA_CLK_RST_BASE + PLLE_SS_CNTL); 1084 1085 value = readl(NV_PA_CLK_RST_BASE + PLLE_BASE); 1086 value &= ~PLLE_BASE_PLDIV_CML(0xf); 1087 value &= ~PLLE_BASE_NDIV(0xff); 1088 value &= ~PLLE_BASE_MDIV(0xff); 1089 value |= PLLE_BASE_PLDIV_CML(cpcon); 1090 value |= PLLE_BASE_NDIV(n); 1091 value |= PLLE_BASE_MDIV(m); 1092 writel(value, NV_PA_CLK_RST_BASE + PLLE_BASE); 1093 1094 udelay(1); 1095 1096 value = readl(NV_PA_CLK_RST_BASE + PLLE_BASE); 1097 value |= PLLE_BASE_ENABLE; 1098 writel(value, NV_PA_CLK_RST_BASE + PLLE_BASE); 1099 1100 /* wait for lock */ 1101 udelay(300); 1102 1103 value = readl(NV_PA_CLK_RST_BASE + PLLE_SS_CNTL); 1104 value &= ~PLLE_SS_CNTL_SSCINVERT; 1105 value &= ~PLLE_SS_CNTL_SSCCENTER; 1106 1107 value &= ~PLLE_SS_CNTL_SSCINCINTR(0x3f); 1108 value &= ~PLLE_SS_CNTL_SSCINC(0xff); 1109 value &= ~PLLE_SS_CNTL_SSCMAX(0x1ff); 1110 1111 value |= PLLE_SS_CNTL_SSCINCINTR(0x20); 1112 value |= PLLE_SS_CNTL_SSCINC(0x01); 1113 value |= PLLE_SS_CNTL_SSCMAX(0x25); 1114 1115 writel(value, NV_PA_CLK_RST_BASE + PLLE_SS_CNTL); 1116 1117 value = readl(NV_PA_CLK_RST_BASE + PLLE_SS_CNTL); 1118 value &= ~PLLE_SS_CNTL_SSCBYP; 1119 value &= ~PLLE_SS_CNTL_BYPASS_SS; 1120 writel(value, NV_PA_CLK_RST_BASE + PLLE_SS_CNTL); 1121 1122 udelay(1); 1123 1124 value = readl(NV_PA_CLK_RST_BASE + PLLE_SS_CNTL); 1125 value &= ~PLLE_SS_CNTL_INTERP_RESET; 1126 writel(value, NV_PA_CLK_RST_BASE + PLLE_SS_CNTL); 1127 1128 udelay(1); 1129 1130 return 0; 1131 } 1132