1 /* 2 * (C) Copyright 2013-2015 3 * NVIDIA Corporation <www.nvidia.com> 4 * 5 * SPDX-License-Identifier: GPL-2.0+ 6 */ 7 8 /* Tegra210 Clock control functions */ 9 10 #include <common.h> 11 #include <asm/io.h> 12 #include <asm/arch/clock.h> 13 #include <asm/arch/sysctr.h> 14 #include <asm/arch/tegra.h> 15 #include <asm/arch-tegra/clk_rst.h> 16 #include <asm/arch-tegra/timer.h> 17 #include <div64.h> 18 #include <fdtdec.h> 19 20 /* 21 * Clock types that we can use as a source. The Tegra210 has muxes for the 22 * peripheral clocks, and in most cases there are four options for the clock 23 * source. This gives us a clock 'type' and exploits what commonality exists 24 * in the device. 25 * 26 * Letters are obvious, except for T which means CLK_M, and S which means the 27 * clock derived from 32KHz. Beware that CLK_M (also called OSC in the 28 * datasheet) and PLL_M are different things. The former is the basic 29 * clock supplied to the SOC from an external oscillator. The latter is the 30 * memory clock PLL. 31 * 32 * See definitions in clock_id in the header file. 33 */ 34 enum clock_type_id { 35 CLOCK_TYPE_AXPT, /* PLL_A, PLL_X, PLL_P, CLK_M */ 36 CLOCK_TYPE_MCPA, /* and so on */ 37 CLOCK_TYPE_MCPT, 38 CLOCK_TYPE_PCM, 39 CLOCK_TYPE_PCMT, 40 CLOCK_TYPE_PDCT, 41 CLOCK_TYPE_ACPT, 42 CLOCK_TYPE_ASPTE, 43 CLOCK_TYPE_PMDACD2T, 44 CLOCK_TYPE_PCST, 45 46 CLOCK_TYPE_PC2CC3M, 47 CLOCK_TYPE_PC2CC3S_T, 48 CLOCK_TYPE_PC2CC3M_T, 49 CLOCK_TYPE_PC2CC3M_T16, /* PC2CC3M_T, but w/16-bit divisor (I2C) */ 50 CLOCK_TYPE_MC2CC3P_A, 51 CLOCK_TYPE_M, 52 CLOCK_TYPE_MCPTM2C2C3, 53 CLOCK_TYPE_PC2CC3T_S, 54 CLOCK_TYPE_AC2CC3P_TS2, 55 CLOCK_TYPE_PC01C00_C42C41TC40, 56 57 CLOCK_TYPE_COUNT, 58 CLOCK_TYPE_NONE = -1, /* invalid clock type */ 59 }; 60 61 enum { 62 CLOCK_MAX_MUX = 8 /* number of source options for each clock */ 63 }; 64 65 /* 66 * Clock source mux for each clock type. This just converts our enum into 67 * a list of mux sources for use by the code. 68 * 69 * Note: 70 * The extra column in each clock source array is used to store the mask 71 * bits in its register for the source. 72 */ 73 #define CLK(x) CLOCK_ID_ ## x 74 static enum clock_id clock_source[CLOCK_TYPE_COUNT][CLOCK_MAX_MUX+1] = { 75 { CLK(AUDIO), CLK(XCPU), CLK(PERIPH), CLK(OSC), 76 CLK(NONE), CLK(NONE), CLK(NONE), CLK(NONE), 77 MASK_BITS_31_30}, 78 { CLK(MEMORY), CLK(CGENERAL), CLK(PERIPH), CLK(AUDIO), 79 CLK(NONE), CLK(NONE), CLK(NONE), CLK(NONE), 80 MASK_BITS_31_30}, 81 { CLK(MEMORY), CLK(CGENERAL), CLK(PERIPH), CLK(OSC), 82 CLK(NONE), CLK(NONE), CLK(NONE), CLK(NONE), 83 MASK_BITS_31_30}, 84 { CLK(PERIPH), CLK(CGENERAL), CLK(MEMORY), CLK(NONE), 85 CLK(NONE), CLK(NONE), CLK(NONE), CLK(NONE), 86 MASK_BITS_31_30}, 87 { CLK(PERIPH), CLK(CGENERAL), CLK(MEMORY), CLK(OSC), 88 CLK(NONE), CLK(NONE), CLK(NONE), CLK(NONE), 89 MASK_BITS_31_30}, 90 { CLK(PERIPH), CLK(DISPLAY), CLK(CGENERAL), CLK(OSC), 91 CLK(NONE), CLK(NONE), CLK(NONE), CLK(NONE), 92 MASK_BITS_31_30}, 93 { CLK(AUDIO), CLK(CGENERAL), CLK(PERIPH), CLK(OSC), 94 CLK(NONE), CLK(NONE), CLK(NONE), CLK(NONE), 95 MASK_BITS_31_30}, 96 { CLK(AUDIO), CLK(SFROM32KHZ), CLK(PERIPH), CLK(OSC), 97 CLK(EPCI), CLK(NONE), CLK(NONE), CLK(NONE), 98 MASK_BITS_31_29}, 99 { CLK(PERIPH), CLK(MEMORY), CLK(DISPLAY), CLK(AUDIO), 100 CLK(CGENERAL), CLK(DISPLAY2), CLK(OSC), CLK(NONE), 101 MASK_BITS_31_29}, 102 { CLK(PERIPH), CLK(CGENERAL), CLK(SFROM32KHZ), CLK(OSC), 103 CLK(NONE), CLK(NONE), CLK(NONE), CLK(NONE), 104 MASK_BITS_31_28}, 105 106 /* Additional clock types on Tegra114+ */ 107 /* CLOCK_TYPE_PC2CC3M */ 108 { CLK(PERIPH), CLK(CGENERAL2), CLK(CGENERAL), CLK(CGENERAL3), 109 CLK(MEMORY), CLK(NONE), CLK(NONE), CLK(NONE), 110 MASK_BITS_31_29}, 111 /* CLOCK_TYPE_PC2CC3S_T */ 112 { CLK(PERIPH), CLK(CGENERAL2), CLK(CGENERAL), CLK(CGENERAL3), 113 CLK(SFROM32KHZ), CLK(NONE), CLK(OSC), CLK(NONE), 114 MASK_BITS_31_29}, 115 /* CLOCK_TYPE_PC2CC3M_T */ 116 { CLK(PERIPH), CLK(CGENERAL2), CLK(CGENERAL), CLK(CGENERAL3), 117 CLK(MEMORY), CLK(NONE), CLK(OSC), CLK(NONE), 118 MASK_BITS_31_29}, 119 /* CLOCK_TYPE_PC2CC3M_T, w/16-bit divisor (I2C) */ 120 { CLK(PERIPH), CLK(CGENERAL2), CLK(CGENERAL), CLK(CGENERAL3), 121 CLK(MEMORY), CLK(NONE), CLK(OSC), CLK(NONE), 122 MASK_BITS_31_29}, 123 /* CLOCK_TYPE_MC2CC3P_A */ 124 { CLK(MEMORY), CLK(CGENERAL2), CLK(CGENERAL), CLK(CGENERAL3), 125 CLK(PERIPH), CLK(NONE), CLK(AUDIO), CLK(NONE), 126 MASK_BITS_31_29}, 127 /* CLOCK_TYPE_M */ 128 { CLK(MEMORY), CLK(NONE), CLK(NONE), CLK(NONE), 129 CLK(NONE), CLK(NONE), CLK(NONE), CLK(NONE), 130 MASK_BITS_31_30}, 131 /* CLOCK_TYPE_MCPTM2C2C3 */ 132 { CLK(MEMORY), CLK(CGENERAL), CLK(PERIPH), CLK(OSC), 133 CLK(MEMORY2), CLK(CGENERAL2), CLK(CGENERAL3), CLK(NONE), 134 MASK_BITS_31_29}, 135 /* CLOCK_TYPE_PC2CC3T_S */ 136 { CLK(PERIPH), CLK(CGENERAL2), CLK(CGENERAL), CLK(CGENERAL3), 137 CLK(OSC), CLK(NONE), CLK(SFROM32KHZ), CLK(NONE), 138 MASK_BITS_31_29}, 139 /* CLOCK_TYPE_AC2CC3P_TS2 */ 140 { CLK(AUDIO), CLK(CGENERAL2), CLK(CGENERAL), CLK(CGENERAL3), 141 CLK(PERIPH), CLK(NONE), CLK(OSC), CLK(SRC2), 142 MASK_BITS_31_29}, 143 /* CLOCK_TYPE_PC01C00_C42C41TC40 */ 144 { CLK(PERIPH), CLK(CGENERAL_1), CLK(CGENERAL_0), CLK(NONE), 145 CLK(CGENERAL4_2), CLK(CGENERAL4_1), CLK(OSC), CLK(CGENERAL4_0), 146 MASK_BITS_31_29}, 147 }; 148 149 /* 150 * Clock type for each peripheral clock source. We put the name in each 151 * record just so it is easy to match things up 152 */ 153 #define TYPE(name, type) type 154 static enum clock_type_id clock_periph_type[PERIPHC_COUNT] = { 155 /* 0x00 */ 156 TYPE(PERIPHC_I2S2, CLOCK_TYPE_AXPT), 157 TYPE(PERIPHC_I2S3, CLOCK_TYPE_AXPT), 158 TYPE(PERIPHC_SPDIF_OUT, CLOCK_TYPE_AXPT), 159 TYPE(PERIPHC_SPDIF_IN, CLOCK_TYPE_PC2CC3M), 160 TYPE(PERIPHC_PWM, CLOCK_TYPE_PC2CC3S_T), 161 TYPE(PERIPHC_05h, CLOCK_TYPE_NONE), 162 TYPE(PERIPHC_SBC2, CLOCK_TYPE_PC2CC3M_T), 163 TYPE(PERIPHC_SBC3, CLOCK_TYPE_PC2CC3M_T), 164 165 /* 0x08 */ 166 TYPE(PERIPHC_08h, CLOCK_TYPE_NONE), 167 TYPE(PERIPHC_I2C1, CLOCK_TYPE_PC2CC3M_T16), 168 TYPE(PERIPHC_I2C5, CLOCK_TYPE_PC2CC3M_T16), 169 TYPE(PERIPHC_0bh, CLOCK_TYPE_NONE), 170 TYPE(PERIPHC_0ch, CLOCK_TYPE_NONE), 171 TYPE(PERIPHC_SBC1, CLOCK_TYPE_PC2CC3M_T), 172 TYPE(PERIPHC_DISP1, CLOCK_TYPE_PMDACD2T), 173 TYPE(PERIPHC_DISP2, CLOCK_TYPE_PMDACD2T), 174 175 /* 0x10 */ 176 TYPE(PERIPHC_10h, CLOCK_TYPE_NONE), 177 TYPE(PERIPHC_11h, CLOCK_TYPE_NONE), 178 TYPE(PERIPHC_VI, CLOCK_TYPE_MC2CC3P_A), 179 TYPE(PERIPHC_13h, CLOCK_TYPE_NONE), 180 TYPE(PERIPHC_SDMMC1, CLOCK_TYPE_PC2CC3M_T), 181 TYPE(PERIPHC_SDMMC2, CLOCK_TYPE_PC2CC3M_T), 182 TYPE(PERIPHC_16h, CLOCK_TYPE_NONE), 183 TYPE(PERIPHC_17h, CLOCK_TYPE_NONE), 184 185 /* 0x18 */ 186 TYPE(PERIPHC_18h, CLOCK_TYPE_NONE), 187 TYPE(PERIPHC_SDMMC4, CLOCK_TYPE_PC2CC3M_T), 188 TYPE(PERIPHC_VFIR, CLOCK_TYPE_PC2CC3M_T), 189 TYPE(PERIPHC_1Bh, CLOCK_TYPE_NONE), 190 TYPE(PERIPHC_1Ch, CLOCK_TYPE_NONE), 191 TYPE(PERIPHC_HSI, CLOCK_TYPE_PC2CC3M_T), 192 TYPE(PERIPHC_UART1, CLOCK_TYPE_PC2CC3M_T), 193 TYPE(PERIPHC_UART2, CLOCK_TYPE_PC2CC3M_T), 194 195 /* 0x20 */ 196 TYPE(PERIPHC_HOST1X, CLOCK_TYPE_MC2CC3P_A), 197 TYPE(PERIPHC_21h, CLOCK_TYPE_NONE), 198 TYPE(PERIPHC_22h, CLOCK_TYPE_NONE), 199 TYPE(PERIPHC_23h, CLOCK_TYPE_NONE), 200 TYPE(PERIPHC_24h, CLOCK_TYPE_NONE), 201 TYPE(PERIPHC_25h, CLOCK_TYPE_NONE), 202 TYPE(PERIPHC_I2C2, CLOCK_TYPE_PC2CC3M_T16), 203 TYPE(PERIPHC_EMC, CLOCK_TYPE_MCPTM2C2C3), 204 205 /* 0x28 */ 206 TYPE(PERIPHC_UART3, CLOCK_TYPE_PC2CC3M_T), 207 TYPE(PERIPHC_29h, CLOCK_TYPE_NONE), 208 TYPE(PERIPHC_VI_SENSOR, CLOCK_TYPE_MC2CC3P_A), 209 TYPE(PERIPHC_2bh, CLOCK_TYPE_NONE), 210 TYPE(PERIPHC_2ch, CLOCK_TYPE_NONE), 211 TYPE(PERIPHC_SBC4, CLOCK_TYPE_PC2CC3M_T), 212 TYPE(PERIPHC_I2C3, CLOCK_TYPE_PC2CC3M_T16), 213 TYPE(PERIPHC_SDMMC3, CLOCK_TYPE_PC2CC3M_T), 214 215 /* 0x30 */ 216 TYPE(PERIPHC_UART4, CLOCK_TYPE_PC2CC3M_T), 217 TYPE(PERIPHC_UART5, CLOCK_TYPE_PC2CC3M_T), 218 TYPE(PERIPHC_VDE, CLOCK_TYPE_PC2CC3M_T), 219 TYPE(PERIPHC_OWR, CLOCK_TYPE_PC2CC3M_T), 220 TYPE(PERIPHC_NOR, CLOCK_TYPE_PC2CC3M_T), 221 TYPE(PERIPHC_CSITE, CLOCK_TYPE_PC2CC3M_T), 222 TYPE(PERIPHC_I2S1, CLOCK_TYPE_AXPT), 223 TYPE(PERIPHC_DTV, CLOCK_TYPE_NONE), 224 225 /* 0x38 */ 226 TYPE(PERIPHC_38h, CLOCK_TYPE_NONE), 227 TYPE(PERIPHC_39h, CLOCK_TYPE_NONE), 228 TYPE(PERIPHC_3ah, CLOCK_TYPE_NONE), 229 TYPE(PERIPHC_3bh, CLOCK_TYPE_NONE), 230 TYPE(PERIPHC_MSENC, CLOCK_TYPE_MC2CC3P_A), 231 TYPE(PERIPHC_TSEC, CLOCK_TYPE_PC2CC3M_T), 232 TYPE(PERIPHC_3eh, CLOCK_TYPE_NONE), 233 TYPE(PERIPHC_OSC, CLOCK_TYPE_NONE), 234 235 /* 0x40 */ 236 TYPE(PERIPHC_40h, CLOCK_TYPE_NONE), /* start with 0x3b0 */ 237 TYPE(PERIPHC_MSELECT, CLOCK_TYPE_PC2CC3M_T), 238 TYPE(PERIPHC_TSENSOR, CLOCK_TYPE_PC2CC3T_S), 239 TYPE(PERIPHC_I2S4, CLOCK_TYPE_AXPT), 240 TYPE(PERIPHC_I2S5, CLOCK_TYPE_AXPT), 241 TYPE(PERIPHC_I2C4, CLOCK_TYPE_PC2CC3M_T16), 242 TYPE(PERIPHC_SBC5, CLOCK_TYPE_PC2CC3M_T), 243 TYPE(PERIPHC_SBC6, CLOCK_TYPE_PC2CC3M_T), 244 245 /* 0x48 */ 246 TYPE(PERIPHC_AUDIO, CLOCK_TYPE_AC2CC3P_TS2), 247 TYPE(PERIPHC_49h, CLOCK_TYPE_NONE), 248 TYPE(PERIPHC_4ah, CLOCK_TYPE_NONE), 249 TYPE(PERIPHC_4bh, CLOCK_TYPE_NONE), 250 TYPE(PERIPHC_4ch, CLOCK_TYPE_NONE), 251 TYPE(PERIPHC_HDA2CODEC2X, CLOCK_TYPE_PC2CC3M_T), 252 TYPE(PERIPHC_ACTMON, CLOCK_TYPE_PC2CC3S_T), 253 TYPE(PERIPHC_EXTPERIPH1, CLOCK_TYPE_ASPTE), 254 255 /* 0x50 */ 256 TYPE(PERIPHC_EXTPERIPH2, CLOCK_TYPE_ASPTE), 257 TYPE(PERIPHC_EXTPERIPH3, CLOCK_TYPE_ASPTE), 258 TYPE(PERIPHC_52h, CLOCK_TYPE_NONE), 259 TYPE(PERIPHC_I2CSLOW, CLOCK_TYPE_PC2CC3S_T), 260 TYPE(PERIPHC_SYS, CLOCK_TYPE_NONE), 261 TYPE(PERIPHC_55h, CLOCK_TYPE_NONE), 262 TYPE(PERIPHC_56h, CLOCK_TYPE_NONE), 263 TYPE(PERIPHC_57h, CLOCK_TYPE_NONE), 264 265 /* 0x58 */ 266 TYPE(PERIPHC_58h, CLOCK_TYPE_NONE), 267 TYPE(PERIPHC_59h, CLOCK_TYPE_NONE), 268 TYPE(PERIPHC_5ah, CLOCK_TYPE_NONE), 269 TYPE(PERIPHC_5bh, CLOCK_TYPE_NONE), 270 TYPE(PERIPHC_SATAOOB, CLOCK_TYPE_PCMT), 271 TYPE(PERIPHC_SATA, CLOCK_TYPE_PCMT), 272 TYPE(PERIPHC_HDA, CLOCK_TYPE_PC2CC3M_T), 273 TYPE(PERIPHC_5fh, CLOCK_TYPE_NONE), 274 275 /* 0x60 */ 276 TYPE(PERIPHC_XUSB_CORE_HOST, CLOCK_TYPE_NONE), 277 TYPE(PERIPHC_XUSB_FALCON, CLOCK_TYPE_NONE), 278 TYPE(PERIPHC_XUSB_FS, CLOCK_TYPE_NONE), 279 TYPE(PERIPHC_XUSB_CORE_DEV, CLOCK_TYPE_NONE), 280 TYPE(PERIPHC_XUSB_SS, CLOCK_TYPE_NONE), 281 TYPE(PERIPHC_CILAB, CLOCK_TYPE_NONE), 282 TYPE(PERIPHC_CILCD, CLOCK_TYPE_NONE), 283 TYPE(PERIPHC_CILE, CLOCK_TYPE_NONE), 284 285 /* 0x68 */ 286 TYPE(PERIPHC_DSIA_LP, CLOCK_TYPE_NONE), 287 TYPE(PERIPHC_DSIB_LP, CLOCK_TYPE_NONE), 288 TYPE(PERIPHC_ENTROPY, CLOCK_TYPE_NONE), 289 TYPE(PERIPHC_DVFS_REF, CLOCK_TYPE_NONE), 290 TYPE(PERIPHC_DVFS_SOC, CLOCK_TYPE_NONE), 291 TYPE(PERIPHC_TRACECLKIN, CLOCK_TYPE_NONE), 292 TYPE(PERIPHC_6eh, CLOCK_TYPE_NONE), 293 TYPE(PERIPHC_6fh, CLOCK_TYPE_NONE), 294 295 /* 0x70 */ 296 TYPE(PERIPHC_EMC_LATENCY, CLOCK_TYPE_NONE), 297 TYPE(PERIPHC_SOC_THERM, CLOCK_TYPE_NONE), 298 TYPE(PERIPHC_72h, CLOCK_TYPE_NONE), 299 TYPE(PERIPHC_73h, CLOCK_TYPE_NONE), 300 TYPE(PERIPHC_74h, CLOCK_TYPE_NONE), 301 TYPE(PERIPHC_75h, CLOCK_TYPE_NONE), 302 TYPE(PERIPHC_VI_SENSOR2, CLOCK_TYPE_NONE), 303 TYPE(PERIPHC_I2C6, CLOCK_TYPE_PC2CC3M_T16), 304 305 /* 0x78 */ 306 TYPE(PERIPHC_78h, CLOCK_TYPE_NONE), 307 TYPE(PERIPHC_EMC_DLL, CLOCK_TYPE_MCPTM2C2C3), 308 TYPE(PERIPHC_7ah, CLOCK_TYPE_NONE), 309 TYPE(PERIPHC_CLK72MHZ, CLOCK_TYPE_NONE), 310 TYPE(PERIPHC_7ch, CLOCK_TYPE_NONE), 311 TYPE(PERIPHC_7dh, CLOCK_TYPE_NONE), 312 TYPE(PERIPHC_VIC, CLOCK_TYPE_NONE), 313 TYPE(PERIPHC_7Fh, CLOCK_TYPE_NONE), 314 315 /* 0x80 */ 316 TYPE(PERIPHC_SDMMC_LEGACY_TM, CLOCK_TYPE_NONE), 317 TYPE(PERIPHC_NVDEC, CLOCK_TYPE_NONE), 318 TYPE(PERIPHC_NVJPG, CLOCK_TYPE_NONE), 319 TYPE(PERIPHC_NVENC, CLOCK_TYPE_NONE), 320 TYPE(PERIPHC_84h, CLOCK_TYPE_NONE), 321 TYPE(PERIPHC_85h, CLOCK_TYPE_NONE), 322 TYPE(PERIPHC_86h, CLOCK_TYPE_NONE), 323 TYPE(PERIPHC_87h, CLOCK_TYPE_NONE), 324 325 /* 0x88 */ 326 TYPE(PERIPHC_88h, CLOCK_TYPE_NONE), 327 TYPE(PERIPHC_89h, CLOCK_TYPE_NONE), 328 TYPE(PERIPHC_DMIC3, CLOCK_TYPE_NONE), 329 TYPE(PERIPHC_APE, CLOCK_TYPE_NONE), 330 TYPE(PERIPHC_QSPI, CLOCK_TYPE_PC01C00_C42C41TC40), 331 TYPE(PERIPHC_VI_I2C, CLOCK_TYPE_NONE), 332 TYPE(PERIPHC_USB2_HSIC_TRK, CLOCK_TYPE_NONE), 333 TYPE(PERIPHC_PEX_SATA_USB_RX_BYP, CLOCK_TYPE_NONE), 334 335 /* 0x90 */ 336 TYPE(PERIPHC_MAUD, CLOCK_TYPE_NONE), 337 TYPE(PERIPHC_TSECB, CLOCK_TYPE_NONE), 338 }; 339 340 /* 341 * This array translates a periph_id to a periphc_internal_id 342 * 343 * Not present/matched up: 344 * uint vi_sensor; _VI_SENSOR_0, 0x1A8 345 * SPDIF - which is both 0x08 and 0x0c 346 * 347 */ 348 #define NONE(name) (-1) 349 #define OFFSET(name, value) PERIPHC_ ## name 350 #define INTERNAL_ID(id) (id & 0x000000ff) 351 static s8 periph_id_to_internal_id[PERIPH_ID_COUNT] = { 352 /* Low word: 31:0 */ 353 NONE(CPU), 354 NONE(COP), 355 NONE(TRIGSYS), 356 NONE(ISPB), 357 NONE(RESERVED4), 358 NONE(TMR), 359 PERIPHC_UART1, 360 PERIPHC_UART2, /* and vfir 0x68 */ 361 362 /* 8 */ 363 NONE(GPIO), 364 PERIPHC_SDMMC2, 365 PERIPHC_SPDIF_IN, 366 PERIPHC_I2S2, 367 PERIPHC_I2C1, 368 NONE(RESERVED13), 369 PERIPHC_SDMMC1, 370 PERIPHC_SDMMC4, 371 372 /* 16 */ 373 NONE(TCW), 374 PERIPHC_PWM, 375 PERIPHC_I2S3, 376 NONE(RESERVED19), 377 PERIPHC_VI, 378 NONE(RESERVED21), 379 NONE(USBD), 380 NONE(ISP), 381 382 /* 24 */ 383 NONE(RESERVED24), 384 NONE(RESERVED25), 385 PERIPHC_DISP2, 386 PERIPHC_DISP1, 387 PERIPHC_HOST1X, 388 NONE(VCP), 389 PERIPHC_I2S1, 390 NONE(CACHE2), 391 392 /* Middle word: 63:32 */ 393 NONE(MEM), 394 NONE(AHBDMA), 395 NONE(APBDMA), 396 NONE(RESERVED35), 397 NONE(RESERVED36), 398 NONE(STAT_MON), 399 NONE(RESERVED38), 400 NONE(FUSE), 401 402 /* 40 */ 403 NONE(KFUSE), 404 PERIPHC_SBC1, /* SBCx = SPIx */ 405 PERIPHC_NOR, 406 NONE(RESERVED43), 407 PERIPHC_SBC2, 408 NONE(XIO), 409 PERIPHC_SBC3, 410 PERIPHC_I2C5, 411 412 /* 48 */ 413 NONE(DSI), 414 NONE(RESERVED49), 415 PERIPHC_HSI, 416 NONE(RESERVED51), 417 NONE(CSI), 418 NONE(RESERVED53), 419 PERIPHC_I2C2, 420 PERIPHC_UART3, 421 422 /* 56 */ 423 NONE(MIPI_CAL), 424 PERIPHC_EMC, 425 NONE(USB2), 426 NONE(USB3), 427 NONE(RESERVED60), 428 PERIPHC_VDE, 429 NONE(BSEA), 430 NONE(BSEV), 431 432 /* Upper word 95:64 */ 433 NONE(RESERVED64), 434 PERIPHC_UART4, 435 PERIPHC_UART5, 436 PERIPHC_I2C3, 437 PERIPHC_SBC4, 438 PERIPHC_SDMMC3, 439 NONE(PCIE), 440 PERIPHC_OWR, 441 442 /* 72 */ 443 NONE(AFI), 444 PERIPHC_CSITE, 445 NONE(PCIEXCLK), 446 NONE(AVPUCQ), 447 NONE(LA), 448 NONE(TRACECLKIN), 449 NONE(SOC_THERM), 450 NONE(DTV), 451 452 /* 80 */ 453 NONE(RESERVED80), 454 PERIPHC_I2CSLOW, 455 NONE(DSIB), 456 PERIPHC_TSEC, 457 NONE(RESERVED84), 458 NONE(RESERVED85), 459 NONE(RESERVED86), 460 NONE(EMUCIF), 461 462 /* 88 */ 463 NONE(RESERVED88), 464 NONE(XUSB_HOST), 465 NONE(RESERVED90), 466 PERIPHC_MSENC, 467 NONE(RESERVED92), 468 NONE(RESERVED93), 469 NONE(RESERVED94), 470 NONE(XUSB_DEV), 471 472 /* V word: 31:0 */ 473 NONE(CPUG), 474 NONE(CPULP), 475 NONE(V_RESERVED2), 476 PERIPHC_MSELECT, 477 NONE(V_RESERVED4), 478 PERIPHC_I2S4, 479 PERIPHC_I2S5, 480 PERIPHC_I2C4, 481 482 /* 104 */ 483 PERIPHC_SBC5, 484 PERIPHC_SBC6, 485 PERIPHC_AUDIO, 486 NONE(APBIF), 487 NONE(V_RESERVED12), 488 NONE(V_RESERVED13), 489 NONE(V_RESERVED14), 490 PERIPHC_HDA2CODEC2X, 491 492 /* 112 */ 493 NONE(ATOMICS), 494 NONE(V_RESERVED17), 495 NONE(V_RESERVED18), 496 NONE(V_RESERVED19), 497 NONE(V_RESERVED20), 498 NONE(V_RESERVED21), 499 NONE(V_RESERVED22), 500 PERIPHC_ACTMON, 501 502 /* 120 */ 503 NONE(EXTPERIPH1), 504 NONE(EXTPERIPH2), 505 NONE(EXTPERIPH3), 506 NONE(OOB), 507 PERIPHC_SATA, 508 PERIPHC_HDA, 509 NONE(TZRAM), 510 NONE(SE), 511 512 /* W word: 31:0 */ 513 NONE(HDA2HDMICODEC), 514 NONE(SATACOLD), 515 NONE(W_RESERVED2), 516 NONE(W_RESERVED3), 517 NONE(W_RESERVED4), 518 NONE(W_RESERVED5), 519 NONE(W_RESERVED6), 520 NONE(W_RESERVED7), 521 522 /* 136 */ 523 NONE(CEC), 524 NONE(W_RESERVED9), 525 NONE(W_RESERVED10), 526 NONE(W_RESERVED11), 527 NONE(W_RESERVED12), 528 NONE(W_RESERVED13), 529 NONE(XUSB_PADCTL), 530 NONE(W_RESERVED15), 531 532 /* 144 */ 533 NONE(W_RESERVED16), 534 NONE(W_RESERVED17), 535 NONE(W_RESERVED18), 536 NONE(W_RESERVED19), 537 NONE(W_RESERVED20), 538 NONE(ENTROPY), 539 NONE(DDS), 540 NONE(W_RESERVED23), 541 542 /* 152 */ 543 NONE(W_RESERVED24), 544 NONE(W_RESERVED25), 545 NONE(W_RESERVED26), 546 NONE(DVFS), 547 NONE(XUSB_SS), 548 NONE(W_RESERVED29), 549 NONE(W_RESERVED30), 550 NONE(W_RESERVED31), 551 552 /* X word: 31:0 */ 553 NONE(SPARE), 554 NONE(X_RESERVED1), 555 NONE(X_RESERVED2), 556 NONE(X_RESERVED3), 557 NONE(CAM_MCLK), 558 NONE(CAM_MCLK2), 559 PERIPHC_I2C6, 560 NONE(X_RESERVED7), 561 562 /* 168 */ 563 NONE(X_RESERVED8), 564 NONE(X_RESERVED9), 565 NONE(X_RESERVED10), 566 NONE(VIM2_CLK), 567 NONE(X_RESERVED12), 568 NONE(X_RESERVED13), 569 NONE(EMC_DLL), 570 NONE(X_RESERVED15), 571 572 /* 176 */ 573 NONE(X_RESERVED16), 574 NONE(CLK72MHZ), 575 NONE(VIC), 576 NONE(X_RESERVED19), 577 NONE(X_RESERVED20), 578 NONE(DPAUX), 579 NONE(SOR0), 580 NONE(X_RESERVED23), 581 582 /* 184 */ 583 NONE(GPU), 584 NONE(X_RESERVED25), 585 NONE(X_RESERVED26), 586 NONE(X_RESERVED27), 587 NONE(X_RESERVED28), 588 NONE(X_RESERVED29), 589 NONE(X_RESERVED30), 590 NONE(X_RESERVED31), 591 592 /* Y: 192 (192 - 223) */ 593 NONE(Y_RESERVED0), 594 PERIPHC_SDMMC_LEGACY_TM, 595 PERIPHC_NVDEC, 596 PERIPHC_NVJPG, 597 NONE(Y_RESERVED4), 598 PERIPHC_DMIC3, /* 197 */ 599 PERIPHC_APE, /* 198 */ 600 NONE(Y_RESERVED7), 601 602 /* 200 */ 603 NONE(Y_RESERVED8), 604 NONE(Y_RESERVED9), 605 NONE(Y_RESERVED10), 606 NONE(Y_RESERVED11), 607 NONE(Y_RESERVED12), 608 NONE(Y_RESERVED13), 609 NONE(Y_RESERVED14), 610 NONE(Y_RESERVED15), 611 612 /* 208 */ 613 PERIPHC_VI_I2C, /* 208 */ 614 NONE(Y_RESERVED17), 615 NONE(Y_RESERVED18), 616 PERIPHC_QSPI, /* 211 */ 617 NONE(Y_RESERVED20), 618 NONE(Y_RESERVED21), 619 NONE(Y_RESERVED22), 620 NONE(Y_RESERVED23), 621 622 /* 216 */ 623 NONE(Y_RESERVED24), 624 NONE(Y_RESERVED25), 625 NONE(Y_RESERVED26), 626 PERIPHC_NVENC, /* 219 */ 627 NONE(Y_RESERVED28), 628 NONE(Y_RESERVED29), 629 NONE(Y_RESERVED30), 630 NONE(Y_RESERVED31), 631 }; 632 633 /* 634 * PLL divider shift/mask tables for all PLL IDs. 635 */ 636 struct clk_pll_info tegra_pll_info_table[CLOCK_ID_PLL_COUNT] = { 637 /* 638 * NOTE: If kcp_mask/kvco_mask == 0, they're not used in that PLL (PLLC, etc.) 639 * If lock_ena or lock_det are >31, they're not used in that PLL (PLLC, etc.) 640 */ 641 { .m_shift = 0, .m_mask = 0xFF, .n_shift = 10, .n_mask = 0xFF, .p_shift = 20, .p_mask = 0x1F, 642 .lock_ena = 32, .lock_det = 27, .kcp_shift = 0, .kcp_mask = 0, .kvco_shift = 0, .kvco_mask = 0 }, /* PLLC */ 643 { .m_shift = 0, .m_mask = 0xFF, .n_shift = 8, .n_mask = 0xFF, .p_shift = 20, .p_mask = 0x1F, 644 .lock_ena = 4, .lock_det = 27, .kcp_shift = 1, .kcp_mask = 3, .kvco_shift = 0, .kvco_mask = 1 }, /* PLLM */ 645 { .m_shift = 0, .m_mask = 0xFF, .n_shift = 10, .n_mask = 0xFF, .p_shift = 20, .p_mask = 0x1F, 646 .lock_ena = 18, .lock_det = 27, .kcp_shift = 0, .kcp_mask = 3, .kvco_shift = 2, .kvco_mask = 1 }, /* PLLP */ 647 { .m_shift = 0, .m_mask = 0xFF, .n_shift = 8, .n_mask = 0xFF, .p_shift = 20, .p_mask = 0x1F, 648 .lock_ena = 28, .lock_det = 27, .kcp_shift = 25, .kcp_mask = 3, .kvco_shift = 24, .kvco_mask = 1 }, /* PLLA */ 649 { .m_shift = 0, .m_mask = 0xFF, .n_shift = 8, .n_mask = 0xFF, .p_shift = 16, .p_mask = 0x1F, 650 .lock_ena = 29, .lock_det = 27, .kcp_shift = 25, .kcp_mask = 3, .kvco_shift = 24, .kvco_mask = 1 }, /* PLLU */ 651 { .m_shift = 0, .m_mask = 0xFF, .n_shift = 11, .n_mask = 0xFF, .p_shift = 20, .p_mask = 0x07, 652 .lock_ena = 18, .lock_det = 27, .kcp_shift = 23, .kcp_mask = 3, .kvco_shift = 22, .kvco_mask = 1 }, /* PLLD */ 653 { .m_shift = 0, .m_mask = 0xFF, .n_shift = 8, .n_mask = 0xFF, .p_shift = 20, .p_mask = 0x1F, 654 .lock_ena = 18, .lock_det = 27, .kcp_shift = 1, .kcp_mask = 3, .kvco_shift = 0, .kvco_mask = 1 }, /* PLLX */ 655 { .m_shift = 0, .m_mask = 0xFF, .n_shift = 8, .n_mask = 0xFF, .p_shift = 0, .p_mask = 0, 656 .lock_ena = 9, .lock_det = 11, .kcp_shift = 6, .kcp_mask = 3, .kvco_shift = 0, .kvco_mask = 1 }, /* PLLE */ 657 { .m_shift = 0, .m_mask = 0, .n_shift = 0, .n_mask = 0, .p_shift = 0, .p_mask = 0, 658 .lock_ena = 0, .lock_det = 0, .kcp_shift = 0, .kcp_mask = 0, .kvco_shift = 0, .kvco_mask = 0 }, /* PLLS (gone)*/ 659 }; 660 661 /* 662 * Get the oscillator frequency, from the corresponding hardware configuration 663 * field. Note that Tegra30+ support 3 new higher freqs, but we map back 664 * to the old T20 freqs. Support for the higher oscillators is TBD. 665 */ 666 enum clock_osc_freq clock_get_osc_freq(void) 667 { 668 struct clk_rst_ctlr *clkrst = 669 (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE; 670 u32 reg; 671 672 reg = readl(&clkrst->crc_osc_ctrl); 673 reg = (reg & OSC_FREQ_MASK) >> OSC_FREQ_SHIFT; 674 /* 675 * 0 = 13MHz, 1 = 16.8MHz, 4 = 19.2MHz, 5 = 38.4MHz, 676 * 8 = 12MHz, 9 = 48MHz, 12 = 26MHz 677 */ 678 if (reg == 5) { 679 debug("OSC_FREQ is 38.4MHz (%d) ...\n", reg); 680 /* Map it to the 5th CLOCK_OSC_ enum, i.e. 4 */ 681 return 4; 682 } 683 684 /* 685 * Map to most common (T20) freqs (except 38.4, handled above): 686 * 13/16.8 = 0, 19.2 = 1, 12/48 = 2, 26 = 3 687 */ 688 return reg >> 2; 689 } 690 691 /* Returns a pointer to the clock source register for a peripheral */ 692 u32 *get_periph_source_reg(enum periph_id periph_id) 693 { 694 struct clk_rst_ctlr *clkrst = 695 (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE; 696 enum periphc_internal_id internal_id; 697 698 /* Coresight is a special case */ 699 if (periph_id == PERIPH_ID_CSI) 700 return &clkrst->crc_clk_src[PERIPH_ID_CSI+1]; 701 702 assert(periph_id >= PERIPH_ID_FIRST && periph_id < PERIPH_ID_COUNT); 703 internal_id = INTERNAL_ID(periph_id_to_internal_id[periph_id]); 704 assert(internal_id != -1); 705 706 if (internal_id < PERIPHC_VW_FIRST) 707 /* L, H, U */ 708 return &clkrst->crc_clk_src[internal_id]; 709 710 if (internal_id < PERIPHC_X_FIRST) { 711 /* VW */ 712 internal_id -= PERIPHC_VW_FIRST; 713 return &clkrst->crc_clk_src_vw[internal_id]; 714 } 715 716 if (internal_id < PERIPHC_Y_FIRST) { 717 /* X */ 718 internal_id -= PERIPHC_X_FIRST; 719 return &clkrst->crc_clk_src_x[internal_id]; 720 } 721 722 /* Y */ 723 internal_id -= PERIPHC_Y_FIRST; 724 return &clkrst->crc_clk_src_y[internal_id]; 725 } 726 727 /** 728 * Given a peripheral ID and the required source clock, this returns which 729 * value should be programmed into the source mux for that peripheral. 730 * 731 * There is special code here to handle the one source type with 5 sources. 732 * 733 * @param periph_id peripheral to start 734 * @param source PLL id of required parent clock 735 * @param mux_bits Set to number of bits in mux register: 2 or 4 736 * @param divider_bits Set to number of divider bits (8 or 16) 737 * @return mux value (0-4, or -1 if not found) 738 */ 739 int get_periph_clock_source(enum periph_id periph_id, 740 enum clock_id parent, int *mux_bits, int *divider_bits) 741 { 742 enum clock_type_id type; 743 enum periphc_internal_id internal_id; 744 int mux; 745 746 assert(clock_periph_id_isvalid(periph_id)); 747 748 internal_id = INTERNAL_ID(periph_id_to_internal_id[periph_id]); 749 assert(periphc_internal_id_isvalid(internal_id)); 750 751 type = clock_periph_type[internal_id]; 752 assert(clock_type_id_isvalid(type)); 753 754 *mux_bits = clock_source[type][CLOCK_MAX_MUX]; 755 756 if (type == CLOCK_TYPE_PC2CC3M_T16) 757 *divider_bits = 16; 758 else 759 *divider_bits = 8; 760 761 for (mux = 0; mux < CLOCK_MAX_MUX; mux++) 762 if (clock_source[type][mux] == parent) 763 return mux; 764 765 /* if we get here, either us or the caller has made a mistake */ 766 printf("Caller requested bad clock: periph=%d, parent=%d\n", periph_id, 767 parent); 768 return -1; 769 } 770 771 void clock_set_enable(enum periph_id periph_id, int enable) 772 { 773 struct clk_rst_ctlr *clkrst = 774 (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE; 775 u32 *clk; 776 u32 reg; 777 778 /* Enable/disable the clock to this peripheral */ 779 assert(clock_periph_id_isvalid(periph_id)); 780 if ((int)periph_id < (int)PERIPH_ID_VW_FIRST) 781 clk = &clkrst->crc_clk_out_enb[PERIPH_REG(periph_id)]; 782 else if ((int)periph_id < (int)PERIPH_ID_X_FIRST) 783 clk = &clkrst->crc_clk_out_enb_vw[PERIPH_REG(periph_id)]; 784 else if ((int)periph_id < (int)PERIPH_ID_Y_FIRST) 785 clk = &clkrst->crc_clk_out_enb_x; 786 else 787 clk = &clkrst->crc_clk_out_enb_y; 788 789 reg = readl(clk); 790 if (enable) 791 reg |= PERIPH_MASK(periph_id); 792 else 793 reg &= ~PERIPH_MASK(periph_id); 794 writel(reg, clk); 795 } 796 797 void reset_set_enable(enum periph_id periph_id, int enable) 798 { 799 struct clk_rst_ctlr *clkrst = 800 (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE; 801 u32 *reset; 802 u32 reg; 803 804 /* Enable/disable reset to the peripheral */ 805 assert(clock_periph_id_isvalid(periph_id)); 806 if (periph_id < PERIPH_ID_VW_FIRST) 807 reset = &clkrst->crc_rst_dev[PERIPH_REG(periph_id)]; 808 else if ((int)periph_id < (int)PERIPH_ID_X_FIRST) 809 reset = &clkrst->crc_rst_dev_vw[PERIPH_REG(periph_id)]; 810 else if ((int)periph_id < (int)PERIPH_ID_Y_FIRST) 811 reset = &clkrst->crc_rst_devices_x; 812 else 813 reset = &clkrst->crc_rst_devices_y; 814 815 reg = readl(reset); 816 if (enable) 817 reg |= PERIPH_MASK(periph_id); 818 else 819 reg &= ~PERIPH_MASK(periph_id); 820 writel(reg, reset); 821 } 822 823 #ifdef CONFIG_OF_CONTROL 824 /* 825 * Convert a device tree clock ID to our peripheral ID. They are mostly 826 * the same but we are very cautious so we check that a valid clock ID is 827 * provided. 828 * 829 * @param clk_id Clock ID according to tegra210 device tree binding 830 * @return peripheral ID, or PERIPH_ID_NONE if the clock ID is invalid 831 */ 832 enum periph_id clk_id_to_periph_id(int clk_id) 833 { 834 if (clk_id > PERIPH_ID_COUNT) 835 return PERIPH_ID_NONE; 836 837 switch (clk_id) { 838 case PERIPH_ID_RESERVED4: 839 case PERIPH_ID_RESERVED25: 840 case PERIPH_ID_RESERVED35: 841 case PERIPH_ID_RESERVED36: 842 case PERIPH_ID_RESERVED38: 843 case PERIPH_ID_RESERVED43: 844 case PERIPH_ID_RESERVED49: 845 case PERIPH_ID_RESERVED53: 846 case PERIPH_ID_RESERVED64: 847 case PERIPH_ID_RESERVED84: 848 case PERIPH_ID_RESERVED85: 849 case PERIPH_ID_RESERVED86: 850 case PERIPH_ID_RESERVED88: 851 case PERIPH_ID_RESERVED90: 852 case PERIPH_ID_RESERVED92: 853 case PERIPH_ID_RESERVED93: 854 case PERIPH_ID_RESERVED94: 855 case PERIPH_ID_V_RESERVED2: 856 case PERIPH_ID_V_RESERVED4: 857 case PERIPH_ID_V_RESERVED17: 858 case PERIPH_ID_V_RESERVED18: 859 case PERIPH_ID_V_RESERVED19: 860 case PERIPH_ID_V_RESERVED20: 861 case PERIPH_ID_V_RESERVED21: 862 case PERIPH_ID_V_RESERVED22: 863 case PERIPH_ID_W_RESERVED2: 864 case PERIPH_ID_W_RESERVED3: 865 case PERIPH_ID_W_RESERVED4: 866 case PERIPH_ID_W_RESERVED5: 867 case PERIPH_ID_W_RESERVED6: 868 case PERIPH_ID_W_RESERVED7: 869 case PERIPH_ID_W_RESERVED9: 870 case PERIPH_ID_W_RESERVED10: 871 case PERIPH_ID_W_RESERVED11: 872 case PERIPH_ID_W_RESERVED12: 873 case PERIPH_ID_W_RESERVED13: 874 case PERIPH_ID_W_RESERVED15: 875 case PERIPH_ID_W_RESERVED16: 876 case PERIPH_ID_W_RESERVED17: 877 case PERIPH_ID_W_RESERVED18: 878 case PERIPH_ID_W_RESERVED19: 879 case PERIPH_ID_W_RESERVED20: 880 case PERIPH_ID_W_RESERVED23: 881 case PERIPH_ID_W_RESERVED29: 882 case PERIPH_ID_W_RESERVED30: 883 case PERIPH_ID_W_RESERVED31: 884 return PERIPH_ID_NONE; 885 default: 886 return clk_id; 887 } 888 } 889 #endif /* CONFIG_OF_CONTROL */ 890 891 /* 892 * T210 redefines PLLP_OUT2 as PLLP_VCO/DIVP, so do different OUT1-4 setup here. 893 * PLLP_BASE/MISC/etc. is already set up for 408MHz in the BootROM. 894 */ 895 void tegra210_setup_pllp(void) 896 { 897 struct clk_rst_ctlr *clkrst = (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE; 898 u32 reg; 899 900 /* Set PLLP_OUT1, 3 & 4 freqs to 9.6, 102 & 204MHz */ 901 902 /* OUT1 */ 903 /* Assert RSTN before enable */ 904 reg = PLLP_OUT1_RSTN_EN; 905 writel(reg, &clkrst->crc_pll[CLOCK_ID_PERIPH].pll_out[0]); 906 /* Set divisor and reenable */ 907 reg = (IN_408_OUT_9_6_DIVISOR << PLLP_OUT1_RATIO) 908 | PLLP_OUT1_OVR | PLLP_OUT1_CLKEN | PLLP_OUT1_RSTN_DIS; 909 writel(reg, &clkrst->crc_pll[CLOCK_ID_PERIPH].pll_out[0]); 910 911 /* OUT3, 4 */ 912 /* Assert RSTN before enable */ 913 reg = PLLP_OUT4_RSTN_EN | PLLP_OUT3_RSTN_EN; 914 writel(reg, &clkrst->crc_pll[CLOCK_ID_PERIPH].pll_out[1]); 915 /* Set divisor and reenable */ 916 reg = (IN_408_OUT_204_DIVISOR << PLLP_OUT4_RATIO) 917 | PLLP_OUT4_OVR | PLLP_OUT4_CLKEN | PLLP_OUT4_RSTN_DIS 918 | (IN_408_OUT_102_DIVISOR << PLLP_OUT3_RATIO) 919 | PLLP_OUT3_OVR | PLLP_OUT3_CLKEN | PLLP_OUT3_RSTN_DIS; 920 writel(reg, &clkrst->crc_pll[CLOCK_ID_PERIPH].pll_out[1]); 921 922 /* 923 * NOTE: If you want to change PLLP_OUT2 away from 204MHz, 924 * you can change PLLP_BASE DIVP here. Currently defaults 925 * to 1, which is 2^1, or 2, so PLLP_OUT2 is 204MHz. 926 * See Table 13 in section 5.1.4 in T210 TRM for more info. 927 */ 928 } 929 930 void clock_early_init(void) 931 { 932 struct clk_rst_ctlr *clkrst = 933 (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE; 934 struct clk_pll_info *pllinfo = &tegra_pll_info_table[CLOCK_ID_DISPLAY]; 935 u32 data; 936 937 tegra210_setup_pllp(); 938 939 /* 940 * PLLC output frequency set to 600Mhz 941 * PLLD output frequency set to 925Mhz 942 */ 943 switch (clock_get_osc_freq()) { 944 case CLOCK_OSC_FREQ_12_0: /* OSC is 12Mhz */ 945 clock_set_rate(CLOCK_ID_CGENERAL, 600, 12, 0, 8); 946 clock_set_rate(CLOCK_ID_DISPLAY, 925, 12, 0, 12); 947 break; 948 949 case CLOCK_OSC_FREQ_26_0: /* OSC is 26Mhz */ 950 clock_set_rate(CLOCK_ID_CGENERAL, 600, 26, 0, 8); 951 clock_set_rate(CLOCK_ID_DISPLAY, 925, 26, 0, 12); 952 break; 953 954 case CLOCK_OSC_FREQ_13_0: /* OSC is 13Mhz */ 955 clock_set_rate(CLOCK_ID_CGENERAL, 600, 13, 0, 8); 956 clock_set_rate(CLOCK_ID_DISPLAY, 925, 13, 0, 12); 957 break; 958 case CLOCK_OSC_FREQ_19_2: 959 clock_set_rate(CLOCK_ID_CGENERAL, 125, 4, 0, 0); 960 clock_set_rate(CLOCK_ID_DISPLAY, 96, 2, 0, 12); 961 break; 962 case CLOCK_OSC_FREQ_38_4: 963 clock_set_rate(CLOCK_ID_CGENERAL, 125, 8, 0, 0); 964 clock_set_rate(CLOCK_ID_DISPLAY, 96, 4, 0, 0); 965 break; 966 default: 967 /* 968 * These are not supported. It is too early to print a 969 * message and the UART likely won't work anyway due to the 970 * oscillator being wrong. 971 */ 972 break; 973 } 974 975 /* PLLC_MISC1: Turn IDDQ off. NOTE: T210 PLLC_MISC_1 maps to pll_misc */ 976 clrbits_le32(&clkrst->crc_pll[CLOCK_ID_CGENERAL].pll_misc, 977 (1 << PLLC_IDDQ)); 978 udelay(2); 979 980 /* 981 * PLLC_MISC: Take PLLC out of reset. NOTE: T210 PLLC_MISC maps 982 * to pll_out[1] 983 */ 984 clrbits_le32(&clkrst->crc_pll[CLOCK_ID_CGENERAL].pll_out[1], 985 (1 << PLLC_RESET)); 986 udelay(2); 987 988 /* PLLD_MISC: Set CLKENABLE and LOCK_DETECT bits */ 989 data = (1 << PLLD_ENABLE_CLK) | (1 << pllinfo->lock_ena); 990 writel(data, &clkrst->crc_pll[CLOCK_ID_DISPLAY].pll_misc); 991 udelay(2); 992 } 993 994 void arch_timer_init(void) 995 { 996 struct sysctr_ctlr *sysctr = (struct sysctr_ctlr *)NV_PA_TSC_BASE; 997 u32 freq, val; 998 999 freq = clock_get_rate(CLOCK_ID_OSC); 1000 debug("%s: osc freq is %dHz [0x%08X]\n", __func__, freq, freq); 1001 1002 /* ARM CNTFRQ */ 1003 #ifndef CONFIG_ARM64 1004 asm("mcr p15, 0, %0, c14, c0, 0\n" : : "r" (freq)); 1005 #endif 1006 1007 /* Only Tegra114+ has the System Counter regs */ 1008 debug("%s: setting CNTFID0 to 0x%08X\n", __func__, freq); 1009 writel(freq, &sysctr->cntfid0); 1010 1011 val = readl(&sysctr->cntcr); 1012 val |= TSC_CNTCR_ENABLE | TSC_CNTCR_HDBG; 1013 writel(val, &sysctr->cntcr); 1014 debug("%s: TSC CNTCR = 0x%08X\n", __func__, val); 1015 } 1016 1017 #define PLLE_SS_CNTL 0x68 1018 #define PLLE_SS_CNTL_SSCINCINTR(x) (((x) & 0x3f) << 24) 1019 #define PLLE_SS_CNTL_SSCINC(x) (((x) & 0xff) << 16) 1020 #define PLLE_SS_CNTL_SSCINVERT (1 << 15) 1021 #define PLLE_SS_CNTL_SSCCENTER (1 << 14) 1022 #define PLLE_SS_CNTL_SSCBYP (1 << 12) 1023 #define PLLE_SS_CNTL_INTERP_RESET (1 << 11) 1024 #define PLLE_SS_CNTL_BYPASS_SS (1 << 10) 1025 #define PLLE_SS_CNTL_SSCMAX(x) (((x) & 0x1ff) << 0) 1026 1027 #define PLLE_BASE 0x0e8 1028 #define PLLE_BASE_ENABLE (1 << 30) 1029 #define PLLE_BASE_LOCK_OVERRIDE (1 << 29) 1030 #define PLLE_BASE_PLDIV_CML(x) (((x) & 0xf) << 24) 1031 #define PLLE_BASE_NDIV(x) (((x) & 0xff) << 8) 1032 #define PLLE_BASE_MDIV(x) (((x) & 0xff) << 0) 1033 1034 #define PLLE_MISC 0x0ec 1035 #define PLLE_MISC_IDDQ_SWCTL (1 << 14) 1036 #define PLLE_MISC_IDDQ_OVERRIDE (1 << 13) 1037 #define PLLE_MISC_LOCK_ENABLE (1 << 9) 1038 #define PLLE_MISC_PTS (1 << 8) 1039 #define PLLE_MISC_VREG_BG_CTRL(x) (((x) & 0x3) << 4) 1040 #define PLLE_MISC_VREG_CTRL(x) (((x) & 0x3) << 2) 1041 1042 #define PLLE_AUX 0x48c 1043 #define PLLE_AUX_SEQ_ENABLE (1 << 24) 1044 #define PLLE_AUX_ENABLE_SWCTL (1 << 4) 1045 1046 int tegra_plle_enable(void) 1047 { 1048 unsigned int m = 1, n = 200, cpcon = 13; 1049 u32 value; 1050 1051 value = readl(NV_PA_CLK_RST_BASE + PLLE_BASE); 1052 value &= ~PLLE_BASE_LOCK_OVERRIDE; 1053 writel(value, NV_PA_CLK_RST_BASE + PLLE_BASE); 1054 1055 value = readl(NV_PA_CLK_RST_BASE + PLLE_AUX); 1056 value |= PLLE_AUX_ENABLE_SWCTL; 1057 value &= ~PLLE_AUX_SEQ_ENABLE; 1058 writel(value, NV_PA_CLK_RST_BASE + PLLE_AUX); 1059 1060 udelay(1); 1061 1062 value = readl(NV_PA_CLK_RST_BASE + PLLE_MISC); 1063 value |= PLLE_MISC_IDDQ_SWCTL; 1064 value &= ~PLLE_MISC_IDDQ_OVERRIDE; 1065 value |= PLLE_MISC_LOCK_ENABLE; 1066 value |= PLLE_MISC_PTS; 1067 value |= PLLE_MISC_VREG_BG_CTRL(3); 1068 value |= PLLE_MISC_VREG_CTRL(2); 1069 writel(value, NV_PA_CLK_RST_BASE + PLLE_MISC); 1070 1071 udelay(5); 1072 1073 value = readl(NV_PA_CLK_RST_BASE + PLLE_SS_CNTL); 1074 value |= PLLE_SS_CNTL_SSCBYP | PLLE_SS_CNTL_INTERP_RESET | 1075 PLLE_SS_CNTL_BYPASS_SS; 1076 writel(value, NV_PA_CLK_RST_BASE + PLLE_SS_CNTL); 1077 1078 value = readl(NV_PA_CLK_RST_BASE + PLLE_BASE); 1079 value &= ~PLLE_BASE_PLDIV_CML(0xf); 1080 value &= ~PLLE_BASE_NDIV(0xff); 1081 value &= ~PLLE_BASE_MDIV(0xff); 1082 value |= PLLE_BASE_PLDIV_CML(cpcon); 1083 value |= PLLE_BASE_NDIV(n); 1084 value |= PLLE_BASE_MDIV(m); 1085 writel(value, NV_PA_CLK_RST_BASE + PLLE_BASE); 1086 1087 udelay(1); 1088 1089 value = readl(NV_PA_CLK_RST_BASE + PLLE_BASE); 1090 value |= PLLE_BASE_ENABLE; 1091 writel(value, NV_PA_CLK_RST_BASE + PLLE_BASE); 1092 1093 /* wait for lock */ 1094 udelay(300); 1095 1096 value = readl(NV_PA_CLK_RST_BASE + PLLE_SS_CNTL); 1097 value &= ~PLLE_SS_CNTL_SSCINVERT; 1098 value &= ~PLLE_SS_CNTL_SSCCENTER; 1099 1100 value &= ~PLLE_SS_CNTL_SSCINCINTR(0x3f); 1101 value &= ~PLLE_SS_CNTL_SSCINC(0xff); 1102 value &= ~PLLE_SS_CNTL_SSCMAX(0x1ff); 1103 1104 value |= PLLE_SS_CNTL_SSCINCINTR(0x20); 1105 value |= PLLE_SS_CNTL_SSCINC(0x01); 1106 value |= PLLE_SS_CNTL_SSCMAX(0x25); 1107 1108 writel(value, NV_PA_CLK_RST_BASE + PLLE_SS_CNTL); 1109 1110 value = readl(NV_PA_CLK_RST_BASE + PLLE_SS_CNTL); 1111 value &= ~PLLE_SS_CNTL_SSCBYP; 1112 value &= ~PLLE_SS_CNTL_BYPASS_SS; 1113 writel(value, NV_PA_CLK_RST_BASE + PLLE_SS_CNTL); 1114 1115 udelay(1); 1116 1117 value = readl(NV_PA_CLK_RST_BASE + PLLE_SS_CNTL); 1118 value &= ~PLLE_SS_CNTL_INTERP_RESET; 1119 writel(value, NV_PA_CLK_RST_BASE + PLLE_SS_CNTL); 1120 1121 udelay(1); 1122 1123 return 0; 1124 } 1125