109f455dcSMasahiro Yamada /* 209f455dcSMasahiro Yamada * (C) Copyright 2010 309f455dcSMasahiro Yamada * NVIDIA Corporation <www.nvidia.com> 409f455dcSMasahiro Yamada * 509f455dcSMasahiro Yamada * SPDX-License-Identifier: GPL-2.0+ 609f455dcSMasahiro Yamada */ 709f455dcSMasahiro Yamada 809f455dcSMasahiro Yamada #include <common.h> 909f455dcSMasahiro Yamada #include <asm/io.h> 1009f455dcSMasahiro Yamada #include <asm/arch/clock.h> 1109f455dcSMasahiro Yamada #include <asm/arch/tegra.h> 1209f455dcSMasahiro Yamada #include <asm/arch/display.h> 13*2eb70de6SSimon Glass #include <asm/arch-tegra/dc.h> 1409f455dcSMasahiro Yamada #include <asm/arch-tegra/clk_rst.h> 1509f455dcSMasahiro Yamada #include <asm/arch-tegra/timer.h> 1609f455dcSMasahiro Yamada 1709f455dcSMasahiro Yamada static struct fdt_disp_config config; 1809f455dcSMasahiro Yamada 1909f455dcSMasahiro Yamada static void update_window(struct dc_ctlr *dc, struct disp_ctl_win *win) 2009f455dcSMasahiro Yamada { 2109f455dcSMasahiro Yamada unsigned h_dda, v_dda; 2209f455dcSMasahiro Yamada unsigned long val; 2309f455dcSMasahiro Yamada 2409f455dcSMasahiro Yamada val = readl(&dc->cmd.disp_win_header); 2509f455dcSMasahiro Yamada val |= WINDOW_A_SELECT; 2609f455dcSMasahiro Yamada writel(val, &dc->cmd.disp_win_header); 2709f455dcSMasahiro Yamada 2809f455dcSMasahiro Yamada writel(win->fmt, &dc->win.color_depth); 2909f455dcSMasahiro Yamada 3009f455dcSMasahiro Yamada clrsetbits_le32(&dc->win.byte_swap, BYTE_SWAP_MASK, 3109f455dcSMasahiro Yamada BYTE_SWAP_NOSWAP << BYTE_SWAP_SHIFT); 3209f455dcSMasahiro Yamada 3309f455dcSMasahiro Yamada val = win->out_x << H_POSITION_SHIFT; 3409f455dcSMasahiro Yamada val |= win->out_y << V_POSITION_SHIFT; 3509f455dcSMasahiro Yamada writel(val, &dc->win.pos); 3609f455dcSMasahiro Yamada 3709f455dcSMasahiro Yamada val = win->out_w << H_SIZE_SHIFT; 3809f455dcSMasahiro Yamada val |= win->out_h << V_SIZE_SHIFT; 3909f455dcSMasahiro Yamada writel(val, &dc->win.size); 4009f455dcSMasahiro Yamada 4109f455dcSMasahiro Yamada val = (win->w * win->bpp / 8) << H_PRESCALED_SIZE_SHIFT; 4209f455dcSMasahiro Yamada val |= win->h << V_PRESCALED_SIZE_SHIFT; 4309f455dcSMasahiro Yamada writel(val, &dc->win.prescaled_size); 4409f455dcSMasahiro Yamada 4509f455dcSMasahiro Yamada writel(0, &dc->win.h_initial_dda); 4609f455dcSMasahiro Yamada writel(0, &dc->win.v_initial_dda); 4709f455dcSMasahiro Yamada 4809f455dcSMasahiro Yamada h_dda = (win->w * 0x1000) / max(win->out_w - 1, 1U); 4909f455dcSMasahiro Yamada v_dda = (win->h * 0x1000) / max(win->out_h - 1, 1U); 5009f455dcSMasahiro Yamada 5109f455dcSMasahiro Yamada val = h_dda << H_DDA_INC_SHIFT; 5209f455dcSMasahiro Yamada val |= v_dda << V_DDA_INC_SHIFT; 5309f455dcSMasahiro Yamada writel(val, &dc->win.dda_increment); 5409f455dcSMasahiro Yamada 5509f455dcSMasahiro Yamada writel(win->stride, &dc->win.line_stride); 5609f455dcSMasahiro Yamada writel(0, &dc->win.buf_stride); 5709f455dcSMasahiro Yamada 5809f455dcSMasahiro Yamada val = WIN_ENABLE; 5909f455dcSMasahiro Yamada if (win->bpp < 24) 6009f455dcSMasahiro Yamada val |= COLOR_EXPAND; 6109f455dcSMasahiro Yamada writel(val, &dc->win.win_opt); 6209f455dcSMasahiro Yamada 6309f455dcSMasahiro Yamada writel((unsigned long)win->phys_addr, &dc->winbuf.start_addr); 6409f455dcSMasahiro Yamada writel(win->x, &dc->winbuf.addr_h_offset); 6509f455dcSMasahiro Yamada writel(win->y, &dc->winbuf.addr_v_offset); 6609f455dcSMasahiro Yamada 6709f455dcSMasahiro Yamada writel(0xff00, &dc->win.blend_nokey); 6809f455dcSMasahiro Yamada writel(0xff00, &dc->win.blend_1win); 6909f455dcSMasahiro Yamada 7009f455dcSMasahiro Yamada val = GENERAL_ACT_REQ | WIN_A_ACT_REQ; 7109f455dcSMasahiro Yamada val |= GENERAL_UPDATE | WIN_A_UPDATE; 7209f455dcSMasahiro Yamada writel(val, &dc->cmd.state_ctrl); 7309f455dcSMasahiro Yamada } 7409f455dcSMasahiro Yamada 7509f455dcSMasahiro Yamada static void write_pair(struct fdt_disp_config *config, int item, u32 *reg) 7609f455dcSMasahiro Yamada { 7709f455dcSMasahiro Yamada writel(config->horiz_timing[item] | 7809f455dcSMasahiro Yamada (config->vert_timing[item] << 16), reg); 7909f455dcSMasahiro Yamada } 8009f455dcSMasahiro Yamada 8109f455dcSMasahiro Yamada static int update_display_mode(struct dc_disp_reg *disp, 8209f455dcSMasahiro Yamada struct fdt_disp_config *config) 8309f455dcSMasahiro Yamada { 8409f455dcSMasahiro Yamada unsigned long val; 8509f455dcSMasahiro Yamada unsigned long rate; 8609f455dcSMasahiro Yamada unsigned long div; 8709f455dcSMasahiro Yamada 8809f455dcSMasahiro Yamada writel(0x0, &disp->disp_timing_opt); 8909f455dcSMasahiro Yamada write_pair(config, FDT_LCD_TIMING_REF_TO_SYNC, &disp->ref_to_sync); 9009f455dcSMasahiro Yamada write_pair(config, FDT_LCD_TIMING_SYNC_WIDTH, &disp->sync_width); 9109f455dcSMasahiro Yamada write_pair(config, FDT_LCD_TIMING_BACK_PORCH, &disp->back_porch); 9209f455dcSMasahiro Yamada write_pair(config, FDT_LCD_TIMING_FRONT_PORCH, &disp->front_porch); 9309f455dcSMasahiro Yamada 9409f455dcSMasahiro Yamada writel(config->width | (config->height << 16), &disp->disp_active); 9509f455dcSMasahiro Yamada 9609f455dcSMasahiro Yamada val = DE_SELECT_ACTIVE << DE_SELECT_SHIFT; 9709f455dcSMasahiro Yamada val |= DE_CONTROL_NORMAL << DE_CONTROL_SHIFT; 9809f455dcSMasahiro Yamada writel(val, &disp->data_enable_opt); 9909f455dcSMasahiro Yamada 10009f455dcSMasahiro Yamada val = DATA_FORMAT_DF1P1C << DATA_FORMAT_SHIFT; 10109f455dcSMasahiro Yamada val |= DATA_ALIGNMENT_MSB << DATA_ALIGNMENT_SHIFT; 10209f455dcSMasahiro Yamada val |= DATA_ORDER_RED_BLUE << DATA_ORDER_SHIFT; 10309f455dcSMasahiro Yamada writel(val, &disp->disp_interface_ctrl); 10409f455dcSMasahiro Yamada 10509f455dcSMasahiro Yamada /* 10609f455dcSMasahiro Yamada * The pixel clock divider is in 7.1 format (where the bottom bit 10709f455dcSMasahiro Yamada * represents 0.5). Here we calculate the divider needed to get from 10809f455dcSMasahiro Yamada * the display clock (typically 600MHz) to the pixel clock. We round 10909f455dcSMasahiro Yamada * up or down as requried. 11009f455dcSMasahiro Yamada */ 11109f455dcSMasahiro Yamada rate = clock_get_periph_rate(PERIPH_ID_DISP1, CLOCK_ID_CGENERAL); 11209f455dcSMasahiro Yamada div = ((rate * 2 + config->pixel_clock / 2) / config->pixel_clock) - 2; 11309f455dcSMasahiro Yamada debug("Display clock %lu, divider %lu\n", rate, div); 11409f455dcSMasahiro Yamada 11509f455dcSMasahiro Yamada writel(0x00010001, &disp->shift_clk_opt); 11609f455dcSMasahiro Yamada 11709f455dcSMasahiro Yamada val = PIXEL_CLK_DIVIDER_PCD1 << PIXEL_CLK_DIVIDER_SHIFT; 11809f455dcSMasahiro Yamada val |= div << SHIFT_CLK_DIVIDER_SHIFT; 11909f455dcSMasahiro Yamada writel(val, &disp->disp_clk_ctrl); 12009f455dcSMasahiro Yamada 12109f455dcSMasahiro Yamada return 0; 12209f455dcSMasahiro Yamada } 12309f455dcSMasahiro Yamada 12409f455dcSMasahiro Yamada /* Start up the display and turn on power to PWMs */ 12509f455dcSMasahiro Yamada static void basic_init(struct dc_cmd_reg *cmd) 12609f455dcSMasahiro Yamada { 12709f455dcSMasahiro Yamada u32 val; 12809f455dcSMasahiro Yamada 12909f455dcSMasahiro Yamada writel(0x00000100, &cmd->gen_incr_syncpt_ctrl); 13009f455dcSMasahiro Yamada writel(0x0000011a, &cmd->cont_syncpt_vsync); 13109f455dcSMasahiro Yamada writel(0x00000000, &cmd->int_type); 13209f455dcSMasahiro Yamada writel(0x00000000, &cmd->int_polarity); 13309f455dcSMasahiro Yamada writel(0x00000000, &cmd->int_mask); 13409f455dcSMasahiro Yamada writel(0x00000000, &cmd->int_enb); 13509f455dcSMasahiro Yamada 13609f455dcSMasahiro Yamada val = PW0_ENABLE | PW1_ENABLE | PW2_ENABLE; 13709f455dcSMasahiro Yamada val |= PW3_ENABLE | PW4_ENABLE | PM0_ENABLE; 13809f455dcSMasahiro Yamada val |= PM1_ENABLE; 13909f455dcSMasahiro Yamada writel(val, &cmd->disp_pow_ctrl); 14009f455dcSMasahiro Yamada 14109f455dcSMasahiro Yamada val = readl(&cmd->disp_cmd); 14209f455dcSMasahiro Yamada val |= CTRL_MODE_C_DISPLAY << CTRL_MODE_SHIFT; 14309f455dcSMasahiro Yamada writel(val, &cmd->disp_cmd); 14409f455dcSMasahiro Yamada } 14509f455dcSMasahiro Yamada 14609f455dcSMasahiro Yamada static void basic_init_timer(struct dc_disp_reg *disp) 14709f455dcSMasahiro Yamada { 14809f455dcSMasahiro Yamada writel(0x00000020, &disp->mem_high_pri); 14909f455dcSMasahiro Yamada writel(0x00000001, &disp->mem_high_pri_timer); 15009f455dcSMasahiro Yamada } 15109f455dcSMasahiro Yamada 15209f455dcSMasahiro Yamada static const u32 rgb_enb_tab[PIN_REG_COUNT] = { 15309f455dcSMasahiro Yamada 0x00000000, 15409f455dcSMasahiro Yamada 0x00000000, 15509f455dcSMasahiro Yamada 0x00000000, 15609f455dcSMasahiro Yamada 0x00000000, 15709f455dcSMasahiro Yamada }; 15809f455dcSMasahiro Yamada 15909f455dcSMasahiro Yamada static const u32 rgb_polarity_tab[PIN_REG_COUNT] = { 16009f455dcSMasahiro Yamada 0x00000000, 16109f455dcSMasahiro Yamada 0x01000000, 16209f455dcSMasahiro Yamada 0x00000000, 16309f455dcSMasahiro Yamada 0x00000000, 16409f455dcSMasahiro Yamada }; 16509f455dcSMasahiro Yamada 16609f455dcSMasahiro Yamada static const u32 rgb_data_tab[PIN_REG_COUNT] = { 16709f455dcSMasahiro Yamada 0x00000000, 16809f455dcSMasahiro Yamada 0x00000000, 16909f455dcSMasahiro Yamada 0x00000000, 17009f455dcSMasahiro Yamada 0x00000000, 17109f455dcSMasahiro Yamada }; 17209f455dcSMasahiro Yamada 17309f455dcSMasahiro Yamada static const u32 rgb_sel_tab[PIN_OUTPUT_SEL_COUNT] = { 17409f455dcSMasahiro Yamada 0x00000000, 17509f455dcSMasahiro Yamada 0x00000000, 17609f455dcSMasahiro Yamada 0x00000000, 17709f455dcSMasahiro Yamada 0x00000000, 17809f455dcSMasahiro Yamada 0x00210222, 17909f455dcSMasahiro Yamada 0x00002200, 18009f455dcSMasahiro Yamada 0x00020000, 18109f455dcSMasahiro Yamada }; 18209f455dcSMasahiro Yamada 18309f455dcSMasahiro Yamada static void rgb_enable(struct dc_com_reg *com) 18409f455dcSMasahiro Yamada { 18509f455dcSMasahiro Yamada int i; 18609f455dcSMasahiro Yamada 18709f455dcSMasahiro Yamada for (i = 0; i < PIN_REG_COUNT; i++) { 18809f455dcSMasahiro Yamada writel(rgb_enb_tab[i], &com->pin_output_enb[i]); 18909f455dcSMasahiro Yamada writel(rgb_polarity_tab[i], &com->pin_output_polarity[i]); 19009f455dcSMasahiro Yamada writel(rgb_data_tab[i], &com->pin_output_data[i]); 19109f455dcSMasahiro Yamada } 19209f455dcSMasahiro Yamada 19309f455dcSMasahiro Yamada for (i = 0; i < PIN_OUTPUT_SEL_COUNT; i++) 19409f455dcSMasahiro Yamada writel(rgb_sel_tab[i], &com->pin_output_sel[i]); 19509f455dcSMasahiro Yamada } 19609f455dcSMasahiro Yamada 19709f455dcSMasahiro Yamada static int setup_window(struct disp_ctl_win *win, 19809f455dcSMasahiro Yamada struct fdt_disp_config *config) 19909f455dcSMasahiro Yamada { 20009f455dcSMasahiro Yamada win->x = 0; 20109f455dcSMasahiro Yamada win->y = 0; 20209f455dcSMasahiro Yamada win->w = config->width; 20309f455dcSMasahiro Yamada win->h = config->height; 20409f455dcSMasahiro Yamada win->out_x = 0; 20509f455dcSMasahiro Yamada win->out_y = 0; 20609f455dcSMasahiro Yamada win->out_w = config->width; 20709f455dcSMasahiro Yamada win->out_h = config->height; 20809f455dcSMasahiro Yamada win->phys_addr = config->frame_buffer; 20909f455dcSMasahiro Yamada win->stride = config->width * (1 << config->log2_bpp) / 8; 21009f455dcSMasahiro Yamada debug("%s: depth = %d\n", __func__, config->log2_bpp); 21109f455dcSMasahiro Yamada switch (config->log2_bpp) { 21209f455dcSMasahiro Yamada case 5: 21309f455dcSMasahiro Yamada case 24: 21409f455dcSMasahiro Yamada win->fmt = COLOR_DEPTH_R8G8B8A8; 21509f455dcSMasahiro Yamada win->bpp = 32; 21609f455dcSMasahiro Yamada break; 21709f455dcSMasahiro Yamada case 4: 21809f455dcSMasahiro Yamada win->fmt = COLOR_DEPTH_B5G6R5; 21909f455dcSMasahiro Yamada win->bpp = 16; 22009f455dcSMasahiro Yamada break; 22109f455dcSMasahiro Yamada 22209f455dcSMasahiro Yamada default: 22309f455dcSMasahiro Yamada debug("Unsupported LCD bit depth"); 22409f455dcSMasahiro Yamada return -1; 22509f455dcSMasahiro Yamada } 22609f455dcSMasahiro Yamada 22709f455dcSMasahiro Yamada return 0; 22809f455dcSMasahiro Yamada } 22909f455dcSMasahiro Yamada 23009f455dcSMasahiro Yamada struct fdt_disp_config *tegra_display_get_config(void) 23109f455dcSMasahiro Yamada { 23209f455dcSMasahiro Yamada return config.valid ? &config : NULL; 23309f455dcSMasahiro Yamada } 23409f455dcSMasahiro Yamada 23509f455dcSMasahiro Yamada static void debug_timing(const char *name, unsigned int timing[]) 23609f455dcSMasahiro Yamada { 23709f455dcSMasahiro Yamada #ifdef DEBUG 23809f455dcSMasahiro Yamada int i; 23909f455dcSMasahiro Yamada 24009f455dcSMasahiro Yamada debug("%s timing: ", name); 24109f455dcSMasahiro Yamada for (i = 0; i < FDT_LCD_TIMING_COUNT; i++) 24209f455dcSMasahiro Yamada debug("%d ", timing[i]); 24309f455dcSMasahiro Yamada debug("\n"); 24409f455dcSMasahiro Yamada #endif 24509f455dcSMasahiro Yamada } 24609f455dcSMasahiro Yamada 24709f455dcSMasahiro Yamada /** 24809f455dcSMasahiro Yamada * Decode panel information from the fdt, according to a standard binding 24909f455dcSMasahiro Yamada * 25009f455dcSMasahiro Yamada * @param blob fdt blob 25109f455dcSMasahiro Yamada * @param node offset of fdt node to read from 25209f455dcSMasahiro Yamada * @param config structure to store fdt config into 25309f455dcSMasahiro Yamada * @return 0 if ok, -ve on error 25409f455dcSMasahiro Yamada */ 25509f455dcSMasahiro Yamada static int tegra_decode_panel(const void *blob, int node, 25609f455dcSMasahiro Yamada struct fdt_disp_config *config) 25709f455dcSMasahiro Yamada { 25809f455dcSMasahiro Yamada int front, back, ref; 25909f455dcSMasahiro Yamada 26009f455dcSMasahiro Yamada config->width = fdtdec_get_int(blob, node, "xres", -1); 26109f455dcSMasahiro Yamada config->height = fdtdec_get_int(blob, node, "yres", -1); 26209f455dcSMasahiro Yamada config->pixel_clock = fdtdec_get_int(blob, node, "clock", 0); 26309f455dcSMasahiro Yamada if (!config->pixel_clock || config->width == -1 || 26409f455dcSMasahiro Yamada config->height == -1) { 26509f455dcSMasahiro Yamada debug("%s: Pixel parameters missing\n", __func__); 26609f455dcSMasahiro Yamada return -FDT_ERR_NOTFOUND; 26709f455dcSMasahiro Yamada } 26809f455dcSMasahiro Yamada 26909f455dcSMasahiro Yamada back = fdtdec_get_int(blob, node, "left-margin", -1); 27009f455dcSMasahiro Yamada front = fdtdec_get_int(blob, node, "right-margin", -1); 27109f455dcSMasahiro Yamada ref = fdtdec_get_int(blob, node, "hsync-len", -1); 27209f455dcSMasahiro Yamada if ((back | front | ref) == -1) { 27309f455dcSMasahiro Yamada debug("%s: Horizontal parameters missing\n", __func__); 27409f455dcSMasahiro Yamada return -FDT_ERR_NOTFOUND; 27509f455dcSMasahiro Yamada } 27609f455dcSMasahiro Yamada 27709f455dcSMasahiro Yamada /* Use a ref-to-sync of 1 always, and take this from the front porch */ 27809f455dcSMasahiro Yamada config->horiz_timing[FDT_LCD_TIMING_REF_TO_SYNC] = 1; 27909f455dcSMasahiro Yamada config->horiz_timing[FDT_LCD_TIMING_SYNC_WIDTH] = ref; 28009f455dcSMasahiro Yamada config->horiz_timing[FDT_LCD_TIMING_BACK_PORCH] = back; 28109f455dcSMasahiro Yamada config->horiz_timing[FDT_LCD_TIMING_FRONT_PORCH] = front - 28209f455dcSMasahiro Yamada config->horiz_timing[FDT_LCD_TIMING_REF_TO_SYNC]; 28309f455dcSMasahiro Yamada debug_timing("horiz", config->horiz_timing); 28409f455dcSMasahiro Yamada 28509f455dcSMasahiro Yamada back = fdtdec_get_int(blob, node, "upper-margin", -1); 28609f455dcSMasahiro Yamada front = fdtdec_get_int(blob, node, "lower-margin", -1); 28709f455dcSMasahiro Yamada ref = fdtdec_get_int(blob, node, "vsync-len", -1); 28809f455dcSMasahiro Yamada if ((back | front | ref) == -1) { 28909f455dcSMasahiro Yamada debug("%s: Vertical parameters missing\n", __func__); 29009f455dcSMasahiro Yamada return -FDT_ERR_NOTFOUND; 29109f455dcSMasahiro Yamada } 29209f455dcSMasahiro Yamada 29309f455dcSMasahiro Yamada config->vert_timing[FDT_LCD_TIMING_REF_TO_SYNC] = 1; 29409f455dcSMasahiro Yamada config->vert_timing[FDT_LCD_TIMING_SYNC_WIDTH] = ref; 29509f455dcSMasahiro Yamada config->vert_timing[FDT_LCD_TIMING_BACK_PORCH] = back; 29609f455dcSMasahiro Yamada config->vert_timing[FDT_LCD_TIMING_FRONT_PORCH] = front - 29709f455dcSMasahiro Yamada config->vert_timing[FDT_LCD_TIMING_REF_TO_SYNC]; 29809f455dcSMasahiro Yamada debug_timing("vert", config->vert_timing); 29909f455dcSMasahiro Yamada 30009f455dcSMasahiro Yamada return 0; 30109f455dcSMasahiro Yamada } 30209f455dcSMasahiro Yamada 30309f455dcSMasahiro Yamada /** 30409f455dcSMasahiro Yamada * Decode the display controller information from the fdt. 30509f455dcSMasahiro Yamada * 30609f455dcSMasahiro Yamada * @param blob fdt blob 30709f455dcSMasahiro Yamada * @param config structure to store fdt config into 30809f455dcSMasahiro Yamada * @return 0 if ok, -ve on error 30909f455dcSMasahiro Yamada */ 31009f455dcSMasahiro Yamada static int tegra_display_decode_config(const void *blob, 31109f455dcSMasahiro Yamada struct fdt_disp_config *config) 31209f455dcSMasahiro Yamada { 31309f455dcSMasahiro Yamada int node, rgb; 31409f455dcSMasahiro Yamada int bpp, bit; 31509f455dcSMasahiro Yamada 31609f455dcSMasahiro Yamada /* TODO: Support multiple controllers */ 31709f455dcSMasahiro Yamada node = fdtdec_next_compatible(blob, 0, COMPAT_NVIDIA_TEGRA20_DC); 31809f455dcSMasahiro Yamada if (node < 0) { 31909f455dcSMasahiro Yamada debug("%s: Cannot find display controller node in fdt\n", 32009f455dcSMasahiro Yamada __func__); 32109f455dcSMasahiro Yamada return node; 32209f455dcSMasahiro Yamada } 32309f455dcSMasahiro Yamada config->disp = (struct disp_ctlr *)fdtdec_get_addr(blob, node, "reg"); 32409f455dcSMasahiro Yamada if (!config->disp) { 32509f455dcSMasahiro Yamada debug("%s: No display controller address\n", __func__); 32609f455dcSMasahiro Yamada return -1; 32709f455dcSMasahiro Yamada } 32809f455dcSMasahiro Yamada 32909f455dcSMasahiro Yamada rgb = fdt_subnode_offset(blob, node, "rgb"); 33009f455dcSMasahiro Yamada 33109f455dcSMasahiro Yamada config->panel_node = fdtdec_lookup_phandle(blob, rgb, "nvidia,panel"); 33209f455dcSMasahiro Yamada if (config->panel_node < 0) { 33309f455dcSMasahiro Yamada debug("%s: Cannot find panel information\n", __func__); 33409f455dcSMasahiro Yamada return -1; 33509f455dcSMasahiro Yamada } 33609f455dcSMasahiro Yamada 33709f455dcSMasahiro Yamada if (tegra_decode_panel(blob, config->panel_node, config)) { 33809f455dcSMasahiro Yamada debug("%s: Failed to decode panel information\n", __func__); 33909f455dcSMasahiro Yamada return -1; 34009f455dcSMasahiro Yamada } 34109f455dcSMasahiro Yamada 34209f455dcSMasahiro Yamada bpp = fdtdec_get_int(blob, config->panel_node, "nvidia,bits-per-pixel", 34309f455dcSMasahiro Yamada -1); 34409f455dcSMasahiro Yamada bit = ffs(bpp) - 1; 34509f455dcSMasahiro Yamada if (bpp == (1 << bit)) 34609f455dcSMasahiro Yamada config->log2_bpp = bit; 34709f455dcSMasahiro Yamada else 34809f455dcSMasahiro Yamada config->log2_bpp = bpp; 34909f455dcSMasahiro Yamada if (bpp == -1) { 35009f455dcSMasahiro Yamada debug("%s: Pixel bpp parameters missing\n", __func__); 35109f455dcSMasahiro Yamada return -FDT_ERR_NOTFOUND; 35209f455dcSMasahiro Yamada } 35309f455dcSMasahiro Yamada config->bpp = bpp; 35409f455dcSMasahiro Yamada 35509f455dcSMasahiro Yamada config->valid = 1; /* we have a valid configuration */ 35609f455dcSMasahiro Yamada 35709f455dcSMasahiro Yamada return 0; 35809f455dcSMasahiro Yamada } 35909f455dcSMasahiro Yamada 36009f455dcSMasahiro Yamada int tegra_display_probe(const void *blob, void *default_lcd_base) 36109f455dcSMasahiro Yamada { 36209f455dcSMasahiro Yamada struct disp_ctl_win window; 36309f455dcSMasahiro Yamada struct dc_ctlr *dc; 36409f455dcSMasahiro Yamada 36509f455dcSMasahiro Yamada if (tegra_display_decode_config(blob, &config)) 36609f455dcSMasahiro Yamada return -1; 36709f455dcSMasahiro Yamada 36809f455dcSMasahiro Yamada config.frame_buffer = (u32)default_lcd_base; 36909f455dcSMasahiro Yamada 37009f455dcSMasahiro Yamada dc = (struct dc_ctlr *)config.disp; 37109f455dcSMasahiro Yamada 37209f455dcSMasahiro Yamada /* 37309f455dcSMasahiro Yamada * A header file for clock constants was NAKed upstream. 37409f455dcSMasahiro Yamada * TODO: Put this into the FDT and fdt_lcd struct when we have clock 37509f455dcSMasahiro Yamada * support there 37609f455dcSMasahiro Yamada */ 37709f455dcSMasahiro Yamada clock_start_periph_pll(PERIPH_ID_HOST1X, CLOCK_ID_PERIPH, 37809f455dcSMasahiro Yamada 144 * 1000000); 37909f455dcSMasahiro Yamada clock_start_periph_pll(PERIPH_ID_DISP1, CLOCK_ID_CGENERAL, 38009f455dcSMasahiro Yamada 600 * 1000000); 38109f455dcSMasahiro Yamada basic_init(&dc->cmd); 38209f455dcSMasahiro Yamada basic_init_timer(&dc->disp); 38309f455dcSMasahiro Yamada rgb_enable(&dc->com); 38409f455dcSMasahiro Yamada 38509f455dcSMasahiro Yamada if (config.pixel_clock) 38609f455dcSMasahiro Yamada update_display_mode(&dc->disp, &config); 38709f455dcSMasahiro Yamada 38809f455dcSMasahiro Yamada if (setup_window(&window, &config)) 38909f455dcSMasahiro Yamada return -1; 39009f455dcSMasahiro Yamada 39109f455dcSMasahiro Yamada update_window(dc, &window); 39209f455dcSMasahiro Yamada 39309f455dcSMasahiro Yamada return 0; 39409f455dcSMasahiro Yamada } 395