1 /* 2 * Copyright (c) 2010-2012, NVIDIA CORPORATION. All rights reserved. 3 * 4 * SPDX-License-Identifier: GPL-2.0 5 */ 6 7 #include <common.h> 8 #include <asm/io.h> 9 #include <asm/arch/tegra.h> 10 #include <asm/arch-tegra/pmc.h> 11 #include "../cpu.h" 12 13 static void enable_cpu_power_rail(void) 14 { 15 struct pmc_ctlr *pmc = (struct pmc_ctlr *)NV_PA_PMC_BASE; 16 u32 reg; 17 18 reg = readl(&pmc->pmc_cntrl); 19 reg |= CPUPWRREQ_OE; 20 writel(reg, &pmc->pmc_cntrl); 21 22 /* 23 * The TI PMU65861C needs a 3.75ms delay between enabling 24 * the power rail and enabling the CPU clock. This delay 25 * between SM1EN and SM1 is for switching time + the ramp 26 * up of the voltage to the CPU (VDD_CPU from PMU). 27 */ 28 udelay(3750); 29 } 30 31 void start_cpu(u32 reset_vector) 32 { 33 /* Enable VDD_CPU */ 34 enable_cpu_power_rail(); 35 36 /* Hold the CPUs in reset */ 37 reset_A9_cpu(1); 38 39 /* Disable the CPU clock */ 40 enable_cpu_clock(0); 41 42 /* Enable CoreSight */ 43 clock_enable_coresight(1); 44 45 /* 46 * Set the entry point for CPU execution from reset, 47 * if it's a non-zero value. 48 */ 49 if (reset_vector) 50 writel(reset_vector, EXCEP_VECTOR_CPU_RESET_VECTOR); 51 52 /* Enable the CPU clock */ 53 enable_cpu_clock(1); 54 55 /* If the CPU doesn't already have power, power it up */ 56 powerup_cpu(); 57 58 /* Take the CPU out of reset */ 59 reset_A9_cpu(0); 60 } 61