1 /* 2 * Copyright (c) 2010-2012, NVIDIA CORPORATION. All rights reserved. 3 * 4 * This program is free software; you can redistribute it and/or modify it 5 * under the terms and conditions of the GNU General Public License, 6 * version 2, as published by the Free Software Foundation. 7 * 8 * This program is distributed in the hope it will be useful, but WITHOUT 9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 11 * more details. 12 * 13 * You should have received a copy of the GNU General Public License 14 * along with this program. If not, see <http://www.gnu.org/licenses/>. 15 */ 16 17 #include <common.h> 18 #include <asm/io.h> 19 #include <asm/arch/tegra.h> 20 #include <asm/arch-tegra/pmc.h> 21 #include "../cpu.h" 22 23 static void enable_cpu_power_rail(void) 24 { 25 struct pmc_ctlr *pmc = (struct pmc_ctlr *)NV_PA_PMC_BASE; 26 u32 reg; 27 28 reg = readl(&pmc->pmc_cntrl); 29 reg |= CPUPWRREQ_OE; 30 writel(reg, &pmc->pmc_cntrl); 31 32 /* 33 * The TI PMU65861C needs a 3.75ms delay between enabling 34 * the power rail and enabling the CPU clock. This delay 35 * between SM1EN and SM1 is for switching time + the ramp 36 * up of the voltage to the CPU (VDD_CPU from PMU). 37 */ 38 udelay(3750); 39 } 40 41 void start_cpu(u32 reset_vector) 42 { 43 /* Enable VDD_CPU */ 44 enable_cpu_power_rail(); 45 46 /* Hold the CPUs in reset */ 47 reset_A9_cpu(1); 48 49 /* Disable the CPU clock */ 50 enable_cpu_clock(0); 51 52 /* Enable CoreSight */ 53 clock_enable_coresight(1); 54 55 /* 56 * Set the entry point for CPU execution from reset, 57 * if it's a non-zero value. 58 */ 59 if (reset_vector) 60 writel(reset_vector, EXCEP_VECTOR_CPU_RESET_VECTOR); 61 62 /* Enable the CPU clock */ 63 enable_cpu_clock(1); 64 65 /* If the CPU doesn't already have power, power it up */ 66 powerup_cpu(); 67 68 /* Take the CPU out of reset */ 69 reset_A9_cpu(0); 70 } 71