1 /* 2 * Copyright (c) 2011 The Chromium OS Authors. 3 * (C) Copyright 2010-2015 4 * NVIDIA Corporation <www.nvidia.com> 5 * 6 * SPDX-License-Identifier: GPL-2.0+ 7 */ 8 9 /* Tegra20 Clock control functions */ 10 11 #include <common.h> 12 #include <errno.h> 13 #include <asm/io.h> 14 #include <asm/arch/clock.h> 15 #include <asm/arch/tegra.h> 16 #include <asm/arch-tegra/clk_rst.h> 17 #include <asm/arch-tegra/timer.h> 18 #include <div64.h> 19 #include <fdtdec.h> 20 21 /* 22 * Clock types that we can use as a source. The Tegra20 has muxes for the 23 * peripheral clocks, and in most cases there are four options for the clock 24 * source. This gives us a clock 'type' and exploits what commonality exists 25 * in the device. 26 * 27 * Letters are obvious, except for T which means CLK_M, and S which means the 28 * clock derived from 32KHz. Beware that CLK_M (also called OSC in the 29 * datasheet) and PLL_M are different things. The former is the basic 30 * clock supplied to the SOC from an external oscillator. The latter is the 31 * memory clock PLL. 32 * 33 * See definitions in clock_id in the header file. 34 */ 35 enum clock_type_id { 36 CLOCK_TYPE_AXPT, /* PLL_A, PLL_X, PLL_P, CLK_M */ 37 CLOCK_TYPE_MCPA, /* and so on */ 38 CLOCK_TYPE_MCPT, 39 CLOCK_TYPE_PCM, 40 CLOCK_TYPE_PCMT, 41 CLOCK_TYPE_PCMT16, /* CLOCK_TYPE_PCMT with 16-bit divider */ 42 CLOCK_TYPE_PCXTS, 43 CLOCK_TYPE_PDCT, 44 45 CLOCK_TYPE_COUNT, 46 CLOCK_TYPE_NONE = -1, /* invalid clock type */ 47 }; 48 49 enum { 50 CLOCK_MAX_MUX = 4 /* number of source options for each clock */ 51 }; 52 53 /* 54 * Clock source mux for each clock type. This just converts our enum into 55 * a list of mux sources for use by the code. Note that CLOCK_TYPE_PCXTS 56 * is special as it has 5 sources. Since it also has a different number of 57 * bits in its register for the source, we just handle it with a special 58 * case in the code. 59 */ 60 #define CLK(x) CLOCK_ID_ ## x 61 static enum clock_id clock_source[CLOCK_TYPE_COUNT][CLOCK_MAX_MUX] = { 62 { CLK(AUDIO), CLK(XCPU), CLK(PERIPH), CLK(OSC) }, 63 { CLK(MEMORY), CLK(CGENERAL), CLK(PERIPH), CLK(AUDIO) }, 64 { CLK(MEMORY), CLK(CGENERAL), CLK(PERIPH), CLK(OSC) }, 65 { CLK(PERIPH), CLK(CGENERAL), CLK(MEMORY), CLK(NONE) }, 66 { CLK(PERIPH), CLK(CGENERAL), CLK(MEMORY), CLK(OSC) }, 67 { CLK(PERIPH), CLK(CGENERAL), CLK(MEMORY), CLK(OSC) }, 68 { CLK(PERIPH), CLK(CGENERAL), CLK(XCPU), CLK(OSC) }, 69 { CLK(PERIPH), CLK(DISPLAY), CLK(CGENERAL), CLK(OSC) }, 70 }; 71 72 /* 73 * Clock peripheral IDs which sadly don't match up with PERIPH_ID. This is 74 * not in the header file since it is for purely internal use - we want 75 * callers to use the PERIPH_ID for all access to peripheral clocks to avoid 76 * confusion bewteen PERIPH_ID_... and PERIPHC_... 77 * 78 * We don't call this CLOCK_PERIPH_ID or PERIPH_CLOCK_ID as it would just be 79 * confusing. 80 * 81 * Note to SOC vendors: perhaps define a unified numbering for peripherals and 82 * use it for reset, clock enable, clock source/divider and even pinmuxing 83 * if you can. 84 */ 85 enum periphc_internal_id { 86 /* 0x00 */ 87 PERIPHC_I2S1, 88 PERIPHC_I2S2, 89 PERIPHC_SPDIF_OUT, 90 PERIPHC_SPDIF_IN, 91 PERIPHC_PWM, 92 PERIPHC_SPI1, 93 PERIPHC_SPI2, 94 PERIPHC_SPI3, 95 96 /* 0x08 */ 97 PERIPHC_XIO, 98 PERIPHC_I2C1, 99 PERIPHC_DVC_I2C, 100 PERIPHC_TWC, 101 PERIPHC_0c, 102 PERIPHC_10, /* PERIPHC_SPI1, what is this really? */ 103 PERIPHC_DISP1, 104 PERIPHC_DISP2, 105 106 /* 0x10 */ 107 PERIPHC_CVE, 108 PERIPHC_IDE0, 109 PERIPHC_VI, 110 PERIPHC_1c, 111 PERIPHC_SDMMC1, 112 PERIPHC_SDMMC2, 113 PERIPHC_G3D, 114 PERIPHC_G2D, 115 116 /* 0x18 */ 117 PERIPHC_NDFLASH, 118 PERIPHC_SDMMC4, 119 PERIPHC_VFIR, 120 PERIPHC_EPP, 121 PERIPHC_MPE, 122 PERIPHC_MIPI, 123 PERIPHC_UART1, 124 PERIPHC_UART2, 125 126 /* 0x20 */ 127 PERIPHC_HOST1X, 128 PERIPHC_21, 129 PERIPHC_TVO, 130 PERIPHC_HDMI, 131 PERIPHC_24, 132 PERIPHC_TVDAC, 133 PERIPHC_I2C2, 134 PERIPHC_EMC, 135 136 /* 0x28 */ 137 PERIPHC_UART3, 138 PERIPHC_29, 139 PERIPHC_VI_SENSOR, 140 PERIPHC_2b, 141 PERIPHC_2c, 142 PERIPHC_SPI4, 143 PERIPHC_I2C3, 144 PERIPHC_SDMMC3, 145 146 /* 0x30 */ 147 PERIPHC_UART4, 148 PERIPHC_UART5, 149 PERIPHC_VDE, 150 PERIPHC_OWR, 151 PERIPHC_NOR, 152 PERIPHC_CSITE, 153 154 PERIPHC_COUNT, 155 156 PERIPHC_NONE = -1, 157 }; 158 159 /* 160 * Clock type for each peripheral clock source. We put the name in each 161 * record just so it is easy to match things up 162 */ 163 #define TYPE(name, type) type 164 static enum clock_type_id clock_periph_type[PERIPHC_COUNT] = { 165 /* 0x00 */ 166 TYPE(PERIPHC_I2S1, CLOCK_TYPE_AXPT), 167 TYPE(PERIPHC_I2S2, CLOCK_TYPE_AXPT), 168 TYPE(PERIPHC_SPDIF_OUT, CLOCK_TYPE_AXPT), 169 TYPE(PERIPHC_SPDIF_IN, CLOCK_TYPE_PCM), 170 TYPE(PERIPHC_PWM, CLOCK_TYPE_PCXTS), 171 TYPE(PERIPHC_SPI1, CLOCK_TYPE_PCMT), 172 TYPE(PERIPHC_SPI22, CLOCK_TYPE_PCMT), 173 TYPE(PERIPHC_SPI3, CLOCK_TYPE_PCMT), 174 175 /* 0x08 */ 176 TYPE(PERIPHC_XIO, CLOCK_TYPE_PCMT), 177 TYPE(PERIPHC_I2C1, CLOCK_TYPE_PCMT16), 178 TYPE(PERIPHC_DVC_I2C, CLOCK_TYPE_PCMT16), 179 TYPE(PERIPHC_TWC, CLOCK_TYPE_PCMT), 180 TYPE(PERIPHC_NONE, CLOCK_TYPE_NONE), 181 TYPE(PERIPHC_SPI1, CLOCK_TYPE_PCMT), 182 TYPE(PERIPHC_DISP1, CLOCK_TYPE_PDCT), 183 TYPE(PERIPHC_DISP2, CLOCK_TYPE_PDCT), 184 185 /* 0x10 */ 186 TYPE(PERIPHC_CVE, CLOCK_TYPE_PDCT), 187 TYPE(PERIPHC_IDE0, CLOCK_TYPE_PCMT), 188 TYPE(PERIPHC_VI, CLOCK_TYPE_MCPA), 189 TYPE(PERIPHC_NONE, CLOCK_TYPE_NONE), 190 TYPE(PERIPHC_SDMMC1, CLOCK_TYPE_PCMT), 191 TYPE(PERIPHC_SDMMC2, CLOCK_TYPE_PCMT), 192 TYPE(PERIPHC_G3D, CLOCK_TYPE_MCPA), 193 TYPE(PERIPHC_G2D, CLOCK_TYPE_MCPA), 194 195 /* 0x18 */ 196 TYPE(PERIPHC_NDFLASH, CLOCK_TYPE_PCMT), 197 TYPE(PERIPHC_SDMMC4, CLOCK_TYPE_PCMT), 198 TYPE(PERIPHC_VFIR, CLOCK_TYPE_PCMT), 199 TYPE(PERIPHC_EPP, CLOCK_TYPE_MCPA), 200 TYPE(PERIPHC_MPE, CLOCK_TYPE_MCPA), 201 TYPE(PERIPHC_MIPI, CLOCK_TYPE_PCMT), 202 TYPE(PERIPHC_UART1, CLOCK_TYPE_PCMT), 203 TYPE(PERIPHC_UART2, CLOCK_TYPE_PCMT), 204 205 /* 0x20 */ 206 TYPE(PERIPHC_HOST1X, CLOCK_TYPE_MCPA), 207 TYPE(PERIPHC_NONE, CLOCK_TYPE_NONE), 208 TYPE(PERIPHC_TVO, CLOCK_TYPE_PDCT), 209 TYPE(PERIPHC_HDMI, CLOCK_TYPE_PDCT), 210 TYPE(PERIPHC_NONE, CLOCK_TYPE_NONE), 211 TYPE(PERIPHC_TVDAC, CLOCK_TYPE_PDCT), 212 TYPE(PERIPHC_I2C2, CLOCK_TYPE_PCMT16), 213 TYPE(PERIPHC_EMC, CLOCK_TYPE_MCPT), 214 215 /* 0x28 */ 216 TYPE(PERIPHC_UART3, CLOCK_TYPE_PCMT), 217 TYPE(PERIPHC_NONE, CLOCK_TYPE_NONE), 218 TYPE(PERIPHC_VI, CLOCK_TYPE_MCPA), 219 TYPE(PERIPHC_NONE, CLOCK_TYPE_NONE), 220 TYPE(PERIPHC_NONE, CLOCK_TYPE_NONE), 221 TYPE(PERIPHC_SPI4, CLOCK_TYPE_PCMT), 222 TYPE(PERIPHC_I2C3, CLOCK_TYPE_PCMT16), 223 TYPE(PERIPHC_SDMMC3, CLOCK_TYPE_PCMT), 224 225 /* 0x30 */ 226 TYPE(PERIPHC_UART4, CLOCK_TYPE_PCMT), 227 TYPE(PERIPHC_UART5, CLOCK_TYPE_PCMT), 228 TYPE(PERIPHC_VDE, CLOCK_TYPE_PCMT), 229 TYPE(PERIPHC_OWR, CLOCK_TYPE_PCMT), 230 TYPE(PERIPHC_NOR, CLOCK_TYPE_PCMT), 231 TYPE(PERIPHC_CSITE, CLOCK_TYPE_PCMT), 232 }; 233 234 /* 235 * This array translates a periph_id to a periphc_internal_id 236 * 237 * Not present/matched up: 238 * uint vi_sensor; _VI_SENSOR_0, 0x1A8 239 * SPDIF - which is both 0x08 and 0x0c 240 * 241 */ 242 #define NONE(name) (-1) 243 #define OFFSET(name, value) PERIPHC_ ## name 244 static s8 periph_id_to_internal_id[PERIPH_ID_COUNT] = { 245 /* Low word: 31:0 */ 246 NONE(CPU), 247 NONE(RESERVED1), 248 NONE(RESERVED2), 249 NONE(AC97), 250 NONE(RTC), 251 NONE(TMR), 252 PERIPHC_UART1, 253 PERIPHC_UART2, /* and vfir 0x68 */ 254 255 /* 0x08 */ 256 NONE(GPIO), 257 PERIPHC_SDMMC2, 258 NONE(SPDIF), /* 0x08 and 0x0c, unclear which to use */ 259 PERIPHC_I2S1, 260 PERIPHC_I2C1, 261 PERIPHC_NDFLASH, 262 PERIPHC_SDMMC1, 263 PERIPHC_SDMMC4, 264 265 /* 0x10 */ 266 PERIPHC_TWC, 267 PERIPHC_PWM, 268 PERIPHC_I2S2, 269 PERIPHC_EPP, 270 PERIPHC_VI, 271 PERIPHC_G2D, 272 NONE(USBD), 273 NONE(ISP), 274 275 /* 0x18 */ 276 PERIPHC_G3D, 277 PERIPHC_IDE0, 278 PERIPHC_DISP2, 279 PERIPHC_DISP1, 280 PERIPHC_HOST1X, 281 NONE(VCP), 282 NONE(RESERVED30), 283 NONE(CACHE2), 284 285 /* Middle word: 63:32 */ 286 NONE(MEM), 287 NONE(AHBDMA), 288 NONE(APBDMA), 289 NONE(RESERVED35), 290 NONE(KBC), 291 NONE(STAT_MON), 292 NONE(PMC), 293 NONE(FUSE), 294 295 /* 0x28 */ 296 NONE(KFUSE), 297 NONE(SBC1), /* SBC1, 0x34, is this SPI1? */ 298 PERIPHC_NOR, 299 PERIPHC_SPI1, 300 PERIPHC_SPI2, 301 PERIPHC_XIO, 302 PERIPHC_SPI3, 303 PERIPHC_DVC_I2C, 304 305 /* 0x30 */ 306 NONE(DSI), 307 PERIPHC_TVO, /* also CVE 0x40 */ 308 PERIPHC_MIPI, 309 PERIPHC_HDMI, 310 PERIPHC_CSITE, 311 PERIPHC_TVDAC, 312 PERIPHC_I2C2, 313 PERIPHC_UART3, 314 315 /* 0x38 */ 316 NONE(RESERVED56), 317 PERIPHC_EMC, 318 NONE(USB2), 319 NONE(USB3), 320 PERIPHC_MPE, 321 PERIPHC_VDE, 322 NONE(BSEA), 323 NONE(BSEV), 324 325 /* Upper word 95:64 */ 326 NONE(SPEEDO), 327 PERIPHC_UART4, 328 PERIPHC_UART5, 329 PERIPHC_I2C3, 330 PERIPHC_SPI4, 331 PERIPHC_SDMMC3, 332 NONE(PCIE), 333 PERIPHC_OWR, 334 335 /* 0x48 */ 336 NONE(AFI), 337 NONE(CORESIGHT), 338 NONE(PCIEXCLK), 339 NONE(AVPUCQ), 340 NONE(RESERVED76), 341 NONE(RESERVED77), 342 NONE(RESERVED78), 343 NONE(RESERVED79), 344 345 /* 0x50 */ 346 NONE(RESERVED80), 347 NONE(RESERVED81), 348 NONE(RESERVED82), 349 NONE(RESERVED83), 350 NONE(IRAMA), 351 NONE(IRAMB), 352 NONE(IRAMC), 353 NONE(IRAMD), 354 355 /* 0x58 */ 356 NONE(CRAM2), 357 }; 358 359 /* 360 * PLL divider shift/mask tables for all PLL IDs. 361 */ 362 struct clk_pll_info tegra_pll_info_table[CLOCK_ID_PLL_COUNT] = { 363 /* 364 * T20 and T25 365 * NOTE: If kcp_mask/kvco_mask == 0, they're not used in that PLL (PLLX, etc.) 366 * If lock_ena or lock_det are >31, they're not used in that PLL. 367 */ 368 369 { .m_shift = 0, .m_mask = 0xFF, .n_shift = 8, .n_mask = 0x3FF, .p_shift = 20, .p_mask = 0x0F, 370 .lock_ena = 24, .lock_det = 27, .kcp_shift = 28, .kcp_mask = 3, .kvco_shift = 27, .kvco_mask = 1 }, /* PLLC */ 371 { .m_shift = 0, .m_mask = 0xFF, .n_shift = 8, .n_mask = 0x3FF, .p_shift = 0, .p_mask = 0, 372 .lock_ena = 0, .lock_det = 27, .kcp_shift = 1, .kcp_mask = 3, .kvco_shift = 0, .kvco_mask = 1 }, /* PLLM */ 373 { .m_shift = 0, .m_mask = 0x1F, .n_shift = 8, .n_mask = 0x3FF, .p_shift = 20, .p_mask = 0x07, 374 .lock_ena = 18, .lock_det = 27, .kcp_shift = 8, .kcp_mask = 0xF, .kvco_shift = 4, .kvco_mask = 0xF }, /* PLLP */ 375 { .m_shift = 0, .m_mask = 0x1F, .n_shift = 8, .n_mask = 0x3FF, .p_shift = 20, .p_mask = 0x07, 376 .lock_ena = 18, .lock_det = 27, .kcp_shift = 8, .kcp_mask = 0xF, .kvco_shift = 4, .kvco_mask = 0xF }, /* PLLA */ 377 { .m_shift = 0, .m_mask = 0x1F, .n_shift = 8, .n_mask = 0x3FF, .p_shift = 20, .p_mask = 0x01, 378 .lock_ena = 22, .lock_det = 27, .kcp_shift = 8, .kcp_mask = 0xF, .kvco_shift = 4, .kvco_mask = 0xF }, /* PLLU */ 379 { .m_shift = 0, .m_mask = 0x1F, .n_shift = 8, .n_mask = 0x3FF, .p_shift = 20, .p_mask = 0x07, 380 .lock_ena = 22, .lock_det = 27, .kcp_shift = 8, .kcp_mask = 0xF, .kvco_shift = 4, .kvco_mask = 0xF }, /* PLLD */ 381 { .m_shift = 0, .m_mask = 0x1F, .n_shift = 8, .n_mask = 0x3FF, .p_shift = 20, .p_mask = 0x0F, 382 .lock_ena = 18, .lock_det = 27, .kcp_shift = 8, .kcp_mask = 0xF, .kvco_shift = 0, .kvco_mask = 0 }, /* PLLX */ 383 { .m_shift = 0, .m_mask = 0xFF, .n_shift = 8, .n_mask = 0xFF, .p_shift = 0, .p_mask = 0, 384 .lock_ena = 9, .lock_det = 11, .kcp_shift = 6, .kcp_mask = 3, .kvco_shift = 0, .kvco_mask = 1 }, /* PLLE */ 385 { .m_shift = 0, .m_mask = 0x0F, .n_shift = 8, .n_mask = 0x3FF, .p_shift = 20, .p_mask = 0x07, 386 .lock_ena = 18, .lock_det = 0, .kcp_shift = 8, .kcp_mask = 0xF, .kvco_shift = 4, .kvco_mask = 0xF }, /* PLLS */ 387 }; 388 389 /* 390 * Get the oscillator frequency, from the corresponding hardware configuration 391 * field. T20 has 4 frequencies that it supports. 392 */ 393 enum clock_osc_freq clock_get_osc_freq(void) 394 { 395 struct clk_rst_ctlr *clkrst = 396 (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE; 397 u32 reg; 398 399 reg = readl(&clkrst->crc_osc_ctrl); 400 return (reg & OSC_FREQ_MASK) >> OSC_FREQ_SHIFT; 401 } 402 403 /* Returns a pointer to the clock source register for a peripheral */ 404 u32 *get_periph_source_reg(enum periph_id periph_id) 405 { 406 struct clk_rst_ctlr *clkrst = 407 (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE; 408 enum periphc_internal_id internal_id; 409 410 assert(clock_periph_id_isvalid(periph_id)); 411 internal_id = periph_id_to_internal_id[periph_id]; 412 assert(internal_id != -1); 413 return &clkrst->crc_clk_src[internal_id]; 414 } 415 416 /** 417 * Given a peripheral ID and the required source clock, this returns which 418 * value should be programmed into the source mux for that peripheral. 419 * 420 * There is special code here to handle the one source type with 5 sources. 421 * 422 * @param periph_id peripheral to start 423 * @param source PLL id of required parent clock 424 * @param mux_bits Set to number of bits in mux register: 2 or 4 425 * @param divider_bits Set to number of divider bits (8 or 16) 426 * @return mux value (0-4, or -1 if not found) 427 */ 428 int get_periph_clock_source(enum periph_id periph_id, 429 enum clock_id parent, int *mux_bits, int *divider_bits) 430 { 431 enum clock_type_id type; 432 enum periphc_internal_id internal_id; 433 int mux; 434 435 assert(clock_periph_id_isvalid(periph_id)); 436 437 internal_id = periph_id_to_internal_id[periph_id]; 438 assert(periphc_internal_id_isvalid(internal_id)); 439 440 type = clock_periph_type[internal_id]; 441 assert(clock_type_id_isvalid(type)); 442 443 /* 444 * Special cases here for the clock with a 4-bit source mux and I2C 445 * with its 16-bit divisor 446 */ 447 if (type == CLOCK_TYPE_PCXTS) 448 *mux_bits = MASK_BITS_31_28; 449 else 450 *mux_bits = MASK_BITS_31_30; 451 if (type == CLOCK_TYPE_PCMT16) 452 *divider_bits = 16; 453 else 454 *divider_bits = 8; 455 456 for (mux = 0; mux < CLOCK_MAX_MUX; mux++) 457 if (clock_source[type][mux] == parent) 458 return mux; 459 460 /* 461 * Not found: it might be looking for the 'S' in CLOCK_TYPE_PCXTS 462 * which is not in our table. If not, then they are asking for a 463 * source which this peripheral can't access through its mux. 464 */ 465 assert(type == CLOCK_TYPE_PCXTS); 466 assert(parent == CLOCK_ID_SFROM32KHZ); 467 if (type == CLOCK_TYPE_PCXTS && parent == CLOCK_ID_SFROM32KHZ) 468 return 4; /* mux value for this clock */ 469 470 /* if we get here, either us or the caller has made a mistake */ 471 printf("Caller requested bad clock: periph=%d, parent=%d\n", periph_id, 472 parent); 473 return -1; 474 } 475 476 void clock_set_enable(enum periph_id periph_id, int enable) 477 { 478 struct clk_rst_ctlr *clkrst = 479 (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE; 480 u32 *clk = &clkrst->crc_clk_out_enb[PERIPH_REG(periph_id)]; 481 u32 reg; 482 483 /* Enable/disable the clock to this peripheral */ 484 assert(clock_periph_id_isvalid(periph_id)); 485 reg = readl(clk); 486 if (enable) 487 reg |= PERIPH_MASK(periph_id); 488 else 489 reg &= ~PERIPH_MASK(periph_id); 490 writel(reg, clk); 491 } 492 493 void reset_set_enable(enum periph_id periph_id, int enable) 494 { 495 struct clk_rst_ctlr *clkrst = 496 (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE; 497 u32 *reset = &clkrst->crc_rst_dev[PERIPH_REG(periph_id)]; 498 u32 reg; 499 500 /* Enable/disable reset to the peripheral */ 501 assert(clock_periph_id_isvalid(periph_id)); 502 reg = readl(reset); 503 if (enable) 504 reg |= PERIPH_MASK(periph_id); 505 else 506 reg &= ~PERIPH_MASK(periph_id); 507 writel(reg, reset); 508 } 509 510 #if CONFIG_IS_ENABLED(OF_CONTROL) 511 /* 512 * Convert a device tree clock ID to our peripheral ID. They are mostly 513 * the same but we are very cautious so we check that a valid clock ID is 514 * provided. 515 * 516 * @param clk_id Clock ID according to tegra20 device tree binding 517 * @return peripheral ID, or PERIPH_ID_NONE if the clock ID is invalid 518 */ 519 enum periph_id clk_id_to_periph_id(int clk_id) 520 { 521 if (clk_id > PERIPH_ID_COUNT) 522 return PERIPH_ID_NONE; 523 524 switch (clk_id) { 525 case PERIPH_ID_RESERVED1: 526 case PERIPH_ID_RESERVED2: 527 case PERIPH_ID_RESERVED30: 528 case PERIPH_ID_RESERVED35: 529 case PERIPH_ID_RESERVED56: 530 case PERIPH_ID_PCIEXCLK: 531 case PERIPH_ID_RESERVED76: 532 case PERIPH_ID_RESERVED77: 533 case PERIPH_ID_RESERVED78: 534 case PERIPH_ID_RESERVED79: 535 case PERIPH_ID_RESERVED80: 536 case PERIPH_ID_RESERVED81: 537 case PERIPH_ID_RESERVED82: 538 case PERIPH_ID_RESERVED83: 539 case PERIPH_ID_RESERVED91: 540 return PERIPH_ID_NONE; 541 default: 542 return clk_id; 543 } 544 } 545 #endif /* CONFIG_IS_ENABLED(OF_CONTROL) */ 546 547 void clock_early_init(void) 548 { 549 /* 550 * PLLP output frequency set to 216MHz 551 * PLLC output frequency set to 600Mhz 552 * 553 * TODO: Can we calculate these values instead of hard-coding? 554 */ 555 switch (clock_get_osc_freq()) { 556 case CLOCK_OSC_FREQ_12_0: /* OSC is 12Mhz */ 557 clock_set_rate(CLOCK_ID_PERIPH, 432, 12, 1, 8); 558 clock_set_rate(CLOCK_ID_CGENERAL, 600, 12, 0, 8); 559 break; 560 561 case CLOCK_OSC_FREQ_26_0: /* OSC is 26Mhz */ 562 clock_set_rate(CLOCK_ID_PERIPH, 432, 26, 1, 8); 563 clock_set_rate(CLOCK_ID_CGENERAL, 600, 26, 0, 8); 564 break; 565 566 case CLOCK_OSC_FREQ_13_0: /* OSC is 13Mhz */ 567 clock_set_rate(CLOCK_ID_PERIPH, 432, 13, 1, 8); 568 clock_set_rate(CLOCK_ID_CGENERAL, 600, 13, 0, 8); 569 break; 570 case CLOCK_OSC_FREQ_19_2: 571 default: 572 /* 573 * These are not supported. It is too early to print a 574 * message and the UART likely won't work anyway due to the 575 * oscillator being wrong. 576 */ 577 break; 578 } 579 } 580 581 void arch_timer_init(void) 582 { 583 } 584 585 #define PMC_SATA_PWRGT 0x1ac 586 #define PMC_SATA_PWRGT_PLLE_IDDQ_OVERRIDE (1 << 5) 587 #define PMC_SATA_PWRGT_PLLE_IDDQ_SWCTL (1 << 4) 588 589 #define PLLE_SS_CNTL 0x68 590 #define PLLE_SS_CNTL_SSCINCINTRV(x) (((x) & 0x3f) << 24) 591 #define PLLE_SS_CNTL_SSCINC(x) (((x) & 0xff) << 16) 592 #define PLLE_SS_CNTL_SSCBYP (1 << 12) 593 #define PLLE_SS_CNTL_INTERP_RESET (1 << 11) 594 #define PLLE_SS_CNTL_BYPASS_SS (1 << 10) 595 #define PLLE_SS_CNTL_SSCMAX(x) (((x) & 0x1ff) << 0) 596 597 #define PLLE_BASE 0x0e8 598 #define PLLE_BASE_ENABLE_CML (1 << 31) 599 #define PLLE_BASE_ENABLE (1 << 30) 600 #define PLLE_BASE_PLDIV_CML(x) (((x) & 0xf) << 24) 601 #define PLLE_BASE_PLDIV(x) (((x) & 0x3f) << 16) 602 #define PLLE_BASE_NDIV(x) (((x) & 0xff) << 8) 603 #define PLLE_BASE_MDIV(x) (((x) & 0xff) << 0) 604 605 #define PLLE_MISC 0x0ec 606 #define PLLE_MISC_SETUP_BASE(x) (((x) & 0xffff) << 16) 607 #define PLLE_MISC_PLL_READY (1 << 15) 608 #define PLLE_MISC_LOCK (1 << 11) 609 #define PLLE_MISC_LOCK_ENABLE (1 << 9) 610 #define PLLE_MISC_SETUP_EXT(x) (((x) & 0x3) << 2) 611 612 static int tegra_plle_train(void) 613 { 614 unsigned int timeout = 2000; 615 unsigned long value; 616 617 value = readl(NV_PA_PMC_BASE + PMC_SATA_PWRGT); 618 value |= PMC_SATA_PWRGT_PLLE_IDDQ_OVERRIDE; 619 writel(value, NV_PA_PMC_BASE + PMC_SATA_PWRGT); 620 621 value = readl(NV_PA_PMC_BASE + PMC_SATA_PWRGT); 622 value |= PMC_SATA_PWRGT_PLLE_IDDQ_SWCTL; 623 writel(value, NV_PA_PMC_BASE + PMC_SATA_PWRGT); 624 625 value = readl(NV_PA_PMC_BASE + PMC_SATA_PWRGT); 626 value &= ~PMC_SATA_PWRGT_PLLE_IDDQ_OVERRIDE; 627 writel(value, NV_PA_PMC_BASE + PMC_SATA_PWRGT); 628 629 do { 630 value = readl(NV_PA_CLK_RST_BASE + PLLE_MISC); 631 if (value & PLLE_MISC_PLL_READY) 632 break; 633 634 udelay(100); 635 } while (--timeout); 636 637 if (timeout == 0) { 638 error("timeout waiting for PLLE to become ready"); 639 return -ETIMEDOUT; 640 } 641 642 return 0; 643 } 644 645 int tegra_plle_enable(void) 646 { 647 unsigned int timeout = 1000; 648 u32 value; 649 int err; 650 651 /* disable PLLE clock */ 652 value = readl(NV_PA_CLK_RST_BASE + PLLE_BASE); 653 value &= ~PLLE_BASE_ENABLE_CML; 654 value &= ~PLLE_BASE_ENABLE; 655 writel(value, NV_PA_CLK_RST_BASE + PLLE_BASE); 656 657 /* clear lock enable and setup field */ 658 value = readl(NV_PA_CLK_RST_BASE + PLLE_MISC); 659 value &= ~PLLE_MISC_LOCK_ENABLE; 660 value &= ~PLLE_MISC_SETUP_BASE(0xffff); 661 value &= ~PLLE_MISC_SETUP_EXT(0x3); 662 writel(value, NV_PA_CLK_RST_BASE + PLLE_MISC); 663 664 value = readl(NV_PA_CLK_RST_BASE + PLLE_MISC); 665 if ((value & PLLE_MISC_PLL_READY) == 0) { 666 err = tegra_plle_train(); 667 if (err < 0) { 668 error("failed to train PLLE: %d", err); 669 return err; 670 } 671 } 672 673 value = readl(NV_PA_CLK_RST_BASE + PLLE_MISC); 674 value |= PLLE_MISC_SETUP_BASE(0x7); 675 value |= PLLE_MISC_LOCK_ENABLE; 676 value |= PLLE_MISC_SETUP_EXT(0); 677 writel(value, NV_PA_CLK_RST_BASE + PLLE_MISC); 678 679 value = readl(NV_PA_CLK_RST_BASE + PLLE_SS_CNTL); 680 value |= PLLE_SS_CNTL_SSCBYP | PLLE_SS_CNTL_INTERP_RESET | 681 PLLE_SS_CNTL_BYPASS_SS; 682 writel(value, NV_PA_CLK_RST_BASE + PLLE_SS_CNTL); 683 684 value = readl(NV_PA_CLK_RST_BASE + PLLE_BASE); 685 value |= PLLE_BASE_ENABLE_CML | PLLE_BASE_ENABLE; 686 writel(value, NV_PA_CLK_RST_BASE + PLLE_BASE); 687 688 do { 689 value = readl(NV_PA_CLK_RST_BASE + PLLE_MISC); 690 if (value & PLLE_MISC_LOCK) 691 break; 692 693 udelay(2); 694 } while (--timeout); 695 696 if (timeout == 0) { 697 error("timeout waiting for PLLE to lock"); 698 return -ETIMEDOUT; 699 } 700 701 udelay(50); 702 703 value = readl(NV_PA_CLK_RST_BASE + PLLE_SS_CNTL); 704 value &= ~PLLE_SS_CNTL_SSCINCINTRV(0x3f); 705 value |= PLLE_SS_CNTL_SSCINCINTRV(0x18); 706 707 value &= ~PLLE_SS_CNTL_SSCINC(0xff); 708 value |= PLLE_SS_CNTL_SSCINC(0x01); 709 710 value &= ~PLLE_SS_CNTL_SSCBYP; 711 value &= ~PLLE_SS_CNTL_INTERP_RESET; 712 value &= ~PLLE_SS_CNTL_BYPASS_SS; 713 714 value &= ~PLLE_SS_CNTL_SSCMAX(0x1ff); 715 value |= PLLE_SS_CNTL_SSCMAX(0x24); 716 writel(value, NV_PA_CLK_RST_BASE + PLLE_SS_CNTL); 717 718 return 0; 719 } 720