1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * Copyright (c) 2016-2018, NVIDIA CORPORATION. 4 */ 5 6 #include <common.h> 7 #include <fdt_support.h> 8 #include <fdtdec.h> 9 #include <linux/sizes.h> 10 #include <asm/arch/tegra.h> 11 #include <asm/armv8/mmu.h> 12 13 /* 14 * Size of a region that's large enough to hold the relocated U-Boot and all 15 * other allocations made around it (stack, heap, page tables, etc.) 16 * In practice, running "bdinfo" at the shell prompt, the stack reaches about 17 * 5MB from the address selected for ram_top as of the time of writing, 18 * so a 16MB region should be plenty. 19 */ 20 #define MIN_USABLE_RAM_SIZE SZ_16M 21 /* 22 * The amount of space we expect to require for stack usage. Used to validate 23 * that all reservations fit into the region selected for the relocation target 24 */ 25 #define MIN_USABLE_STACK_SIZE SZ_1M 26 27 DECLARE_GLOBAL_DATA_PTR; 28 29 extern unsigned long nvtboot_boot_x0; 30 extern struct mm_region tegra_mem_map[]; 31 32 /* 33 * These variables are written to before relocation, and hence cannot be 34 * in.bss, since .bss overlaps the DTB that's appended to the U-Boot binary. 35 * The section attribute forces this into .data and avoids this issue. This 36 * also has the nice side-effect of the content being valid after relocation. 37 */ 38 39 /* The number of valid entries in ram_banks[] */ 40 static int ram_bank_count __attribute__((section(".data"))); 41 42 /* 43 * The usable top-of-RAM for U-Boot. This is both: 44 * a) Below 4GB to avoid issues with peripherals that use 32-bit addressing. 45 * b) At the end of a region that has enough space to hold the relocated U-Boot 46 * and all other allocations made around it (stack, heap, page tables, etc.) 47 */ 48 static u64 ram_top __attribute__((section(".data"))); 49 /* The base address of the region of RAM that ends at ram_top */ 50 static u64 region_base __attribute__((section(".data"))); 51 52 int dram_init(void) 53 { 54 unsigned int na, ns; 55 const void *nvtboot_blob = (void *)nvtboot_boot_x0; 56 int node, len, i; 57 const u32 *prop; 58 59 na = fdtdec_get_uint(nvtboot_blob, 0, "#address-cells", 2); 60 ns = fdtdec_get_uint(nvtboot_blob, 0, "#size-cells", 2); 61 62 node = fdt_path_offset(nvtboot_blob, "/memory"); 63 if (node < 0) { 64 pr_err("Can't find /memory node in nvtboot DTB"); 65 hang(); 66 } 67 prop = fdt_getprop(nvtboot_blob, node, "reg", &len); 68 if (!prop) { 69 pr_err("Can't find /memory/reg property in nvtboot DTB"); 70 hang(); 71 } 72 73 /* Calculate the true # of base/size pairs to read */ 74 len /= 4; /* Convert bytes to number of cells */ 75 len /= (na + ns); /* Convert cells to number of banks */ 76 if (len > CONFIG_NR_DRAM_BANKS) 77 len = CONFIG_NR_DRAM_BANKS; 78 79 /* Parse the /memory node, and save useful entries */ 80 gd->ram_size = 0; 81 ram_bank_count = 0; 82 for (i = 0; i < len; i++) { 83 u64 bank_start, bank_end, bank_size, usable_bank_size; 84 85 /* Extract raw memory region data from DTB */ 86 bank_start = fdt_read_number(prop, na); 87 prop += na; 88 bank_size = fdt_read_number(prop, ns); 89 prop += ns; 90 gd->ram_size += bank_size; 91 bank_end = bank_start + bank_size; 92 debug("Bank %d: %llx..%llx (+%llx)\n", i, 93 bank_start, bank_end, bank_size); 94 95 /* 96 * Align the bank to MMU section size. This is not strictly 97 * necessary, since the translation table construction code 98 * handles page granularity without issue. However, aligning 99 * the MMU entries reduces the size and number of levels in the 100 * page table, so is worth it. 101 */ 102 bank_start = ROUND(bank_start, SZ_2M); 103 bank_end = bank_end & ~(SZ_2M - 1); 104 bank_size = bank_end - bank_start; 105 debug(" aligned: %llx..%llx (+%llx)\n", 106 bank_start, bank_end, bank_size); 107 if (bank_end <= bank_start) 108 continue; 109 110 /* Record data used to create MMU translation tables */ 111 ram_bank_count++; 112 /* Index below is deliberately 1-based to skip MMIO entry */ 113 tegra_mem_map[ram_bank_count].virt = bank_start; 114 tegra_mem_map[ram_bank_count].phys = bank_start; 115 tegra_mem_map[ram_bank_count].size = bank_size; 116 tegra_mem_map[ram_bank_count].attrs = 117 PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_INNER_SHARE; 118 119 /* Determine best bank to relocate U-Boot into */ 120 if (bank_end > SZ_4G) 121 bank_end = SZ_4G; 122 debug(" end %llx (usable)\n", bank_end); 123 usable_bank_size = bank_end - bank_start; 124 debug(" size %llx (usable)\n", usable_bank_size); 125 if ((usable_bank_size >= MIN_USABLE_RAM_SIZE) && 126 (bank_end > ram_top)) { 127 ram_top = bank_end; 128 region_base = bank_start; 129 debug("ram top now %llx\n", ram_top); 130 } 131 } 132 133 /* Ensure memory map contains the desired sentinel entry */ 134 tegra_mem_map[ram_bank_count + 1].virt = 0; 135 tegra_mem_map[ram_bank_count + 1].phys = 0; 136 tegra_mem_map[ram_bank_count + 1].size = 0; 137 tegra_mem_map[ram_bank_count + 1].attrs = 0; 138 139 /* Error out if a relocation target couldn't be found */ 140 if (!ram_top) { 141 pr_err("Can't find a usable RAM top"); 142 hang(); 143 } 144 145 return 0; 146 } 147 148 int dram_init_banksize(void) 149 { 150 int i; 151 152 if ((gd->start_addr_sp - region_base) < MIN_USABLE_STACK_SIZE) { 153 pr_err("Reservations exceed chosen region size"); 154 hang(); 155 } 156 157 for (i = 0; i < ram_bank_count; i++) { 158 gd->bd->bi_dram[i].start = tegra_mem_map[1 + i].virt; 159 gd->bd->bi_dram[i].size = tegra_mem_map[1 + i].size; 160 } 161 162 #ifdef CONFIG_PCI 163 gd->pci_ram_top = ram_top; 164 #endif 165 166 return 0; 167 } 168 169 ulong board_get_usable_ram_top(ulong total_size) 170 { 171 return ram_top; 172 } 173