1 /* 2 * Copyright (c) 2016-2018, NVIDIA CORPORATION. 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 #include <common.h> 8 #include <fdt_support.h> 9 #include <fdtdec.h> 10 #include <asm/arch/tegra.h> 11 #include <asm/armv8/mmu.h> 12 13 #define SZ_4G 0x100000000ULL 14 15 /* 16 * Size of a region that's large enough to hold the relocated U-Boot and all 17 * other allocations made around it (stack, heap, page tables, etc.) 18 * In practice, running "bdinfo" at the shell prompt, the stack reaches about 19 * 5MB from the address selected for ram_top as of the time of writing, 20 * so a 16MB region should be plenty. 21 */ 22 #define MIN_USABLE_RAM_SIZE SZ_16M 23 /* 24 * The amount of space we expect to require for stack usage. Used to validate 25 * that all reservations fit into the region selected for the relocation target 26 */ 27 #define MIN_USABLE_STACK_SIZE SZ_1M 28 29 DECLARE_GLOBAL_DATA_PTR; 30 31 extern unsigned long nvtboot_boot_x0; 32 extern struct mm_region tegra_mem_map[]; 33 34 /* 35 * These variables are written to before relocation, and hence cannot be 36 * in.bss, since .bss overlaps the DTB that's appended to the U-Boot binary. 37 * The section attribute forces this into .data and avoids this issue. This 38 * also has the nice side-effect of the content being valid after relocation. 39 */ 40 41 /* The number of valid entries in ram_banks[] */ 42 static int ram_bank_count __attribute__((section(".data"))); 43 44 /* 45 * The usable top-of-RAM for U-Boot. This is both: 46 * a) Below 4GB to avoid issues with peripherals that use 32-bit addressing. 47 * b) At the end of a region that has enough space to hold the relocated U-Boot 48 * and all other allocations made around it (stack, heap, page tables, etc.) 49 */ 50 static u64 ram_top __attribute__((section(".data"))); 51 /* The base address of the region of RAM that ends at ram_top */ 52 static u64 region_base __attribute__((section(".data"))); 53 54 int dram_init(void) 55 { 56 unsigned int na, ns; 57 const void *nvtboot_blob = (void *)nvtboot_boot_x0; 58 int node, len, i; 59 const u32 *prop; 60 61 na = fdtdec_get_uint(nvtboot_blob, 0, "#address-cells", 2); 62 ns = fdtdec_get_uint(nvtboot_blob, 0, "#size-cells", 2); 63 64 node = fdt_path_offset(nvtboot_blob, "/memory"); 65 if (node < 0) { 66 pr_err("Can't find /memory node in nvtboot DTB"); 67 hang(); 68 } 69 prop = fdt_getprop(nvtboot_blob, node, "reg", &len); 70 if (!prop) { 71 pr_err("Can't find /memory/reg property in nvtboot DTB"); 72 hang(); 73 } 74 75 /* Calculate the true # of base/size pairs to read */ 76 len /= 4; /* Convert bytes to number of cells */ 77 len /= (na + ns); /* Convert cells to number of banks */ 78 if (len > CONFIG_NR_DRAM_BANKS) 79 len = CONFIG_NR_DRAM_BANKS; 80 81 /* Parse the /memory node, and save useful entries */ 82 gd->ram_size = 0; 83 ram_bank_count = 0; 84 for (i = 0; i < len; i++) { 85 u64 bank_start, bank_end, bank_size, usable_bank_size; 86 87 /* Extract raw memory region data from DTB */ 88 bank_start = fdt_read_number(prop, na); 89 prop += na; 90 bank_size = fdt_read_number(prop, ns); 91 prop += ns; 92 gd->ram_size += bank_size; 93 bank_end = bank_start + bank_size; 94 debug("Bank %d: %llx..%llx (+%llx)\n", i, 95 bank_start, bank_end, bank_size); 96 97 /* 98 * Align the bank to MMU section size. This is not strictly 99 * necessary, since the translation table construction code 100 * handles page granularity without issue. However, aligning 101 * the MMU entries reduces the size and number of levels in the 102 * page table, so is worth it. 103 */ 104 bank_start = ROUND(bank_start, SZ_2M); 105 bank_end = bank_end & ~(SZ_2M - 1); 106 bank_size = bank_end - bank_start; 107 debug(" aligned: %llx..%llx (+%llx)\n", 108 bank_start, bank_end, bank_size); 109 if (bank_end <= bank_start) 110 continue; 111 112 /* Record data used to create MMU translation tables */ 113 ram_bank_count++; 114 /* Index below is deliberately 1-based to skip MMIO entry */ 115 tegra_mem_map[ram_bank_count].virt = bank_start; 116 tegra_mem_map[ram_bank_count].phys = bank_start; 117 tegra_mem_map[ram_bank_count].size = bank_size; 118 tegra_mem_map[ram_bank_count].attrs = 119 PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_INNER_SHARE; 120 121 /* Determine best bank to relocate U-Boot into */ 122 if (bank_end > SZ_4G) 123 bank_end = SZ_4G; 124 debug(" end %llx (usable)\n", bank_end); 125 usable_bank_size = bank_end - bank_start; 126 debug(" size %llx (usable)\n", usable_bank_size); 127 if ((usable_bank_size >= MIN_USABLE_RAM_SIZE) && 128 (bank_end > ram_top)) { 129 ram_top = bank_end; 130 region_base = bank_start; 131 debug("ram top now %llx\n", ram_top); 132 } 133 } 134 135 /* Ensure memory map contains the desired sentinel entry */ 136 tegra_mem_map[ram_bank_count + 1].virt = 0; 137 tegra_mem_map[ram_bank_count + 1].phys = 0; 138 tegra_mem_map[ram_bank_count + 1].size = 0; 139 tegra_mem_map[ram_bank_count + 1].attrs = 0; 140 141 /* Error out if a relocation target couldn't be found */ 142 if (!ram_top) { 143 pr_err("Can't find a usable RAM top"); 144 hang(); 145 } 146 147 return 0; 148 } 149 150 int dram_init_banksize(void) 151 { 152 int i; 153 154 if ((gd->start_addr_sp - region_base) < MIN_USABLE_STACK_SIZE) { 155 pr_err("Reservations exceed chosen region size"); 156 hang(); 157 } 158 159 for (i = 0; i < ram_bank_count; i++) { 160 gd->bd->bi_dram[i].start = tegra_mem_map[1 + i].virt; 161 gd->bd->bi_dram[i].size = tegra_mem_map[1 + i].size; 162 } 163 164 #ifdef CONFIG_PCI 165 gd->pci_ram_top = ram_top; 166 #endif 167 168 return 0; 169 } 170 171 ulong board_get_usable_ram_top(ulong total_size) 172 { 173 return ram_top; 174 } 175