1 /* 2 * Copyright (c) 2014, NVIDIA CORPORATION. All rights reserved. 3 * 4 * SPDX-License-Identifier: GPL-2.0 5 */ 6 7 #define pr_fmt(fmt) "tegra-xusb-padctl: " fmt 8 9 #include <common.h> 10 #include <errno.h> 11 #include <fdtdec.h> 12 #include <malloc.h> 13 14 #include <asm/io.h> 15 16 #include <asm/arch/clock.h> 17 #include <asm/arch-tegra/xusb-padctl.h> 18 19 #include <dt-bindings/pinctrl/pinctrl-tegra-xusb.h> 20 21 #define XUSB_PADCTL_ELPG_PROGRAM 0x01c 22 #define XUSB_PADCTL_ELPG_PROGRAM_AUX_MUX_LP0_VCORE_DOWN (1 << 26) 23 #define XUSB_PADCTL_ELPG_PROGRAM_AUX_MUX_LP0_CLAMP_EN_EARLY (1 << 25) 24 #define XUSB_PADCTL_ELPG_PROGRAM_AUX_MUX_LP0_CLAMP_EN (1 << 24) 25 26 #define XUSB_PADCTL_IOPHY_PLL_P0_CTL1 0x040 27 #define XUSB_PADCTL_IOPHY_PLL_P0_CTL1_PLL0_LOCKDET (1 << 19) 28 #define XUSB_PADCTL_IOPHY_PLL_P0_CTL1_REFCLK_SEL_MASK (0xf << 12) 29 #define XUSB_PADCTL_IOPHY_PLL_P0_CTL1_PLL_RST (1 << 1) 30 31 #define XUSB_PADCTL_IOPHY_PLL_P0_CTL2 0x044 32 #define XUSB_PADCTL_IOPHY_PLL_P0_CTL2_REFCLKBUF_EN (1 << 6) 33 #define XUSB_PADCTL_IOPHY_PLL_P0_CTL2_TXCLKREF_EN (1 << 5) 34 #define XUSB_PADCTL_IOPHY_PLL_P0_CTL2_TXCLKREF_SEL (1 << 4) 35 36 #define XUSB_PADCTL_IOPHY_PLL_S0_CTL1 0x138 37 #define XUSB_PADCTL_IOPHY_PLL_S0_CTL1_PLL1_LOCKDET (1 << 27) 38 #define XUSB_PADCTL_IOPHY_PLL_S0_CTL1_PLL1_MODE (1 << 24) 39 #define XUSB_PADCTL_IOPHY_PLL_S0_CTL1_PLL_PWR_OVRD (1 << 3) 40 #define XUSB_PADCTL_IOPHY_PLL_S0_CTL1_PLL_RST (1 << 1) 41 #define XUSB_PADCTL_IOPHY_PLL_S0_CTL1_PLL_IDDQ (1 << 0) 42 43 #define XUSB_PADCTL_IOPHY_MISC_PAD_S0_CTL1 0x148 44 #define XUSB_PADCTL_IOPHY_MISC_PAD_S0_CTL1_IDDQ_OVRD (1 << 1) 45 #define XUSB_PADCTL_IOPHY_MISC_PAD_S0_CTL1_IDDQ (1 << 0) 46 47 enum tegra124_function { 48 TEGRA124_FUNC_SNPS, 49 TEGRA124_FUNC_XUSB, 50 TEGRA124_FUNC_UART, 51 TEGRA124_FUNC_PCIE, 52 TEGRA124_FUNC_USB3, 53 TEGRA124_FUNC_SATA, 54 TEGRA124_FUNC_RSVD, 55 }; 56 57 static const char *const tegra124_functions[] = { 58 "snps", 59 "xusb", 60 "uart", 61 "pcie", 62 "usb3", 63 "sata", 64 "rsvd", 65 }; 66 67 static const unsigned int tegra124_otg_functions[] = { 68 TEGRA124_FUNC_SNPS, 69 TEGRA124_FUNC_XUSB, 70 TEGRA124_FUNC_UART, 71 TEGRA124_FUNC_RSVD, 72 }; 73 74 static const unsigned int tegra124_usb_functions[] = { 75 TEGRA124_FUNC_SNPS, 76 TEGRA124_FUNC_XUSB, 77 }; 78 79 static const unsigned int tegra124_pci_functions[] = { 80 TEGRA124_FUNC_PCIE, 81 TEGRA124_FUNC_USB3, 82 TEGRA124_FUNC_SATA, 83 TEGRA124_FUNC_RSVD, 84 }; 85 86 struct tegra_xusb_padctl_lane { 87 const char *name; 88 89 unsigned int offset; 90 unsigned int shift; 91 unsigned int mask; 92 unsigned int iddq; 93 94 const unsigned int *funcs; 95 unsigned int num_funcs; 96 }; 97 98 #define TEGRA124_LANE(_name, _offset, _shift, _mask, _iddq, _funcs) \ 99 { \ 100 .name = _name, \ 101 .offset = _offset, \ 102 .shift = _shift, \ 103 .mask = _mask, \ 104 .iddq = _iddq, \ 105 .num_funcs = ARRAY_SIZE(tegra124_##_funcs##_functions), \ 106 .funcs = tegra124_##_funcs##_functions, \ 107 } 108 109 static const struct tegra_xusb_padctl_lane tegra124_lanes[] = { 110 TEGRA124_LANE("otg-0", 0x004, 0, 0x3, 0, otg), 111 TEGRA124_LANE("otg-1", 0x004, 2, 0x3, 0, otg), 112 TEGRA124_LANE("otg-2", 0x004, 4, 0x3, 0, otg), 113 TEGRA124_LANE("ulpi-0", 0x004, 12, 0x1, 0, usb), 114 TEGRA124_LANE("hsic-0", 0x004, 14, 0x1, 0, usb), 115 TEGRA124_LANE("hsic-1", 0x004, 15, 0x1, 0, usb), 116 TEGRA124_LANE("pcie-0", 0x134, 16, 0x3, 1, pci), 117 TEGRA124_LANE("pcie-1", 0x134, 18, 0x3, 2, pci), 118 TEGRA124_LANE("pcie-2", 0x134, 20, 0x3, 3, pci), 119 TEGRA124_LANE("pcie-3", 0x134, 22, 0x3, 4, pci), 120 TEGRA124_LANE("pcie-4", 0x134, 24, 0x3, 5, pci), 121 TEGRA124_LANE("sata-0", 0x134, 26, 0x3, 6, pci), 122 }; 123 124 struct tegra_xusb_phy_ops { 125 int (*prepare)(struct tegra_xusb_phy *phy); 126 int (*enable)(struct tegra_xusb_phy *phy); 127 int (*disable)(struct tegra_xusb_phy *phy); 128 int (*unprepare)(struct tegra_xusb_phy *phy); 129 }; 130 131 struct tegra_xusb_phy { 132 const struct tegra_xusb_phy_ops *ops; 133 134 struct tegra_xusb_padctl *padctl; 135 }; 136 137 struct tegra_xusb_padctl_pin { 138 const struct tegra_xusb_padctl_lane *lane; 139 140 unsigned int func; 141 int iddq; 142 }; 143 144 #define MAX_GROUPS 3 145 #define MAX_PINS 6 146 147 struct tegra_xusb_padctl_group { 148 const char *name; 149 150 const char *pins[MAX_PINS]; 151 unsigned int num_pins; 152 153 const char *func; 154 int iddq; 155 }; 156 157 struct tegra_xusb_padctl_config { 158 const char *name; 159 160 struct tegra_xusb_padctl_group groups[MAX_GROUPS]; 161 unsigned int num_groups; 162 }; 163 164 struct tegra_xusb_padctl { 165 struct fdt_resource regs; 166 167 unsigned int enable; 168 169 struct tegra_xusb_phy phys[2]; 170 171 const struct tegra_xusb_padctl_lane *lanes; 172 unsigned int num_lanes; 173 174 const char *const *functions; 175 unsigned int num_functions; 176 177 struct tegra_xusb_padctl_config config; 178 }; 179 180 static inline u32 padctl_readl(struct tegra_xusb_padctl *padctl, 181 unsigned long offset) 182 { 183 return readl(padctl->regs.start + offset); 184 } 185 186 static inline void padctl_writel(struct tegra_xusb_padctl *padctl, 187 u32 value, unsigned long offset) 188 { 189 writel(value, padctl->regs.start + offset); 190 } 191 192 static int tegra_xusb_padctl_enable(struct tegra_xusb_padctl *padctl) 193 { 194 u32 value; 195 196 if (padctl->enable++ > 0) 197 return 0; 198 199 value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM); 200 value &= ~XUSB_PADCTL_ELPG_PROGRAM_AUX_MUX_LP0_CLAMP_EN; 201 padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM); 202 203 udelay(100); 204 205 value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM); 206 value &= ~XUSB_PADCTL_ELPG_PROGRAM_AUX_MUX_LP0_CLAMP_EN_EARLY; 207 padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM); 208 209 udelay(100); 210 211 value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM); 212 value &= ~XUSB_PADCTL_ELPG_PROGRAM_AUX_MUX_LP0_VCORE_DOWN; 213 padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM); 214 215 return 0; 216 } 217 218 static int tegra_xusb_padctl_disable(struct tegra_xusb_padctl *padctl) 219 { 220 u32 value; 221 222 if (padctl->enable == 0) { 223 error("tegra-xusb-padctl: unbalanced enable/disable"); 224 return 0; 225 } 226 227 if (--padctl->enable > 0) 228 return 0; 229 230 value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM); 231 value |= XUSB_PADCTL_ELPG_PROGRAM_AUX_MUX_LP0_VCORE_DOWN; 232 padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM); 233 234 udelay(100); 235 236 value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM); 237 value |= XUSB_PADCTL_ELPG_PROGRAM_AUX_MUX_LP0_CLAMP_EN_EARLY; 238 padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM); 239 240 udelay(100); 241 242 value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM); 243 value |= XUSB_PADCTL_ELPG_PROGRAM_AUX_MUX_LP0_CLAMP_EN; 244 padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM); 245 246 return 0; 247 } 248 249 static int phy_prepare(struct tegra_xusb_phy *phy) 250 { 251 return tegra_xusb_padctl_enable(phy->padctl); 252 } 253 254 static int phy_unprepare(struct tegra_xusb_phy *phy) 255 { 256 return tegra_xusb_padctl_disable(phy->padctl); 257 } 258 259 static int pcie_phy_enable(struct tegra_xusb_phy *phy) 260 { 261 struct tegra_xusb_padctl *padctl = phy->padctl; 262 int err = -ETIMEDOUT; 263 unsigned long start; 264 u32 value; 265 266 value = padctl_readl(padctl, XUSB_PADCTL_IOPHY_PLL_P0_CTL1); 267 value &= ~XUSB_PADCTL_IOPHY_PLL_P0_CTL1_REFCLK_SEL_MASK; 268 padctl_writel(padctl, value, XUSB_PADCTL_IOPHY_PLL_P0_CTL1); 269 270 value = padctl_readl(padctl, XUSB_PADCTL_IOPHY_PLL_P0_CTL2); 271 value |= XUSB_PADCTL_IOPHY_PLL_P0_CTL2_REFCLKBUF_EN | 272 XUSB_PADCTL_IOPHY_PLL_P0_CTL2_TXCLKREF_EN | 273 XUSB_PADCTL_IOPHY_PLL_P0_CTL2_TXCLKREF_SEL; 274 padctl_writel(padctl, value, XUSB_PADCTL_IOPHY_PLL_P0_CTL2); 275 276 value = padctl_readl(padctl, XUSB_PADCTL_IOPHY_PLL_P0_CTL1); 277 value |= XUSB_PADCTL_IOPHY_PLL_P0_CTL1_PLL_RST; 278 padctl_writel(padctl, value, XUSB_PADCTL_IOPHY_PLL_P0_CTL1); 279 280 start = get_timer(0); 281 282 while (get_timer(start) < 50) { 283 value = padctl_readl(padctl, XUSB_PADCTL_IOPHY_PLL_P0_CTL1); 284 if (value & XUSB_PADCTL_IOPHY_PLL_P0_CTL1_PLL0_LOCKDET) { 285 err = 0; 286 break; 287 } 288 } 289 290 return err; 291 } 292 293 static int pcie_phy_disable(struct tegra_xusb_phy *phy) 294 { 295 struct tegra_xusb_padctl *padctl = phy->padctl; 296 u32 value; 297 298 value = padctl_readl(padctl, XUSB_PADCTL_IOPHY_PLL_P0_CTL1); 299 value &= ~XUSB_PADCTL_IOPHY_PLL_P0_CTL1_PLL_RST; 300 padctl_writel(padctl, value, XUSB_PADCTL_IOPHY_PLL_P0_CTL1); 301 302 return 0; 303 } 304 305 static int sata_phy_enable(struct tegra_xusb_phy *phy) 306 { 307 struct tegra_xusb_padctl *padctl = phy->padctl; 308 int err = -ETIMEDOUT; 309 unsigned long start; 310 u32 value; 311 312 value = padctl_readl(padctl, XUSB_PADCTL_IOPHY_MISC_PAD_S0_CTL1); 313 value &= ~XUSB_PADCTL_IOPHY_MISC_PAD_S0_CTL1_IDDQ_OVRD; 314 value &= ~XUSB_PADCTL_IOPHY_MISC_PAD_S0_CTL1_IDDQ; 315 padctl_writel(padctl, value, XUSB_PADCTL_IOPHY_MISC_PAD_S0_CTL1); 316 317 value = padctl_readl(padctl, XUSB_PADCTL_IOPHY_PLL_S0_CTL1); 318 value &= ~XUSB_PADCTL_IOPHY_PLL_S0_CTL1_PLL_PWR_OVRD; 319 value &= ~XUSB_PADCTL_IOPHY_PLL_S0_CTL1_PLL_IDDQ; 320 padctl_writel(padctl, value, XUSB_PADCTL_IOPHY_PLL_S0_CTL1); 321 322 value = padctl_readl(padctl, XUSB_PADCTL_IOPHY_PLL_S0_CTL1); 323 value |= XUSB_PADCTL_IOPHY_PLL_S0_CTL1_PLL1_MODE; 324 padctl_writel(padctl, value, XUSB_PADCTL_IOPHY_PLL_S0_CTL1); 325 326 value = padctl_readl(padctl, XUSB_PADCTL_IOPHY_PLL_S0_CTL1); 327 value |= XUSB_PADCTL_IOPHY_PLL_S0_CTL1_PLL_RST; 328 padctl_writel(padctl, value, XUSB_PADCTL_IOPHY_PLL_S0_CTL1); 329 330 start = get_timer(0); 331 332 while (get_timer(start) < 50) { 333 value = padctl_readl(padctl, XUSB_PADCTL_IOPHY_PLL_S0_CTL1); 334 if (value & XUSB_PADCTL_IOPHY_PLL_S0_CTL1_PLL1_LOCKDET) { 335 err = 0; 336 break; 337 } 338 } 339 340 return err; 341 } 342 343 static int sata_phy_disable(struct tegra_xusb_phy *phy) 344 { 345 struct tegra_xusb_padctl *padctl = phy->padctl; 346 u32 value; 347 348 value = padctl_readl(padctl, XUSB_PADCTL_IOPHY_PLL_S0_CTL1); 349 value &= ~XUSB_PADCTL_IOPHY_PLL_S0_CTL1_PLL_RST; 350 padctl_writel(padctl, value, XUSB_PADCTL_IOPHY_PLL_S0_CTL1); 351 352 value = padctl_readl(padctl, XUSB_PADCTL_IOPHY_PLL_S0_CTL1); 353 value &= ~XUSB_PADCTL_IOPHY_PLL_S0_CTL1_PLL1_MODE; 354 padctl_writel(padctl, value, XUSB_PADCTL_IOPHY_PLL_S0_CTL1); 355 356 value = padctl_readl(padctl, XUSB_PADCTL_IOPHY_PLL_S0_CTL1); 357 value |= XUSB_PADCTL_IOPHY_PLL_S0_CTL1_PLL_PWR_OVRD; 358 value |= XUSB_PADCTL_IOPHY_PLL_S0_CTL1_PLL_IDDQ; 359 padctl_writel(padctl, value, XUSB_PADCTL_IOPHY_PLL_S0_CTL1); 360 361 value = padctl_readl(padctl, XUSB_PADCTL_IOPHY_MISC_PAD_S0_CTL1); 362 value |= ~XUSB_PADCTL_IOPHY_MISC_PAD_S0_CTL1_IDDQ_OVRD; 363 value |= ~XUSB_PADCTL_IOPHY_MISC_PAD_S0_CTL1_IDDQ; 364 padctl_writel(padctl, value, XUSB_PADCTL_IOPHY_MISC_PAD_S0_CTL1); 365 366 return 0; 367 } 368 369 static const struct tegra_xusb_phy_ops pcie_phy_ops = { 370 .prepare = phy_prepare, 371 .enable = pcie_phy_enable, 372 .disable = pcie_phy_disable, 373 .unprepare = phy_unprepare, 374 }; 375 376 static const struct tegra_xusb_phy_ops sata_phy_ops = { 377 .prepare = phy_prepare, 378 .enable = sata_phy_enable, 379 .disable = sata_phy_disable, 380 .unprepare = phy_unprepare, 381 }; 382 383 static struct tegra_xusb_padctl *padctl = &(struct tegra_xusb_padctl) { 384 .phys = { 385 [0] = { 386 .ops = &pcie_phy_ops, 387 }, 388 [1] = { 389 .ops = &sata_phy_ops, 390 }, 391 }, 392 }; 393 394 static const struct tegra_xusb_padctl_lane * 395 tegra_xusb_padctl_find_lane(struct tegra_xusb_padctl *padctl, const char *name) 396 { 397 unsigned int i; 398 399 for (i = 0; i < padctl->num_lanes; i++) 400 if (strcmp(name, padctl->lanes[i].name) == 0) 401 return &padctl->lanes[i]; 402 403 return NULL; 404 } 405 406 static int 407 tegra_xusb_padctl_group_parse_dt(struct tegra_xusb_padctl *padctl, 408 struct tegra_xusb_padctl_group *group, 409 const void *fdt, int node) 410 { 411 unsigned int i; 412 int len, err; 413 414 group->name = fdt_get_name(fdt, node, &len); 415 416 len = fdt_count_strings(fdt, node, "nvidia,lanes"); 417 if (len < 0) { 418 error("tegra-xusb-padctl: failed to parse \"nvidia,lanes\" property"); 419 return -EINVAL; 420 } 421 422 group->num_pins = len; 423 424 for (i = 0; i < group->num_pins; i++) { 425 err = fdt_get_string_index(fdt, node, "nvidia,lanes", i, 426 &group->pins[i]); 427 if (err < 0) { 428 error("tegra-xusb-padctl: failed to read string from \"nvidia,lanes\" property"); 429 return -EINVAL; 430 } 431 } 432 433 group->num_pins = len; 434 435 err = fdt_get_string(fdt, node, "nvidia,function", &group->func); 436 if (err < 0) { 437 error("tegra-xusb-padctl: failed to parse \"nvidia,func\" property"); 438 return -EINVAL; 439 } 440 441 group->iddq = fdtdec_get_int(fdt, node, "nvidia,iddq", -1); 442 443 return 0; 444 } 445 446 static int tegra_xusb_padctl_find_function(struct tegra_xusb_padctl *padctl, 447 const char *name) 448 { 449 unsigned int i; 450 451 for (i = 0; i < padctl->num_functions; i++) 452 if (strcmp(name, padctl->functions[i]) == 0) 453 return i; 454 455 return -ENOENT; 456 } 457 458 static int 459 tegra_xusb_padctl_lane_find_function(struct tegra_xusb_padctl *padctl, 460 const struct tegra_xusb_padctl_lane *lane, 461 const char *name) 462 { 463 unsigned int i; 464 int func; 465 466 func = tegra_xusb_padctl_find_function(padctl, name); 467 if (func < 0) 468 return func; 469 470 for (i = 0; i < lane->num_funcs; i++) 471 if (lane->funcs[i] == func) 472 return i; 473 474 return -ENOENT; 475 } 476 477 static int 478 tegra_xusb_padctl_group_apply(struct tegra_xusb_padctl *padctl, 479 const struct tegra_xusb_padctl_group *group) 480 { 481 unsigned int i; 482 483 for (i = 0; i < group->num_pins; i++) { 484 const struct tegra_xusb_padctl_lane *lane; 485 unsigned int func; 486 u32 value; 487 488 lane = tegra_xusb_padctl_find_lane(padctl, group->pins[i]); 489 if (!lane) { 490 error("tegra-xusb-padctl: no lane for pin %s", 491 group->pins[i]); 492 continue; 493 } 494 495 func = tegra_xusb_padctl_lane_find_function(padctl, lane, 496 group->func); 497 if (func < 0) { 498 error("tegra-xusb-padctl: function %s invalid for lane %s: %d", 499 group->func, lane->name, func); 500 continue; 501 } 502 503 value = padctl_readl(padctl, lane->offset); 504 505 /* set pin function */ 506 value &= ~(lane->mask << lane->shift); 507 value |= func << lane->shift; 508 509 /* 510 * Set IDDQ if supported on the lane and specified in the 511 * configuration. 512 */ 513 if (lane->iddq > 0 && group->iddq >= 0) { 514 if (group->iddq != 0) 515 value &= ~(1 << lane->iddq); 516 else 517 value |= 1 << lane->iddq; 518 } 519 520 padctl_writel(padctl, value, lane->offset); 521 } 522 523 return 0; 524 } 525 526 static int 527 tegra_xusb_padctl_config_apply(struct tegra_xusb_padctl *padctl, 528 struct tegra_xusb_padctl_config *config) 529 { 530 unsigned int i; 531 532 for (i = 0; i < config->num_groups; i++) { 533 const struct tegra_xusb_padctl_group *group; 534 int err; 535 536 group = &config->groups[i]; 537 538 err = tegra_xusb_padctl_group_apply(padctl, group); 539 if (err < 0) { 540 error("tegra-xusb-padctl: failed to apply group %s: %d", 541 group->name, err); 542 continue; 543 } 544 } 545 546 return 0; 547 } 548 549 static int 550 tegra_xusb_padctl_config_parse_dt(struct tegra_xusb_padctl *padctl, 551 struct tegra_xusb_padctl_config *config, 552 const void *fdt, int node) 553 { 554 int subnode; 555 556 config->name = fdt_get_name(fdt, node, NULL); 557 558 fdt_for_each_subnode(fdt, subnode, node) { 559 struct tegra_xusb_padctl_group *group; 560 int err; 561 562 group = &config->groups[config->num_groups]; 563 564 err = tegra_xusb_padctl_group_parse_dt(padctl, group, fdt, 565 subnode); 566 if (err < 0) { 567 error("tegra-xusb-padctl: failed to parse group %s", 568 group->name); 569 return err; 570 } 571 572 config->num_groups++; 573 } 574 575 return 0; 576 } 577 578 static int tegra_xusb_padctl_parse_dt(struct tegra_xusb_padctl *padctl, 579 const void *fdt, int node) 580 { 581 int subnode, err; 582 583 err = fdt_get_resource(fdt, node, "reg", 0, &padctl->regs); 584 if (err < 0) { 585 error("tegra-xusb-padctl: registers not found"); 586 return err; 587 } 588 589 fdt_for_each_subnode(fdt, subnode, node) { 590 struct tegra_xusb_padctl_config *config = &padctl->config; 591 592 err = tegra_xusb_padctl_config_parse_dt(padctl, config, fdt, 593 subnode); 594 if (err < 0) { 595 error("tegra-xusb-padctl: failed to parse entry %s: %d", 596 config->name, err); 597 continue; 598 } 599 } 600 601 return 0; 602 } 603 604 static int process_nodes(const void *fdt, int nodes[], unsigned int count) 605 { 606 unsigned int i; 607 608 for (i = 0; i < count; i++) { 609 enum fdt_compat_id id; 610 int err; 611 612 if (!fdtdec_get_is_enabled(fdt, nodes[i])) 613 continue; 614 615 id = fdtdec_lookup(fdt, nodes[i]); 616 switch (id) { 617 case COMPAT_NVIDIA_TEGRA124_XUSB_PADCTL: 618 break; 619 620 default: 621 error("tegra-xusb-padctl: unsupported compatible: %s", 622 fdtdec_get_compatible(id)); 623 continue; 624 } 625 626 padctl->num_lanes = ARRAY_SIZE(tegra124_lanes); 627 padctl->lanes = tegra124_lanes; 628 629 padctl->num_functions = ARRAY_SIZE(tegra124_functions); 630 padctl->functions = tegra124_functions; 631 632 err = tegra_xusb_padctl_parse_dt(padctl, fdt, nodes[i]); 633 if (err < 0) { 634 error("tegra-xusb-padctl: failed to parse DT: %d", 635 err); 636 continue; 637 } 638 639 /* deassert XUSB padctl reset */ 640 reset_set_enable(PERIPH_ID_XUSB_PADCTL, 0); 641 642 err = tegra_xusb_padctl_config_apply(padctl, &padctl->config); 643 if (err < 0) { 644 error("tegra-xusb-padctl: failed to apply pinmux: %d", 645 err); 646 continue; 647 } 648 649 /* only a single instance is supported */ 650 break; 651 } 652 653 return 0; 654 } 655 656 struct tegra_xusb_phy *tegra_xusb_phy_get(unsigned int type) 657 { 658 struct tegra_xusb_phy *phy = NULL; 659 660 switch (type) { 661 case TEGRA_XUSB_PADCTL_PCIE: 662 phy = &padctl->phys[0]; 663 phy->padctl = padctl; 664 break; 665 666 case TEGRA_XUSB_PADCTL_SATA: 667 phy = &padctl->phys[1]; 668 phy->padctl = padctl; 669 break; 670 } 671 672 return phy; 673 } 674 675 int tegra_xusb_phy_prepare(struct tegra_xusb_phy *phy) 676 { 677 if (phy && phy->ops && phy->ops->prepare) 678 return phy->ops->prepare(phy); 679 680 return phy ? -ENOSYS : -EINVAL; 681 } 682 683 int tegra_xusb_phy_enable(struct tegra_xusb_phy *phy) 684 { 685 if (phy && phy->ops && phy->ops->enable) 686 return phy->ops->enable(phy); 687 688 return phy ? -ENOSYS : -EINVAL; 689 } 690 691 int tegra_xusb_phy_disable(struct tegra_xusb_phy *phy) 692 { 693 if (phy && phy->ops && phy->ops->disable) 694 return phy->ops->disable(phy); 695 696 return phy ? -ENOSYS : -EINVAL; 697 } 698 699 int tegra_xusb_phy_unprepare(struct tegra_xusb_phy *phy) 700 { 701 if (phy && phy->ops && phy->ops->unprepare) 702 return phy->ops->unprepare(phy); 703 704 return phy ? -ENOSYS : -EINVAL; 705 } 706 707 void tegra_xusb_padctl_init(const void *fdt) 708 { 709 int count, nodes[1]; 710 711 count = fdtdec_find_aliases_for_id(fdt, "padctl", 712 COMPAT_NVIDIA_TEGRA124_XUSB_PADCTL, 713 nodes, ARRAY_SIZE(nodes)); 714 if (process_nodes(fdt, nodes, count)) 715 return; 716 } 717