1 /* 2 * (C) Copyright 2013 3 * NVIDIA Corporation <www.nvidia.com> 4 * 5 * SPDX-License-Identifier: GPL-2.0+ 6 */ 7 8 /* Tegra124 high-level function multiplexing */ 9 10 #include <common.h> 11 #include <asm/arch/clock.h> 12 #include <asm/arch/funcmux.h> 13 #include <asm/arch/pinmux.h> 14 15 int funcmux_select(enum periph_id id, int config) 16 { 17 int bad_config = config != FUNCMUX_DEFAULT; 18 19 switch (id) { 20 case PERIPH_ID_UART4: 21 switch (config) { 22 case FUNCMUX_UART4_GPIO: /* TXD,RXD,CTS,RTS */ 23 pinmux_set_func(PMUX_PINGRP_PJ7, PMUX_FUNC_UARTD); 24 pinmux_set_func(PMUX_PINGRP_PB0, PMUX_FUNC_UARTD); 25 pinmux_set_func(PMUX_PINGRP_PB1, PMUX_FUNC_UARTD); 26 pinmux_set_func(PMUX_PINGRP_PK7, PMUX_FUNC_UARTD); 27 28 pinmux_set_io(PMUX_PINGRP_PJ7, PMUX_PIN_OUTPUT); 29 pinmux_set_io(PMUX_PINGRP_PB0, PMUX_PIN_INPUT); 30 pinmux_set_io(PMUX_PINGRP_PB1, PMUX_PIN_INPUT); 31 pinmux_set_io(PMUX_PINGRP_PK7, PMUX_PIN_OUTPUT); 32 33 pinmux_tristate_disable(PMUX_PINGRP_PJ7); 34 pinmux_tristate_disable(PMUX_PINGRP_PB0); 35 pinmux_tristate_disable(PMUX_PINGRP_PB1); 36 pinmux_tristate_disable(PMUX_PINGRP_PK7); 37 break; 38 } 39 break; 40 41 case PERIPH_ID_UART1: 42 switch (config) { 43 case FUNCMUX_UART1_KBC: 44 pinmux_set_func(PMUX_PINGRP_KB_ROW9_PS1, 45 PMUX_FUNC_UARTA); 46 pinmux_set_func(PMUX_PINGRP_KB_ROW10_PS2, 47 PMUX_FUNC_UARTA); 48 49 pinmux_set_io(PMUX_PINGRP_KB_ROW9_PS1, PMUX_PIN_OUTPUT); 50 pinmux_set_io(PMUX_PINGRP_KB_ROW10_PS2, PMUX_PIN_INPUT); 51 52 pinmux_tristate_disable(PMUX_PINGRP_KB_ROW9_PS1); 53 pinmux_tristate_disable(PMUX_PINGRP_KB_ROW10_PS2); 54 break; 55 } 56 break; 57 58 /* Add other periph IDs here as needed */ 59 60 default: 61 debug("%s: invalid periph_id %d", __func__, id); 62 return -1; 63 } 64 65 if (bad_config) { 66 debug("%s: invalid config %d for periph_id %d", __func__, 67 config, id); 68 return -1; 69 } 70 return 0; 71 } 72