1*09f455dcSMasahiro Yamada /* 2*09f455dcSMasahiro Yamada * (C) Copyright 2013 3*09f455dcSMasahiro Yamada * NVIDIA Corporation <www.nvidia.com> 4*09f455dcSMasahiro Yamada * 5*09f455dcSMasahiro Yamada * SPDX-License-Identifier: GPL-2.0+ 6*09f455dcSMasahiro Yamada */ 7*09f455dcSMasahiro Yamada 8*09f455dcSMasahiro Yamada /* Tegra124 high-level function multiplexing */ 9*09f455dcSMasahiro Yamada 10*09f455dcSMasahiro Yamada #include <common.h> 11*09f455dcSMasahiro Yamada #include <asm/arch/clock.h> 12*09f455dcSMasahiro Yamada #include <asm/arch/funcmux.h> 13*09f455dcSMasahiro Yamada #include <asm/arch/pinmux.h> 14*09f455dcSMasahiro Yamada 15*09f455dcSMasahiro Yamada int funcmux_select(enum periph_id id, int config) 16*09f455dcSMasahiro Yamada { 17*09f455dcSMasahiro Yamada int bad_config = config != FUNCMUX_DEFAULT; 18*09f455dcSMasahiro Yamada 19*09f455dcSMasahiro Yamada switch (id) { 20*09f455dcSMasahiro Yamada case PERIPH_ID_UART4: 21*09f455dcSMasahiro Yamada switch (config) { 22*09f455dcSMasahiro Yamada case FUNCMUX_UART4_GPIO: /* TXD,RXD,CTS,RTS */ 23*09f455dcSMasahiro Yamada pinmux_set_func(PMUX_PINGRP_PJ7, PMUX_FUNC_UARTD); 24*09f455dcSMasahiro Yamada pinmux_set_func(PMUX_PINGRP_PB0, PMUX_FUNC_UARTD); 25*09f455dcSMasahiro Yamada pinmux_set_func(PMUX_PINGRP_PB1, PMUX_FUNC_UARTD); 26*09f455dcSMasahiro Yamada pinmux_set_func(PMUX_PINGRP_PK7, PMUX_FUNC_UARTD); 27*09f455dcSMasahiro Yamada 28*09f455dcSMasahiro Yamada pinmux_set_io(PMUX_PINGRP_PJ7, PMUX_PIN_OUTPUT); 29*09f455dcSMasahiro Yamada pinmux_set_io(PMUX_PINGRP_PB0, PMUX_PIN_INPUT); 30*09f455dcSMasahiro Yamada pinmux_set_io(PMUX_PINGRP_PB1, PMUX_PIN_INPUT); 31*09f455dcSMasahiro Yamada pinmux_set_io(PMUX_PINGRP_PK7, PMUX_PIN_OUTPUT); 32*09f455dcSMasahiro Yamada 33*09f455dcSMasahiro Yamada pinmux_tristate_disable(PMUX_PINGRP_PJ7); 34*09f455dcSMasahiro Yamada pinmux_tristate_disable(PMUX_PINGRP_PB0); 35*09f455dcSMasahiro Yamada pinmux_tristate_disable(PMUX_PINGRP_PB1); 36*09f455dcSMasahiro Yamada pinmux_tristate_disable(PMUX_PINGRP_PK7); 37*09f455dcSMasahiro Yamada break; 38*09f455dcSMasahiro Yamada } 39*09f455dcSMasahiro Yamada break; 40*09f455dcSMasahiro Yamada 41*09f455dcSMasahiro Yamada case PERIPH_ID_UART1: 42*09f455dcSMasahiro Yamada switch (config) { 43*09f455dcSMasahiro Yamada case FUNCMUX_UART1_KBC: 44*09f455dcSMasahiro Yamada pinmux_set_func(PMUX_PINGRP_KB_ROW9_PS1, 45*09f455dcSMasahiro Yamada PMUX_FUNC_UARTA); 46*09f455dcSMasahiro Yamada pinmux_set_func(PMUX_PINGRP_KB_ROW10_PS2, 47*09f455dcSMasahiro Yamada PMUX_FUNC_UARTA); 48*09f455dcSMasahiro Yamada 49*09f455dcSMasahiro Yamada pinmux_set_io(PMUX_PINGRP_KB_ROW9_PS1, PMUX_PIN_OUTPUT); 50*09f455dcSMasahiro Yamada pinmux_set_io(PMUX_PINGRP_KB_ROW10_PS2, PMUX_PIN_INPUT); 51*09f455dcSMasahiro Yamada 52*09f455dcSMasahiro Yamada pinmux_tristate_disable(PMUX_PINGRP_KB_ROW9_PS1); 53*09f455dcSMasahiro Yamada pinmux_tristate_disable(PMUX_PINGRP_KB_ROW10_PS2); 54*09f455dcSMasahiro Yamada break; 55*09f455dcSMasahiro Yamada } 56*09f455dcSMasahiro Yamada break; 57*09f455dcSMasahiro Yamada 58*09f455dcSMasahiro Yamada /* Add other periph IDs here as needed */ 59*09f455dcSMasahiro Yamada 60*09f455dcSMasahiro Yamada default: 61*09f455dcSMasahiro Yamada debug("%s: invalid periph_id %d", __func__, id); 62*09f455dcSMasahiro Yamada return -1; 63*09f455dcSMasahiro Yamada } 64*09f455dcSMasahiro Yamada 65*09f455dcSMasahiro Yamada if (bad_config) { 66*09f455dcSMasahiro Yamada debug("%s: invalid config %d for periph_id %d", __func__, 67*09f455dcSMasahiro Yamada config, id); 68*09f455dcSMasahiro Yamada return -1; 69*09f455dcSMasahiro Yamada } 70*09f455dcSMasahiro Yamada return 0; 71*09f455dcSMasahiro Yamada } 72