1*83d290c5STom Rini // SPDX-License-Identifier: GPL-2.0+
209f455dcSMasahiro Yamada /*
309f455dcSMasahiro Yamada * (C) Copyright 2013
409f455dcSMasahiro Yamada * NVIDIA Corporation <www.nvidia.com>
509f455dcSMasahiro Yamada */
609f455dcSMasahiro Yamada
709f455dcSMasahiro Yamada /* Tegra124 high-level function multiplexing */
809f455dcSMasahiro Yamada
909f455dcSMasahiro Yamada #include <common.h>
1009f455dcSMasahiro Yamada #include <asm/arch/clock.h>
1109f455dcSMasahiro Yamada #include <asm/arch/funcmux.h>
1209f455dcSMasahiro Yamada #include <asm/arch/pinmux.h>
1309f455dcSMasahiro Yamada
funcmux_select(enum periph_id id,int config)1409f455dcSMasahiro Yamada int funcmux_select(enum periph_id id, int config)
1509f455dcSMasahiro Yamada {
1609f455dcSMasahiro Yamada int bad_config = config != FUNCMUX_DEFAULT;
1709f455dcSMasahiro Yamada
1809f455dcSMasahiro Yamada switch (id) {
1909f455dcSMasahiro Yamada case PERIPH_ID_UART4:
2009f455dcSMasahiro Yamada switch (config) {
2109f455dcSMasahiro Yamada case FUNCMUX_UART4_GPIO: /* TXD,RXD,CTS,RTS */
2209f455dcSMasahiro Yamada pinmux_set_func(PMUX_PINGRP_PJ7, PMUX_FUNC_UARTD);
2309f455dcSMasahiro Yamada pinmux_set_func(PMUX_PINGRP_PB0, PMUX_FUNC_UARTD);
2409f455dcSMasahiro Yamada pinmux_set_func(PMUX_PINGRP_PB1, PMUX_FUNC_UARTD);
2509f455dcSMasahiro Yamada pinmux_set_func(PMUX_PINGRP_PK7, PMUX_FUNC_UARTD);
2609f455dcSMasahiro Yamada
2709f455dcSMasahiro Yamada pinmux_set_io(PMUX_PINGRP_PJ7, PMUX_PIN_OUTPUT);
2809f455dcSMasahiro Yamada pinmux_set_io(PMUX_PINGRP_PB0, PMUX_PIN_INPUT);
2909f455dcSMasahiro Yamada pinmux_set_io(PMUX_PINGRP_PB1, PMUX_PIN_INPUT);
3009f455dcSMasahiro Yamada pinmux_set_io(PMUX_PINGRP_PK7, PMUX_PIN_OUTPUT);
3109f455dcSMasahiro Yamada
3209f455dcSMasahiro Yamada pinmux_tristate_disable(PMUX_PINGRP_PJ7);
3309f455dcSMasahiro Yamada pinmux_tristate_disable(PMUX_PINGRP_PB0);
3409f455dcSMasahiro Yamada pinmux_tristate_disable(PMUX_PINGRP_PB1);
3509f455dcSMasahiro Yamada pinmux_tristate_disable(PMUX_PINGRP_PK7);
3609f455dcSMasahiro Yamada break;
3709f455dcSMasahiro Yamada }
3809f455dcSMasahiro Yamada break;
3909f455dcSMasahiro Yamada
4009f455dcSMasahiro Yamada case PERIPH_ID_UART1:
4109f455dcSMasahiro Yamada switch (config) {
4209f455dcSMasahiro Yamada case FUNCMUX_UART1_KBC:
4309f455dcSMasahiro Yamada pinmux_set_func(PMUX_PINGRP_KB_ROW9_PS1,
4409f455dcSMasahiro Yamada PMUX_FUNC_UARTA);
4509f455dcSMasahiro Yamada pinmux_set_func(PMUX_PINGRP_KB_ROW10_PS2,
4609f455dcSMasahiro Yamada PMUX_FUNC_UARTA);
4709f455dcSMasahiro Yamada
4809f455dcSMasahiro Yamada pinmux_set_io(PMUX_PINGRP_KB_ROW9_PS1, PMUX_PIN_OUTPUT);
4909f455dcSMasahiro Yamada pinmux_set_io(PMUX_PINGRP_KB_ROW10_PS2, PMUX_PIN_INPUT);
5009f455dcSMasahiro Yamada
5109f455dcSMasahiro Yamada pinmux_tristate_disable(PMUX_PINGRP_KB_ROW9_PS1);
5209f455dcSMasahiro Yamada pinmux_tristate_disable(PMUX_PINGRP_KB_ROW10_PS2);
5309f455dcSMasahiro Yamada break;
5409f455dcSMasahiro Yamada }
5509f455dcSMasahiro Yamada break;
5609f455dcSMasahiro Yamada
5709f455dcSMasahiro Yamada /* Add other periph IDs here as needed */
5809f455dcSMasahiro Yamada
5909f455dcSMasahiro Yamada default:
6009f455dcSMasahiro Yamada debug("%s: invalid periph_id %d", __func__, id);
6109f455dcSMasahiro Yamada return -1;
6209f455dcSMasahiro Yamada }
6309f455dcSMasahiro Yamada
6409f455dcSMasahiro Yamada if (bad_config) {
6509f455dcSMasahiro Yamada debug("%s: invalid config %d for periph_id %d", __func__,
6609f455dcSMasahiro Yamada config, id);
6709f455dcSMasahiro Yamada return -1;
6809f455dcSMasahiro Yamada }
6909f455dcSMasahiro Yamada return 0;
7009f455dcSMasahiro Yamada }
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