1 /* 2 * (C) Copyright 2013 3 * NVIDIA Corporation <www.nvidia.com> 4 * 5 * SPDX-License-Identifier: GPL-2.0+ 6 */ 7 8 #include <common.h> 9 #include <asm/io.h> 10 #include <asm/arch/ahb.h> 11 #include <asm/arch/clock.h> 12 #include <asm/arch/flow.h> 13 #include <asm/arch/pinmux.h> 14 #include <asm/arch/tegra.h> 15 #include <asm/arch-tegra/clk_rst.h> 16 #include <asm/arch-tegra/pmc.h> 17 #include <asm/arch-tegra/ap.h> 18 #include "../cpu.h" 19 20 /* Tegra124-specific CPU init code */ 21 22 static void enable_cpu_power_rail(void) 23 { 24 struct pmc_ctlr *pmc = (struct pmc_ctlr *)NV_PA_PMC_BASE; 25 26 debug("enable_cpu_power_rail entry\n"); 27 28 /* un-tristate PWR_I2C SCL/SDA, rest of the defaults are correct */ 29 pinmux_tristate_disable(PMUX_PINGRP_PWR_I2C_SCL_PZ6); 30 pinmux_tristate_disable(PMUX_PINGRP_PWR_I2C_SDA_PZ7); 31 32 pmic_enable_cpu_vdd(); 33 34 /* 35 * Set CPUPWRGOOD_TIMER - APB clock is 1/2 of SCLK (102MHz), 36 * set it for 5ms as per SysEng (102MHz*5ms = 510000 (7C830h). 37 */ 38 writel(0x7C830, &pmc->pmc_cpupwrgood_timer); 39 40 /* Set polarity to 0 (normal) and enable CPUPWRREQ_OE */ 41 clrbits_le32(&pmc->pmc_cntrl, CPUPWRREQ_POL); 42 setbits_le32(&pmc->pmc_cntrl, CPUPWRREQ_OE); 43 } 44 45 static void enable_cpu_clocks(void) 46 { 47 struct clk_rst_ctlr *clkrst = (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE; 48 u32 reg; 49 50 debug("enable_cpu_clocks entry\n"); 51 52 /* Wait for PLL-X to lock */ 53 do { 54 reg = readl(&clkrst->crc_pll_simple[SIMPLE_PLLX].pll_base); 55 debug("%s: PLLX base = 0x%08X\n", __func__, reg); 56 } while ((reg & PLL_LOCK_MASK) == 0); 57 58 debug("%s: PLLX locked, delay for stable clocks\n", __func__); 59 /* Wait until all clocks are stable */ 60 udelay(PLL_STABILIZATION_DELAY); 61 62 debug("%s: Setting CCLK_BURST and DIVIDER\n", __func__); 63 writel(CCLK_BURST_POLICY, &clkrst->crc_cclk_brst_pol); 64 writel(SUPER_CCLK_DIVIDER, &clkrst->crc_super_cclk_div); 65 66 debug("%s: Enabling clock to all CPUs\n", __func__); 67 /* Enable the clock to all CPUs */ 68 reg = CLR_CPU3_CLK_STP | CLR_CPU2_CLK_STP | CLR_CPU1_CLK_STP | 69 CLR_CPU0_CLK_STP; 70 writel(reg, &clkrst->crc_clk_cpu_cmplx_clr); 71 72 debug("%s: Enabling main CPU complex clocks\n", __func__); 73 /* Always enable the main CPU complex clocks */ 74 clock_enable(PERIPH_ID_CPU); 75 clock_enable(PERIPH_ID_CPULP); 76 clock_enable(PERIPH_ID_CPUG); 77 78 debug("%s: Done\n", __func__); 79 } 80 81 static void remove_cpu_resets(void) 82 { 83 struct clk_rst_ctlr *clkrst = (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE; 84 u32 reg; 85 86 debug("remove_cpu_resets entry\n"); 87 88 /* Take the slow and fast partitions out of reset */ 89 reg = CLR_NONCPURESET; 90 writel(reg, &clkrst->crc_rst_cpulp_cmplx_clr); 91 writel(reg, &clkrst->crc_rst_cpug_cmplx_clr); 92 93 /* Clear the SW-controlled reset of the slow cluster */ 94 reg = CLR_CPURESET0 | CLR_DBGRESET0 | CLR_CORERESET0 | CLR_CXRESET0 | 95 CLR_L2RESET | CLR_PRESETDBG; 96 writel(reg, &clkrst->crc_rst_cpulp_cmplx_clr); 97 98 /* Clear the SW-controlled reset of the fast cluster */ 99 reg = CLR_CPURESET0 | CLR_DBGRESET0 | CLR_CORERESET0 | CLR_CXRESET0 | 100 CLR_CPURESET1 | CLR_DBGRESET1 | CLR_CORERESET1 | CLR_CXRESET1 | 101 CLR_CPURESET2 | CLR_DBGRESET2 | CLR_CORERESET2 | CLR_CXRESET2 | 102 CLR_CPURESET3 | CLR_DBGRESET3 | CLR_CORERESET3 | CLR_CXRESET3 | 103 CLR_L2RESET | CLR_PRESETDBG; 104 writel(reg, &clkrst->crc_rst_cpug_cmplx_clr); 105 } 106 107 /** 108 * The Tegra124 requires some special clock initialization, including setting up 109 * the DVC I2C, turning on MSELECT and selecting the G CPU cluster 110 */ 111 void tegra124_init_clocks(void) 112 { 113 struct flow_ctlr *flow = (struct flow_ctlr *)NV_PA_FLOW_BASE; 114 struct pmc_ctlr *pmc = (struct pmc_ctlr *)NV_PA_PMC_BASE; 115 struct clk_rst_ctlr *clkrst = 116 (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE; 117 u32 val; 118 119 debug("tegra124_init_clocks entry\n"); 120 121 /* Set active CPU cluster to G */ 122 clrbits_le32(&flow->cluster_control, 1); 123 124 /* Change the oscillator drive strength */ 125 val = readl(&clkrst->crc_osc_ctrl); 126 val &= ~OSC_XOFS_MASK; 127 val |= (OSC_DRIVE_STRENGTH << OSC_XOFS_SHIFT); 128 writel(val, &clkrst->crc_osc_ctrl); 129 130 /* Update same value in PMC_OSC_EDPD_OVER XOFS field for warmboot */ 131 val = readl(&pmc->pmc_osc_edpd_over); 132 val &= ~PMC_XOFS_MASK; 133 val |= (OSC_DRIVE_STRENGTH << PMC_XOFS_SHIFT); 134 writel(val, &pmc->pmc_osc_edpd_over); 135 136 /* Set HOLD_CKE_LOW_EN to 1 */ 137 setbits_le32(&pmc->pmc_cntrl2, HOLD_CKE_LOW_EN); 138 139 debug("Setting up PLLX\n"); 140 init_pllx(); 141 142 val = (1 << CLK_SYS_RATE_AHB_RATE_SHIFT); 143 writel(val, &clkrst->crc_clk_sys_rate); 144 145 /* Enable clocks to required peripherals. TBD - minimize this list */ 146 debug("Enabling clocks\n"); 147 148 clock_set_enable(PERIPH_ID_CACHE2, 1); 149 clock_set_enable(PERIPH_ID_GPIO, 1); 150 clock_set_enable(PERIPH_ID_TMR, 1); 151 clock_set_enable(PERIPH_ID_CPU, 1); 152 clock_set_enable(PERIPH_ID_EMC, 1); 153 clock_set_enable(PERIPH_ID_I2C5, 1); 154 clock_set_enable(PERIPH_ID_APBDMA, 1); 155 clock_set_enable(PERIPH_ID_MEM, 1); 156 clock_set_enable(PERIPH_ID_CORESIGHT, 1); 157 clock_set_enable(PERIPH_ID_MSELECT, 1); 158 clock_set_enable(PERIPH_ID_DVFS, 1); 159 160 /* 161 * Set MSELECT clock source as PLLP (00), and ask for a clock 162 * divider that would set the MSELECT clock at 102MHz for a 163 * PLLP base of 408MHz. 164 */ 165 clock_ll_set_source_divisor(PERIPH_ID_MSELECT, 0, 166 CLK_DIVIDER(NVBL_PLLP_KHZ, 102000)); 167 168 /* Give clock time to stabilize */ 169 udelay(IO_STABILIZATION_DELAY); 170 171 /* I2C5 (DVC) gets CLK_M and a divisor of 17 */ 172 clock_ll_set_source_divisor(PERIPH_ID_I2C5, 3, 16); 173 174 /* Give clock time to stabilize */ 175 udelay(IO_STABILIZATION_DELAY); 176 177 /* Take required peripherals out of reset */ 178 debug("Taking periphs out of reset\n"); 179 reset_set_enable(PERIPH_ID_CACHE2, 0); 180 reset_set_enable(PERIPH_ID_GPIO, 0); 181 reset_set_enable(PERIPH_ID_TMR, 0); 182 reset_set_enable(PERIPH_ID_COP, 0); 183 reset_set_enable(PERIPH_ID_EMC, 0); 184 reset_set_enable(PERIPH_ID_I2C5, 0); 185 reset_set_enable(PERIPH_ID_APBDMA, 0); 186 reset_set_enable(PERIPH_ID_MEM, 0); 187 reset_set_enable(PERIPH_ID_CORESIGHT, 0); 188 reset_set_enable(PERIPH_ID_MSELECT, 0); 189 reset_set_enable(PERIPH_ID_DVFS, 0); 190 191 debug("tegra124_init_clocks exit\n"); 192 } 193 194 static bool is_partition_powered(u32 partid) 195 { 196 struct pmc_ctlr *pmc = (struct pmc_ctlr *)NV_PA_PMC_BASE; 197 u32 reg; 198 199 /* Get power gate status */ 200 reg = readl(&pmc->pmc_pwrgate_status); 201 return !!(reg & (1 << partid)); 202 } 203 204 static void power_partition(u32 partid) 205 { 206 struct pmc_ctlr *pmc = (struct pmc_ctlr *)NV_PA_PMC_BASE; 207 208 debug("%s: part ID = %08X\n", __func__, partid); 209 /* Is the partition already on? */ 210 if (!is_partition_powered(partid)) { 211 /* No, toggle the partition power state (OFF -> ON) */ 212 debug("power_partition, toggling state\n"); 213 writel(START_CP | partid, &pmc->pmc_pwrgate_toggle); 214 215 /* Wait for the power to come up */ 216 while (!is_partition_powered(partid)) 217 ; 218 219 /* Give I/O signals time to stabilize */ 220 udelay(IO_STABILIZATION_DELAY); 221 } 222 } 223 224 void powerup_cpus(void) 225 { 226 debug("powerup_cpus entry\n"); 227 228 /* We boot to the fast cluster */ 229 debug("powerup_cpus entry: G cluster\n"); 230 231 /* Power up the fast cluster rail partition */ 232 debug("powerup_cpus: CRAIL\n"); 233 power_partition(CRAIL); 234 235 /* Power up the fast cluster non-CPU partition */ 236 debug("powerup_cpus: C0NC\n"); 237 power_partition(C0NC); 238 239 /* Power up the fast cluster CPU0 partition */ 240 debug("powerup_cpus: CE0\n"); 241 power_partition(CE0); 242 243 debug("powerup_cpus: done\n"); 244 } 245 246 void start_cpu(u32 reset_vector) 247 { 248 struct pmc_ctlr *pmc = (struct pmc_ctlr *)NV_PA_PMC_BASE; 249 250 debug("start_cpu entry, reset_vector = %x\n", reset_vector); 251 252 tegra124_init_clocks(); 253 254 /* Set power-gating timer multiplier */ 255 writel((MULT_8 << TIMER_MULT_SHIFT) | (MULT_8 << TIMER_MULT_CPU_SHIFT), 256 &pmc->pmc_pwrgate_timer_mult); 257 258 enable_cpu_power_rail(); 259 enable_cpu_clocks(); 260 clock_enable_coresight(1); 261 remove_cpu_resets(); 262 writel(reset_vector, EXCEP_VECTOR_CPU_RESET_VECTOR); 263 powerup_cpus(); 264 debug("start_cpu exit, should continue @ reset_vector\n"); 265 } 266