1 /* 2 * (C) Copyright 2013 3 * NVIDIA Corporation <www.nvidia.com> 4 * 5 * SPDX-License-Identifier: GPL-2.0+ 6 */ 7 8 #include <common.h> 9 #include <asm/io.h> 10 #include <asm/arch/ahb.h> 11 #include <asm/arch/clock.h> 12 #include <asm/arch/flow.h> 13 #include <asm/arch/pinmux.h> 14 #include <asm/arch/tegra.h> 15 #include <asm/arch-tegra/clk_rst.h> 16 #include <asm/arch-tegra/pmc.h> 17 #include <asm/arch-tegra/ap.h> 18 #include "../cpu.h" 19 20 /* Tegra124-specific CPU init code */ 21 22 static void enable_cpu_power_rail(void) 23 { 24 struct pmc_ctlr *pmc = (struct pmc_ctlr *)NV_PA_PMC_BASE; 25 26 debug("%s entry\n", __func__); 27 28 /* un-tristate PWR_I2C SCL/SDA, rest of the defaults are correct */ 29 pinmux_tristate_disable(PMUX_PINGRP_PWR_I2C_SCL_PZ6); 30 pinmux_tristate_disable(PMUX_PINGRP_PWR_I2C_SDA_PZ7); 31 32 pmic_enable_cpu_vdd(); 33 34 /* 35 * Set CPUPWRGOOD_TIMER - APB clock is 1/2 of SCLK (102MHz), 36 * set it for 5ms as per SysEng (102MHz*5ms = 510000 (7C830h). 37 */ 38 writel(0x7C830, &pmc->pmc_cpupwrgood_timer); 39 40 /* Set polarity to 0 (normal) and enable CPUPWRREQ_OE */ 41 clrbits_le32(&pmc->pmc_cntrl, CPUPWRREQ_POL); 42 setbits_le32(&pmc->pmc_cntrl, CPUPWRREQ_OE); 43 } 44 45 static void enable_cpu_clocks(void) 46 { 47 struct clk_rst_ctlr *clkrst = (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE; 48 struct clk_pll_info *pllinfo = &tegra_pll_info_table[CLOCK_ID_XCPU]; 49 u32 reg; 50 51 debug("%s entry\n", __func__); 52 53 /* Wait for PLL-X to lock */ 54 do { 55 reg = readl(&clkrst->crc_pll_simple[SIMPLE_PLLX].pll_base); 56 debug("%s: PLLX base = 0x%08X\n", __func__, reg); 57 } while ((reg & (1 << pllinfo->lock_det)) == 0); 58 59 debug("%s: PLLX locked, delay for stable clocks\n", __func__); 60 /* Wait until all clocks are stable */ 61 udelay(PLL_STABILIZATION_DELAY); 62 63 debug("%s: Setting CCLK_BURST and DIVIDER\n", __func__); 64 writel(CCLK_BURST_POLICY, &clkrst->crc_cclk_brst_pol); 65 writel(SUPER_CCLK_DIVIDER, &clkrst->crc_super_cclk_div); 66 67 debug("%s: Enabling clock to all CPUs\n", __func__); 68 /* Enable the clock to all CPUs */ 69 reg = CLR_CPU3_CLK_STP | CLR_CPU2_CLK_STP | CLR_CPU1_CLK_STP | 70 CLR_CPU0_CLK_STP; 71 writel(reg, &clkrst->crc_clk_cpu_cmplx_clr); 72 73 debug("%s: Enabling main CPU complex clocks\n", __func__); 74 /* Always enable the main CPU complex clocks */ 75 clock_enable(PERIPH_ID_CPU); 76 clock_enable(PERIPH_ID_CPULP); 77 clock_enable(PERIPH_ID_CPUG); 78 79 debug("%s: Done\n", __func__); 80 } 81 82 static void remove_cpu_resets(void) 83 { 84 struct clk_rst_ctlr *clkrst = (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE; 85 u32 reg; 86 87 debug("%s entry\n", __func__); 88 89 /* Take the slow and fast partitions out of reset */ 90 reg = CLR_NONCPURESET; 91 writel(reg, &clkrst->crc_rst_cpulp_cmplx_clr); 92 writel(reg, &clkrst->crc_rst_cpug_cmplx_clr); 93 94 /* Clear the SW-controlled reset of the slow cluster */ 95 reg = CLR_CPURESET0 | CLR_DBGRESET0 | CLR_CORERESET0 | CLR_CXRESET0 | 96 CLR_L2RESET | CLR_PRESETDBG; 97 writel(reg, &clkrst->crc_rst_cpulp_cmplx_clr); 98 99 /* Clear the SW-controlled reset of the fast cluster */ 100 reg = CLR_CPURESET0 | CLR_DBGRESET0 | CLR_CORERESET0 | CLR_CXRESET0 | 101 CLR_CPURESET1 | CLR_DBGRESET1 | CLR_CORERESET1 | CLR_CXRESET1 | 102 CLR_CPURESET2 | CLR_DBGRESET2 | CLR_CORERESET2 | CLR_CXRESET2 | 103 CLR_CPURESET3 | CLR_DBGRESET3 | CLR_CORERESET3 | CLR_CXRESET3 | 104 CLR_L2RESET | CLR_PRESETDBG; 105 writel(reg, &clkrst->crc_rst_cpug_cmplx_clr); 106 } 107 108 /** 109 * Tegra124 requires some special clock initialization, including setting up 110 * the DVC I2C, turning on MSELECT and selecting the G CPU cluster 111 */ 112 void tegra124_init_clocks(void) 113 { 114 struct flow_ctlr *flow = (struct flow_ctlr *)NV_PA_FLOW_BASE; 115 struct pmc_ctlr *pmc = (struct pmc_ctlr *)NV_PA_PMC_BASE; 116 struct clk_rst_ctlr *clkrst = 117 (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE; 118 u32 val; 119 120 debug("%s entry\n", __func__); 121 122 /* Set active CPU cluster to G */ 123 clrbits_le32(&flow->cluster_control, 1); 124 125 /* Change the oscillator drive strength */ 126 val = readl(&clkrst->crc_osc_ctrl); 127 val &= ~OSC_XOFS_MASK; 128 val |= (OSC_DRIVE_STRENGTH << OSC_XOFS_SHIFT); 129 writel(val, &clkrst->crc_osc_ctrl); 130 131 /* Update same value in PMC_OSC_EDPD_OVER XOFS field for warmboot */ 132 val = readl(&pmc->pmc_osc_edpd_over); 133 val &= ~PMC_XOFS_MASK; 134 val |= (OSC_DRIVE_STRENGTH << PMC_XOFS_SHIFT); 135 writel(val, &pmc->pmc_osc_edpd_over); 136 137 /* Set HOLD_CKE_LOW_EN to 1 */ 138 setbits_le32(&pmc->pmc_cntrl2, HOLD_CKE_LOW_EN); 139 140 debug("Setting up PLLX\n"); 141 init_pllx(); 142 143 val = (1 << CLK_SYS_RATE_AHB_RATE_SHIFT); 144 writel(val, &clkrst->crc_clk_sys_rate); 145 146 /* Enable clocks to required peripherals. TBD - minimize this list */ 147 debug("Enabling clocks\n"); 148 149 clock_set_enable(PERIPH_ID_CACHE2, 1); 150 clock_set_enable(PERIPH_ID_GPIO, 1); 151 clock_set_enable(PERIPH_ID_TMR, 1); 152 clock_set_enable(PERIPH_ID_CPU, 1); 153 clock_set_enable(PERIPH_ID_EMC, 1); 154 clock_set_enable(PERIPH_ID_I2C5, 1); 155 clock_set_enable(PERIPH_ID_APBDMA, 1); 156 clock_set_enable(PERIPH_ID_MEM, 1); 157 clock_set_enable(PERIPH_ID_CORESIGHT, 1); 158 clock_set_enable(PERIPH_ID_MSELECT, 1); 159 clock_set_enable(PERIPH_ID_DVFS, 1); 160 161 /* 162 * Set MSELECT clock source as PLLP (00), and ask for a clock 163 * divider that would set the MSELECT clock at 102MHz for a 164 * PLLP base of 408MHz. 165 */ 166 clock_ll_set_source_divisor(PERIPH_ID_MSELECT, 0, 167 CLK_DIVIDER(NVBL_PLLP_KHZ, 102000)); 168 169 /* Give clock time to stabilize */ 170 udelay(IO_STABILIZATION_DELAY); 171 172 /* I2C5 (DVC) gets CLK_M and a divisor of 17 */ 173 clock_ll_set_source_divisor(PERIPH_ID_I2C5, 3, 16); 174 175 /* Give clock time to stabilize */ 176 udelay(IO_STABILIZATION_DELAY); 177 178 /* Take required peripherals out of reset */ 179 debug("Taking periphs out of reset\n"); 180 reset_set_enable(PERIPH_ID_CACHE2, 0); 181 reset_set_enable(PERIPH_ID_GPIO, 0); 182 reset_set_enable(PERIPH_ID_TMR, 0); 183 reset_set_enable(PERIPH_ID_COP, 0); 184 reset_set_enable(PERIPH_ID_EMC, 0); 185 reset_set_enable(PERIPH_ID_I2C5, 0); 186 reset_set_enable(PERIPH_ID_APBDMA, 0); 187 reset_set_enable(PERIPH_ID_MEM, 0); 188 reset_set_enable(PERIPH_ID_CORESIGHT, 0); 189 reset_set_enable(PERIPH_ID_MSELECT, 0); 190 reset_set_enable(PERIPH_ID_DVFS, 0); 191 192 debug("%s exit\n", __func__); 193 } 194 195 static bool is_partition_powered(u32 partid) 196 { 197 struct pmc_ctlr *pmc = (struct pmc_ctlr *)NV_PA_PMC_BASE; 198 u32 reg; 199 200 /* Get power gate status */ 201 reg = readl(&pmc->pmc_pwrgate_status); 202 return !!(reg & (1 << partid)); 203 } 204 205 static void power_partition(u32 partid) 206 { 207 struct pmc_ctlr *pmc = (struct pmc_ctlr *)NV_PA_PMC_BASE; 208 209 debug("%s: part ID = %08X\n", __func__, partid); 210 /* Is the partition already on? */ 211 if (!is_partition_powered(partid)) { 212 /* No, toggle the partition power state (OFF -> ON) */ 213 debug("power_partition, toggling state\n"); 214 writel(START_CP | partid, &pmc->pmc_pwrgate_toggle); 215 216 /* Wait for the power to come up */ 217 while (!is_partition_powered(partid)) 218 ; 219 220 /* Give I/O signals time to stabilize */ 221 udelay(IO_STABILIZATION_DELAY); 222 } 223 } 224 225 void powerup_cpus(void) 226 { 227 /* We boot to the fast cluster */ 228 debug("%s entry: G cluster\n", __func__); 229 230 /* Power up the fast cluster rail partition */ 231 debug("%s: CRAIL\n", __func__); 232 power_partition(CRAIL); 233 234 /* Power up the fast cluster non-CPU partition */ 235 debug("%s: C0NC\n", __func__); 236 power_partition(C0NC); 237 238 /* Power up the fast cluster CPU0 partition */ 239 debug("%s: CE0\n", __func__); 240 power_partition(CE0); 241 242 debug("%s: done\n", __func__); 243 } 244 245 void start_cpu(u32 reset_vector) 246 { 247 struct pmc_ctlr *pmc = (struct pmc_ctlr *)NV_PA_PMC_BASE; 248 249 debug("%s entry, reset_vector = %x\n", __func__, reset_vector); 250 251 tegra124_init_clocks(); 252 253 /* Set power-gating timer multiplier */ 254 writel((MULT_8 << TIMER_MULT_SHIFT) | (MULT_8 << TIMER_MULT_CPU_SHIFT), 255 &pmc->pmc_pwrgate_timer_mult); 256 257 enable_cpu_power_rail(); 258 enable_cpu_clocks(); 259 clock_enable_coresight(1); 260 remove_cpu_resets(); 261 writel(reset_vector, EXCEP_VECTOR_CPU_RESET_VECTOR); 262 powerup_cpus(); 263 debug("%s exit, should continue @ reset_vector\n", __func__); 264 } 265