1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3  * (C) Copyright 2013-2015
4  * NVIDIA Corporation <www.nvidia.com>
5  */
6 
7 /* Tegra124 Clock control functions */
8 
9 #include <common.h>
10 #include <asm/io.h>
11 #include <asm/arch/clock.h>
12 #include <asm/arch/sysctr.h>
13 #include <asm/arch/tegra.h>
14 #include <asm/arch-tegra/clk_rst.h>
15 #include <asm/arch-tegra/timer.h>
16 #include <div64.h>
17 #include <fdtdec.h>
18 
19 /*
20  * Clock types that we can use as a source. The Tegra124 has muxes for the
21  * peripheral clocks, and in most cases there are four options for the clock
22  * source. This gives us a clock 'type' and exploits what commonality exists
23  * in the device.
24  *
25  * Letters are obvious, except for T which means CLK_M, and S which means the
26  * clock derived from 32KHz. Beware that CLK_M (also called OSC in the
27  * datasheet) and PLL_M are different things. The former is the basic
28  * clock supplied to the SOC from an external oscillator. The latter is the
29  * memory clock PLL.
30  *
31  * See definitions in clock_id in the header file.
32  */
33 enum clock_type_id {
34 	CLOCK_TYPE_AXPT,	/* PLL_A, PLL_X, PLL_P, CLK_M */
35 	CLOCK_TYPE_MCPA,	/* and so on */
36 	CLOCK_TYPE_MCPT,
37 	CLOCK_TYPE_PCM,
38 	CLOCK_TYPE_PCMT,
39 	CLOCK_TYPE_PDCT,
40 	CLOCK_TYPE_ACPT,
41 	CLOCK_TYPE_ASPTE,
42 	CLOCK_TYPE_PMDACD2T,
43 	CLOCK_TYPE_PCST,
44 	CLOCK_TYPE_DP,
45 
46 	CLOCK_TYPE_PC2CC3M,
47 	CLOCK_TYPE_PC2CC3S_T,
48 	CLOCK_TYPE_PC2CC3M_T,
49 	CLOCK_TYPE_PC2CC3M_T16,	/* PC2CC3M_T, but w/16-bit divisor (I2C) */
50 	CLOCK_TYPE_MC2CC3P_A,
51 	CLOCK_TYPE_M,
52 	CLOCK_TYPE_MCPTM2C2C3,
53 	CLOCK_TYPE_PC2CC3T_S,
54 	CLOCK_TYPE_AC2CC3P_TS2,
55 
56 	CLOCK_TYPE_COUNT,
57 	CLOCK_TYPE_NONE = -1,   /* invalid clock type */
58 };
59 
60 enum {
61 	CLOCK_MAX_MUX   = 8     /* number of source options for each clock */
62 };
63 
64 /*
65  * Clock source mux for each clock type. This just converts our enum into
66  * a list of mux sources for use by the code.
67  *
68  * Note:
69  *  The extra column in each clock source array is used to store the mask
70  *  bits in its register for the source.
71  */
72 #define CLK(x) CLOCK_ID_ ## x
73 static enum clock_id clock_source[CLOCK_TYPE_COUNT][CLOCK_MAX_MUX+1] = {
74 	{ CLK(AUDIO),	CLK(XCPU),	CLK(PERIPH),	CLK(OSC),
75 		CLK(NONE),	CLK(NONE),	CLK(NONE),	CLK(NONE),
76 		MASK_BITS_31_30},
77 	{ CLK(MEMORY),	CLK(CGENERAL),	CLK(PERIPH),	CLK(AUDIO),
78 		CLK(NONE),	CLK(NONE),	CLK(NONE),	CLK(NONE),
79 		MASK_BITS_31_30},
80 	{ CLK(MEMORY),	CLK(CGENERAL),	CLK(PERIPH),	CLK(OSC),
81 		CLK(NONE),	CLK(NONE),	CLK(NONE),	CLK(NONE),
82 		MASK_BITS_31_30},
83 	{ CLK(PERIPH),	CLK(CGENERAL),	CLK(MEMORY),	CLK(NONE),
84 		CLK(NONE),	CLK(NONE),	CLK(NONE),	CLK(NONE),
85 		MASK_BITS_31_30},
86 	{ CLK(PERIPH),	CLK(CGENERAL),	CLK(MEMORY),	CLK(OSC),
87 		CLK(NONE),	CLK(NONE),	CLK(NONE),	CLK(NONE),
88 		MASK_BITS_31_30},
89 	{ CLK(PERIPH),	CLK(DISPLAY),	CLK(CGENERAL),	CLK(OSC),
90 		CLK(NONE),	CLK(NONE),	CLK(NONE),	CLK(NONE),
91 		MASK_BITS_31_30},
92 	{ CLK(AUDIO),	CLK(CGENERAL),	CLK(PERIPH),	CLK(OSC),
93 		CLK(NONE),	CLK(NONE),	CLK(NONE),	CLK(NONE),
94 		MASK_BITS_31_30},
95 	{ CLK(AUDIO),	CLK(SFROM32KHZ),	CLK(PERIPH),	CLK(OSC),
96 		CLK(EPCI),	CLK(NONE),	CLK(NONE),	CLK(NONE),
97 		MASK_BITS_31_29},
98 	{ CLK(PERIPH),	CLK(MEMORY),	CLK(DISPLAY),	CLK(AUDIO),
99 		CLK(CGENERAL),	CLK(DISPLAY2),	CLK(OSC),	CLK(NONE),
100 		MASK_BITS_31_29},
101 	{ CLK(PERIPH),	CLK(CGENERAL),	CLK(SFROM32KHZ),	CLK(OSC),
102 		CLK(NONE),	CLK(NONE),	CLK(NONE),	CLK(NONE),
103 		MASK_BITS_31_28},
104 	/* CLOCK_TYPE_DP */
105 	{ CLK(NONE),	CLK(NONE),	CLK(NONE),	CLK(NONE),
106 		CLK(NONE),	CLK(NONE),	CLK(NONE),	CLK(NONE),
107 		MASK_BITS_31_28},
108 
109 	/* Additional clock types on Tegra114+ */
110 	/* CLOCK_TYPE_PC2CC3M */
111 	{ CLK(PERIPH),	CLK(CGENERAL2),	CLK(CGENERAL),	CLK(CGENERAL3),
112 		CLK(MEMORY),	CLK(NONE),	CLK(NONE),	CLK(NONE),
113 		MASK_BITS_31_29},
114 	/* CLOCK_TYPE_PC2CC3S_T */
115 	{ CLK(PERIPH),	CLK(CGENERAL2),	CLK(CGENERAL),	CLK(CGENERAL3),
116 		CLK(SFROM32KHZ), CLK(NONE),	CLK(OSC),	CLK(NONE),
117 		MASK_BITS_31_29},
118 	/* CLOCK_TYPE_PC2CC3M_T */
119 	{ CLK(PERIPH),	CLK(CGENERAL2),	CLK(CGENERAL),	CLK(CGENERAL3),
120 		CLK(MEMORY),	CLK(NONE),	CLK(OSC),	CLK(NONE),
121 		MASK_BITS_31_29},
122 	/* CLOCK_TYPE_PC2CC3M_T, w/16-bit divisor (I2C) */
123 	{ CLK(PERIPH),	CLK(CGENERAL2),	CLK(CGENERAL),	CLK(CGENERAL3),
124 		CLK(MEMORY),	CLK(NONE),	CLK(OSC),	CLK(NONE),
125 		MASK_BITS_31_29},
126 	/* CLOCK_TYPE_MC2CC3P_A */
127 	{ CLK(MEMORY),	CLK(CGENERAL2),	CLK(CGENERAL),	CLK(CGENERAL3),
128 		CLK(PERIPH),	CLK(NONE),	CLK(AUDIO),	CLK(NONE),
129 		MASK_BITS_31_29},
130 	/* CLOCK_TYPE_M */
131 	{ CLK(MEMORY),		CLK(NONE),	CLK(NONE),	CLK(NONE),
132 		CLK(NONE),	CLK(NONE),	CLK(NONE),	CLK(NONE),
133 		MASK_BITS_31_30},
134 	/* CLOCK_TYPE_MCPTM2C2C3 */
135 	{ CLK(MEMORY),	CLK(CGENERAL),	CLK(PERIPH),	CLK(OSC),
136 		CLK(MEMORY2),	CLK(CGENERAL2),	CLK(CGENERAL3),	CLK(NONE),
137 		MASK_BITS_31_29},
138 	/* CLOCK_TYPE_PC2CC3T_S */
139 	{ CLK(PERIPH),	CLK(CGENERAL2),	CLK(CGENERAL),	CLK(CGENERAL3),
140 		CLK(OSC),	CLK(NONE),	CLK(SFROM32KHZ), CLK(NONE),
141 		MASK_BITS_31_29},
142 	/* CLOCK_TYPE_AC2CC3P_TS2 */
143 	{ CLK(AUDIO),	CLK(CGENERAL2),	CLK(CGENERAL),	CLK(CGENERAL3),
144 		CLK(PERIPH),	CLK(NONE),	CLK(OSC),	CLK(SRC2),
145 		MASK_BITS_31_29},
146 };
147 
148 /*
149  * Clock type for each peripheral clock source. We put the name in each
150  * record just so it is easy to match things up
151  */
152 #define TYPE(name, type) type
153 static enum clock_type_id clock_periph_type[PERIPHC_COUNT] = {
154 	/* 0x00 */
155 	TYPE(PERIPHC_I2S1,	CLOCK_TYPE_AXPT),
156 	TYPE(PERIPHC_I2S2,	CLOCK_TYPE_AXPT),
157 	TYPE(PERIPHC_SPDIF_OUT,	CLOCK_TYPE_AXPT),
158 	TYPE(PERIPHC_SPDIF_IN,	CLOCK_TYPE_PC2CC3M),
159 	TYPE(PERIPHC_PWM,	CLOCK_TYPE_PC2CC3S_T),
160 	TYPE(PERIPHC_05h,	CLOCK_TYPE_NONE),
161 	TYPE(PERIPHC_SBC2,	CLOCK_TYPE_PC2CC3M_T),
162 	TYPE(PERIPHC_SBC3,	CLOCK_TYPE_PC2CC3M_T),
163 
164 	/* 0x08 */
165 	TYPE(PERIPHC_08h,	CLOCK_TYPE_NONE),
166 	TYPE(PERIPHC_I2C1,	CLOCK_TYPE_PC2CC3M_T16),
167 	TYPE(PERIPHC_I2C5,	CLOCK_TYPE_PC2CC3M_T16),
168 	TYPE(PERIPHC_0bh,	CLOCK_TYPE_NONE),
169 	TYPE(PERIPHC_0ch,	CLOCK_TYPE_NONE),
170 	TYPE(PERIPHC_SBC1,	CLOCK_TYPE_PC2CC3M_T),
171 	TYPE(PERIPHC_DISP1,	CLOCK_TYPE_PMDACD2T),
172 	TYPE(PERIPHC_DISP2,	CLOCK_TYPE_PMDACD2T),
173 
174 	/* 0x10 */
175 	TYPE(PERIPHC_10h,	CLOCK_TYPE_NONE),
176 	TYPE(PERIPHC_11h,	CLOCK_TYPE_NONE),
177 	TYPE(PERIPHC_VI,	CLOCK_TYPE_MC2CC3P_A),
178 	TYPE(PERIPHC_13h,	CLOCK_TYPE_NONE),
179 	TYPE(PERIPHC_SDMMC1,	CLOCK_TYPE_PC2CC3M_T),
180 	TYPE(PERIPHC_SDMMC2,	CLOCK_TYPE_PC2CC3M_T),
181 	TYPE(PERIPHC_16h,	CLOCK_TYPE_NONE),
182 	TYPE(PERIPHC_17h,	CLOCK_TYPE_NONE),
183 
184 	/* 0x18 */
185 	TYPE(PERIPHC_18h,	CLOCK_TYPE_NONE),
186 	TYPE(PERIPHC_SDMMC4,	CLOCK_TYPE_PC2CC3M_T),
187 	TYPE(PERIPHC_VFIR,	CLOCK_TYPE_PC2CC3M_T),
188 	TYPE(PERIPHC_1Bh,	CLOCK_TYPE_NONE),
189 	TYPE(PERIPHC_1Ch,	CLOCK_TYPE_NONE),
190 	TYPE(PERIPHC_HSI,	CLOCK_TYPE_PC2CC3M_T),
191 	TYPE(PERIPHC_UART1,	CLOCK_TYPE_PC2CC3M_T),
192 	TYPE(PERIPHC_UART2,	CLOCK_TYPE_PC2CC3M_T),
193 
194 	/* 0x20 */
195 	TYPE(PERIPHC_HOST1X,	CLOCK_TYPE_MC2CC3P_A),
196 	TYPE(PERIPHC_21h,	CLOCK_TYPE_NONE),
197 	TYPE(PERIPHC_22h,	CLOCK_TYPE_NONE),
198 	TYPE(PERIPHC_HDMI,	CLOCK_TYPE_PMDACD2T),
199 	TYPE(PERIPHC_24h,	CLOCK_TYPE_NONE),
200 	TYPE(PERIPHC_25h,	CLOCK_TYPE_NONE),
201 	TYPE(PERIPHC_I2C2,	CLOCK_TYPE_PC2CC3M_T16),
202 	TYPE(PERIPHC_EMC,	CLOCK_TYPE_MCPTM2C2C3),
203 
204 	/* 0x28 */
205 	TYPE(PERIPHC_UART3,	CLOCK_TYPE_PC2CC3M_T),
206 	TYPE(PERIPHC_29h,	CLOCK_TYPE_NONE),
207 	TYPE(PERIPHC_VI_SENSOR,	CLOCK_TYPE_MC2CC3P_A),
208 	TYPE(PERIPHC_2bh,	CLOCK_TYPE_NONE),
209 	TYPE(PERIPHC_2ch,	CLOCK_TYPE_NONE),
210 	TYPE(PERIPHC_SBC4,	CLOCK_TYPE_PC2CC3M_T),
211 	TYPE(PERIPHC_I2C3,	CLOCK_TYPE_PC2CC3M_T16),
212 	TYPE(PERIPHC_SDMMC3,	CLOCK_TYPE_PC2CC3M_T),
213 
214 	/* 0x30 */
215 	TYPE(PERIPHC_UART4,	CLOCK_TYPE_PC2CC3M_T),
216 	TYPE(PERIPHC_UART5,	CLOCK_TYPE_PC2CC3M_T),
217 	TYPE(PERIPHC_VDE,	CLOCK_TYPE_PC2CC3M_T),
218 	TYPE(PERIPHC_OWR,	CLOCK_TYPE_PC2CC3M_T),
219 	TYPE(PERIPHC_NOR,	CLOCK_TYPE_PC2CC3M_T),
220 	TYPE(PERIPHC_CSITE,	CLOCK_TYPE_PC2CC3M_T),
221 	TYPE(PERIPHC_I2S0,	CLOCK_TYPE_AXPT),
222 	TYPE(PERIPHC_DTV,	CLOCK_TYPE_NONE),
223 
224 	/* 0x38 */
225 	TYPE(PERIPHC_38h,	CLOCK_TYPE_NONE),
226 	TYPE(PERIPHC_39h,	CLOCK_TYPE_NONE),
227 	TYPE(PERIPHC_3ah,	CLOCK_TYPE_NONE),
228 	TYPE(PERIPHC_3bh,	CLOCK_TYPE_NONE),
229 	TYPE(PERIPHC_MSENC,	CLOCK_TYPE_MC2CC3P_A),
230 	TYPE(PERIPHC_TSEC,	CLOCK_TYPE_PC2CC3M_T),
231 	TYPE(PERIPHC_3eh,	CLOCK_TYPE_NONE),
232 	TYPE(PERIPHC_OSC,	CLOCK_TYPE_NONE),
233 
234 	/* 0x40 */
235 	TYPE(PERIPHC_40h,	CLOCK_TYPE_NONE),	/* start with 0x3b0 */
236 	TYPE(PERIPHC_MSELECT,	CLOCK_TYPE_PC2CC3M_T),
237 	TYPE(PERIPHC_TSENSOR,	CLOCK_TYPE_PC2CC3T_S),
238 	TYPE(PERIPHC_I2S3,	CLOCK_TYPE_AXPT),
239 	TYPE(PERIPHC_I2S4,	CLOCK_TYPE_AXPT),
240 	TYPE(PERIPHC_I2C4,	CLOCK_TYPE_PC2CC3M_T16),
241 	TYPE(PERIPHC_SBC5,	CLOCK_TYPE_PC2CC3M_T),
242 	TYPE(PERIPHC_SBC6,	CLOCK_TYPE_PC2CC3M_T),
243 
244 	/* 0x48 */
245 	TYPE(PERIPHC_AUDIO,	CLOCK_TYPE_AC2CC3P_TS2),
246 	TYPE(PERIPHC_49h,	CLOCK_TYPE_NONE),
247 	TYPE(PERIPHC_DAM0,	CLOCK_TYPE_AC2CC3P_TS2),
248 	TYPE(PERIPHC_DAM1,	CLOCK_TYPE_AC2CC3P_TS2),
249 	TYPE(PERIPHC_DAM2,	CLOCK_TYPE_AC2CC3P_TS2),
250 	TYPE(PERIPHC_HDA2CODEC2X, CLOCK_TYPE_PC2CC3M_T),
251 	TYPE(PERIPHC_ACTMON,	CLOCK_TYPE_PC2CC3S_T),
252 	TYPE(PERIPHC_EXTPERIPH1, CLOCK_TYPE_ASPTE),
253 
254 	/* 0x50 */
255 	TYPE(PERIPHC_EXTPERIPH2, CLOCK_TYPE_ASPTE),
256 	TYPE(PERIPHC_EXTPERIPH3, CLOCK_TYPE_ASPTE),
257 	TYPE(PERIPHC_52h,	CLOCK_TYPE_NONE),
258 	TYPE(PERIPHC_I2CSLOW,	CLOCK_TYPE_PC2CC3S_T),
259 	TYPE(PERIPHC_SYS,	CLOCK_TYPE_NONE),
260 	TYPE(PERIPHC_55h,	CLOCK_TYPE_NONE),
261 	TYPE(PERIPHC_56h,	CLOCK_TYPE_NONE),
262 	TYPE(PERIPHC_57h,	CLOCK_TYPE_NONE),
263 
264 	/* 0x58 */
265 	TYPE(PERIPHC_58h,	CLOCK_TYPE_NONE),
266 	TYPE(PERIPHC_SOR,	CLOCK_TYPE_NONE),
267 	TYPE(PERIPHC_5ah,	CLOCK_TYPE_NONE),
268 	TYPE(PERIPHC_5bh,	CLOCK_TYPE_NONE),
269 	TYPE(PERIPHC_SATAOOB,	CLOCK_TYPE_PCMT),
270 	TYPE(PERIPHC_SATA,	CLOCK_TYPE_PCMT),
271 	TYPE(PERIPHC_HDA,	CLOCK_TYPE_PC2CC3M_T),
272 	TYPE(PERIPHC_5fh,	CLOCK_TYPE_NONE),
273 
274 	/* 0x60 */
275 	TYPE(PERIPHC_XUSB_CORE_HOST, CLOCK_TYPE_NONE),
276 	TYPE(PERIPHC_XUSB_FALCON, CLOCK_TYPE_NONE),
277 	TYPE(PERIPHC_XUSB_FS,	CLOCK_TYPE_NONE),
278 	TYPE(PERIPHC_XUSB_CORE_DEV, CLOCK_TYPE_NONE),
279 	TYPE(PERIPHC_XUSB_SS,	CLOCK_TYPE_NONE),
280 	TYPE(PERIPHC_CILAB,	CLOCK_TYPE_NONE),
281 	TYPE(PERIPHC_CILCD,	CLOCK_TYPE_NONE),
282 	TYPE(PERIPHC_CILE,	CLOCK_TYPE_NONE),
283 
284 	/* 0x68 */
285 	TYPE(PERIPHC_DSIA_LP,	CLOCK_TYPE_NONE),
286 	TYPE(PERIPHC_DSIB_LP,	CLOCK_TYPE_NONE),
287 	TYPE(PERIPHC_ENTROPY,	CLOCK_TYPE_NONE),
288 	TYPE(PERIPHC_DVFS_REF,	CLOCK_TYPE_NONE),
289 	TYPE(PERIPHC_DVFS_SOC,	CLOCK_TYPE_NONE),
290 	TYPE(PERIPHC_TRACECLKIN, CLOCK_TYPE_NONE),
291 	TYPE(PERIPHC_ADX0,	CLOCK_TYPE_NONE),
292 	TYPE(PERIPHC_AMX0,	CLOCK_TYPE_NONE),
293 
294 	/* 0x70 */
295 	TYPE(PERIPHC_EMC_LATENCY, CLOCK_TYPE_NONE),
296 	TYPE(PERIPHC_SOC_THERM,	CLOCK_TYPE_NONE),
297 	TYPE(PERIPHC_72h,	CLOCK_TYPE_NONE),
298 	TYPE(PERIPHC_73h,	CLOCK_TYPE_NONE),
299 	TYPE(PERIPHC_74h,	CLOCK_TYPE_NONE),
300 	TYPE(PERIPHC_75h,	CLOCK_TYPE_NONE),
301 	TYPE(PERIPHC_VI_SENSOR2, CLOCK_TYPE_NONE),
302 	TYPE(PERIPHC_I2C6,	CLOCK_TYPE_PC2CC3M_T16),
303 
304 	/* 0x78 */
305 	TYPE(PERIPHC_78h,	CLOCK_TYPE_NONE),
306 	TYPE(PERIPHC_EMC_DLL,	CLOCK_TYPE_MCPTM2C2C3),
307 	TYPE(PERIPHC_HDMI_AUDIO, CLOCK_TYPE_NONE),
308 	TYPE(PERIPHC_CLK72MHZ,	CLOCK_TYPE_NONE),
309 	TYPE(PERIPHC_ADX1,	CLOCK_TYPE_AC2CC3P_TS2),
310 	TYPE(PERIPHC_AMX1,	CLOCK_TYPE_AC2CC3P_TS2),
311 	TYPE(PERIPHC_VIC,	CLOCK_TYPE_NONE),
312 	TYPE(PERIPHC_7Fh,	CLOCK_TYPE_NONE),
313 };
314 
315 /*
316  * This array translates a periph_id to a periphc_internal_id
317  *
318  * Not present/matched up:
319  *	uint vi_sensor;	 _VI_SENSOR_0,		0x1A8
320  *	SPDIF - which is both 0x08 and 0x0c
321  *
322  */
323 #define NONE(name) (-1)
324 #define OFFSET(name, value) PERIPHC_ ## name
325 static s8 periph_id_to_internal_id[PERIPH_ID_COUNT] = {
326 	/* Low word: 31:0 */
327 	NONE(CPU),
328 	NONE(COP),
329 	NONE(TRIGSYS),
330 	NONE(ISPB),
331 	NONE(RESERVED4),
332 	NONE(TMR),
333 	PERIPHC_UART1,
334 	PERIPHC_UART2,	/* and vfir 0x68 */
335 
336 	/* 8 */
337 	NONE(GPIO),
338 	PERIPHC_SDMMC2,
339 	PERIPHC_SPDIF_IN,
340 	PERIPHC_I2S1,
341 	PERIPHC_I2C1,
342 	NONE(RESERVED13),
343 	PERIPHC_SDMMC1,
344 	PERIPHC_SDMMC4,
345 
346 	/* 16 */
347 	NONE(TCW),
348 	PERIPHC_PWM,
349 	PERIPHC_I2S2,
350 	NONE(RESERVED19),
351 	PERIPHC_VI,
352 	NONE(RESERVED21),
353 	NONE(USBD),
354 	NONE(ISP),
355 
356 	/* 24 */
357 	NONE(RESERVED24),
358 	NONE(RESERVED25),
359 	PERIPHC_DISP2,
360 	PERIPHC_DISP1,
361 	PERIPHC_HOST1X,
362 	NONE(VCP),
363 	PERIPHC_I2S0,
364 	NONE(CACHE2),
365 
366 	/* Middle word: 63:32 */
367 	NONE(MEM),
368 	NONE(AHBDMA),
369 	NONE(APBDMA),
370 	NONE(RESERVED35),
371 	NONE(RESERVED36),
372 	NONE(STAT_MON),
373 	NONE(RESERVED38),
374 	NONE(FUSE),
375 
376 	/* 40 */
377 	NONE(KFUSE),
378 	PERIPHC_SBC1,		/* SBCx = SPIx */
379 	PERIPHC_NOR,
380 	NONE(RESERVED43),
381 	PERIPHC_SBC2,
382 	NONE(XIO),
383 	PERIPHC_SBC3,
384 	PERIPHC_I2C5,
385 
386 	/* 48 */
387 	NONE(DSI),
388 	NONE(RESERVED49),
389 	PERIPHC_HSI,
390 	PERIPHC_HDMI,
391 	NONE(CSI),
392 	NONE(RESERVED53),
393 	PERIPHC_I2C2,
394 	PERIPHC_UART3,
395 
396 	/* 56 */
397 	NONE(MIPI_CAL),
398 	PERIPHC_EMC,
399 	NONE(USB2),
400 	NONE(USB3),
401 	NONE(RESERVED60),
402 	PERIPHC_VDE,
403 	NONE(BSEA),
404 	NONE(BSEV),
405 
406 	/* Upper word 95:64 */
407 	NONE(RESERVED64),
408 	PERIPHC_UART4,
409 	PERIPHC_UART5,
410 	PERIPHC_I2C3,
411 	PERIPHC_SBC4,
412 	PERIPHC_SDMMC3,
413 	NONE(PCIE),
414 	PERIPHC_OWR,
415 
416 	/* 72 */
417 	NONE(AFI),
418 	PERIPHC_CSITE,
419 	NONE(PCIEXCLK),
420 	NONE(AVPUCQ),
421 	NONE(LA),
422 	NONE(TRACECLKIN),
423 	NONE(SOC_THERM),
424 	NONE(DTV),
425 
426 	/* 80 */
427 	NONE(RESERVED80),
428 	PERIPHC_I2CSLOW,
429 	NONE(DSIB),
430 	PERIPHC_TSEC,
431 	NONE(RESERVED84),
432 	NONE(RESERVED85),
433 	NONE(RESERVED86),
434 	NONE(EMUCIF),
435 
436 	/* 88 */
437 	NONE(RESERVED88),
438 	NONE(XUSB_HOST),
439 	NONE(RESERVED90),
440 	PERIPHC_MSENC,
441 	NONE(RESERVED92),
442 	NONE(RESERVED93),
443 	NONE(RESERVED94),
444 	NONE(XUSB_DEV),
445 
446 	/* V word: 31:0 */
447 	NONE(CPUG),
448 	NONE(CPULP),
449 	NONE(V_RESERVED2),
450 	PERIPHC_MSELECT,
451 	NONE(V_RESERVED4),
452 	PERIPHC_I2S3,
453 	PERIPHC_I2S4,
454 	PERIPHC_I2C4,
455 
456 	/* 104 */
457 	PERIPHC_SBC5,
458 	PERIPHC_SBC6,
459 	PERIPHC_AUDIO,
460 	NONE(APBIF),
461 	PERIPHC_DAM0,
462 	PERIPHC_DAM1,
463 	PERIPHC_DAM2,
464 	PERIPHC_HDA2CODEC2X,
465 
466 	/* 112 */
467 	NONE(ATOMICS),
468 	NONE(V_RESERVED17),
469 	NONE(V_RESERVED18),
470 	NONE(V_RESERVED19),
471 	NONE(V_RESERVED20),
472 	NONE(V_RESERVED21),
473 	NONE(V_RESERVED22),
474 	PERIPHC_ACTMON,
475 
476 	/* 120 */
477 	PERIPHC_EXTPERIPH1,
478 	NONE(EXTPERIPH2),
479 	NONE(EXTPERIPH3),
480 	NONE(OOB),
481 	PERIPHC_SATA,
482 	PERIPHC_HDA,
483 	NONE(TZRAM),
484 	NONE(SE),
485 
486 	/* W word: 31:0 */
487 	NONE(HDA2HDMICODEC),
488 	NONE(SATACOLD),
489 	NONE(W_RESERVED2),
490 	NONE(W_RESERVED3),
491 	NONE(W_RESERVED4),
492 	NONE(W_RESERVED5),
493 	NONE(W_RESERVED6),
494 	NONE(W_RESERVED7),
495 
496 	/* 136 */
497 	NONE(CEC),
498 	NONE(W_RESERVED9),
499 	NONE(W_RESERVED10),
500 	NONE(W_RESERVED11),
501 	NONE(W_RESERVED12),
502 	NONE(W_RESERVED13),
503 	NONE(XUSB_PADCTL),
504 	NONE(W_RESERVED15),
505 
506 	/* 144 */
507 	NONE(W_RESERVED16),
508 	NONE(W_RESERVED17),
509 	NONE(W_RESERVED18),
510 	NONE(W_RESERVED19),
511 	NONE(W_RESERVED20),
512 	NONE(ENTROPY),
513 	NONE(DDS),
514 	NONE(W_RESERVED23),
515 
516 	/* 152 */
517 	NONE(DP2),
518 	NONE(AMX0),
519 	NONE(ADX0),
520 	NONE(DVFS),
521 	NONE(XUSB_SS),
522 	NONE(W_RESERVED29),
523 	NONE(W_RESERVED30),
524 	NONE(W_RESERVED31),
525 
526 	/* X word: 31:0 */
527 	NONE(SPARE),
528 	NONE(X_RESERVED1),
529 	NONE(X_RESERVED2),
530 	NONE(X_RESERVED3),
531 	NONE(CAM_MCLK),
532 	NONE(CAM_MCLK2),
533 	PERIPHC_I2C6,
534 	NONE(X_RESERVED7),
535 
536 	/* 168 */
537 	NONE(X_RESERVED8),
538 	NONE(X_RESERVED9),
539 	NONE(X_RESERVED10),
540 	NONE(VIM2_CLK),
541 	NONE(X_RESERVED12),
542 	NONE(X_RESERVED13),
543 	NONE(EMC_DLL),
544 	NONE(X_RESERVED15),
545 
546 	/* 176 */
547 	NONE(HDMI_AUDIO),
548 	NONE(CLK72MHZ),
549 	NONE(VIC),
550 	NONE(X_RESERVED19),
551 	NONE(ADX1),
552 	NONE(DPAUX),
553 	PERIPHC_SOR,
554 	NONE(X_RESERVED23),
555 
556 	/* 184 */
557 	NONE(GPU),
558 	NONE(AMX1),
559 	NONE(X_RESERVED26),
560 	NONE(X_RESERVED27),
561 	NONE(X_RESERVED28),
562 	NONE(X_RESERVED29),
563 	NONE(X_RESERVED30),
564 	NONE(X_RESERVED31),
565 };
566 
567 /*
568  * PLL divider shift/mask tables for all PLL IDs.
569  */
570 struct clk_pll_info tegra_pll_info_table[CLOCK_ID_PLL_COUNT] = {
571 	/*
572 	 * T124: same as T114, some deviations from T2x/T30. Adds PLLDP.
573 	 * NOTE: If kcp_mask/kvco_mask == 0, they're not used in that PLL (PLLX, etc.)
574 	 *       If lock_ena or lock_det are >31, they're not used in that PLL.
575 	 */
576 
577 	{ .m_shift = 0, .m_mask = 0xFF, .n_shift = 8, .n_mask = 0xFF,  .p_shift = 20, .p_mask = 0x0F,
578 	  .lock_ena = 24, .lock_det = 27, .kcp_shift = 28, .kcp_mask = 3, .kvco_shift = 27, .kvco_mask = 1 },	/* PLLC */
579 	{ .m_shift = 0, .m_mask = 0xFF, .n_shift = 8, .n_mask = 0xFF,  .p_shift = 0,  .p_mask = 0,
580 	  .lock_ena = 0,  .lock_det = 27, .kcp_shift = 1, .kcp_mask = 3, .kvco_shift = 0, .kvco_mask = 1 },	/* PLLM */
581 	{ .m_shift = 0, .m_mask = 0x1F, .n_shift = 8, .n_mask = 0x3FF, .p_shift = 20, .p_mask = 0x07,
582 	  .lock_ena = 18, .lock_det = 27, .kcp_shift = 8, .kcp_mask = 0xF, .kvco_shift = 4, .kvco_mask = 0xF },	/* PLLP */
583 	{ .m_shift = 0, .m_mask = 0x1F, .n_shift = 8, .n_mask = 0x3FF, .p_shift = 20, .p_mask = 0x07,
584 	  .lock_ena = 18, .lock_det = 27, .kcp_shift = 8, .kcp_mask = 0xF, .kvco_shift = 4, .kvco_mask = 0xF },	/* PLLA */
585 	{ .m_shift = 0, .m_mask = 0x1F, .n_shift = 8, .n_mask = 0x3FF, .p_shift = 20, .p_mask = 0x01,
586 	  .lock_ena = 22, .lock_det = 27, .kcp_shift = 8, .kcp_mask = 0xF, .kvco_shift = 4, .kvco_mask = 0xF },	/* PLLU */
587 	{ .m_shift = 0, .m_mask = 0x1F, .n_shift = 8, .n_mask = 0x3FF, .p_shift = 20, .p_mask = 0x07,
588 	  .lock_ena = 22, .lock_det = 27, .kcp_shift = 8, .kcp_mask = 0xF, .kvco_shift = 4, .kvco_mask = 0xF },	/* PLLD */
589 	{ .m_shift = 0, .m_mask = 0xFF, .n_shift = 8, .n_mask = 0xFF,  .p_shift = 20, .p_mask = 0x0F,
590 	  .lock_ena = 18, .lock_det = 27, .kcp_shift = 0, .kcp_mask = 0, .kvco_shift = 0, .kvco_mask = 0 },	/* PLLX */
591 	{ .m_shift = 0, .m_mask = 0xFF, .n_shift = 8, .n_mask = 0xFF,  .p_shift = 0,  .p_mask = 0,
592 	  .lock_ena = 9,  .lock_det = 11, .kcp_shift = 6, .kcp_mask = 3, .kvco_shift = 0, .kvco_mask = 1 },	/* PLLE */
593 	{ .m_shift = 0, .m_mask = 0x0F, .n_shift = 8, .n_mask = 0x3FF, .p_shift = 20, .p_mask = 0x07,
594 	  .lock_ena = 18, .lock_det = 27, .kcp_shift = 8, .kcp_mask = 0xF, .kvco_shift = 4, .kvco_mask = 0xF },	/* PLLS (RESERVED) */
595 	{ .m_shift = 0, .m_mask = 0xFF, .n_shift = 8, .n_mask = 0xFF,  .p_shift = 20,  .p_mask = 0xF,
596 	  .lock_ena = 30, .lock_det = 27, .kcp_shift = 25, .kcp_mask = 3, .kvco_shift = 24, .kvco_mask = 1 },	/* PLLDP */
597 };
598 
599 /*
600  * Get the oscillator frequency, from the corresponding hardware configuration
601  * field. Note that Tegra30+ support 3 new higher freqs, but we map back
602  * to the old T20 freqs. Support for the higher oscillators is TBD.
603  */
604 enum clock_osc_freq clock_get_osc_freq(void)
605 {
606 	struct clk_rst_ctlr *clkrst =
607 			(struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
608 	u32 reg;
609 
610 	reg = readl(&clkrst->crc_osc_ctrl);
611 	reg = (reg & OSC_FREQ_MASK) >> OSC_FREQ_SHIFT;
612 
613 	if (reg & 1)				/* one of the newer freqs */
614 		printf("Warning: OSC_FREQ is unsupported! (%d)\n", reg);
615 
616 	return reg >> 2;	/* Map to most common (T20) freqs */
617 }
618 
619 /* Returns a pointer to the clock source register for a peripheral */
620 u32 *get_periph_source_reg(enum periph_id periph_id)
621 {
622 	struct clk_rst_ctlr *clkrst =
623 		(struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
624 	enum periphc_internal_id internal_id;
625 
626 	/* Coresight is a special case */
627 	if (periph_id == PERIPH_ID_CSI)
628 		return &clkrst->crc_clk_src[PERIPH_ID_CSI+1];
629 
630 	assert(periph_id >= PERIPH_ID_FIRST && periph_id < PERIPH_ID_COUNT);
631 	internal_id = periph_id_to_internal_id[periph_id];
632 	assert(internal_id != -1);
633 	if (internal_id >= PERIPHC_X_FIRST) {
634 		internal_id -= PERIPHC_X_FIRST;
635 		return &clkrst->crc_clk_src_x[internal_id];
636 	} else if (internal_id >= PERIPHC_VW_FIRST) {
637 		internal_id -= PERIPHC_VW_FIRST;
638 		return &clkrst->crc_clk_src_vw[internal_id];
639 	} else {
640 		return &clkrst->crc_clk_src[internal_id];
641 	}
642 }
643 
644 int get_periph_clock_info(enum periph_id periph_id, int *mux_bits,
645 			  int *divider_bits, int *type)
646 {
647 	enum periphc_internal_id internal_id;
648 
649 	if (!clock_periph_id_isvalid(periph_id))
650 		return -1;
651 
652 	internal_id = periph_id_to_internal_id[periph_id];
653 	if (!periphc_internal_id_isvalid(internal_id))
654 		return -1;
655 
656 	*type = clock_periph_type[internal_id];
657 	if (!clock_type_id_isvalid(*type))
658 		return -1;
659 
660 	*mux_bits = clock_source[*type][CLOCK_MAX_MUX];
661 
662 	if (*type == CLOCK_TYPE_PC2CC3M_T16)
663 		*divider_bits = 16;
664 	else
665 		*divider_bits = 8;
666 
667 	return 0;
668 }
669 
670 enum clock_id get_periph_clock_id(enum periph_id periph_id, int source)
671 {
672 	enum periphc_internal_id internal_id;
673 	int type;
674 
675 	if (!clock_periph_id_isvalid(periph_id))
676 		return CLOCK_ID_NONE;
677 
678 	internal_id = periph_id_to_internal_id[periph_id];
679 	if (!periphc_internal_id_isvalid(internal_id))
680 		return CLOCK_ID_NONE;
681 
682 	type = clock_periph_type[internal_id];
683 	if (!clock_type_id_isvalid(type))
684 		return CLOCK_ID_NONE;
685 
686 	return clock_source[type][source];
687 }
688 
689 /**
690  * Given a peripheral ID and the required source clock, this returns which
691  * value should be programmed into the source mux for that peripheral.
692  *
693  * There is special code here to handle the one source type with 5 sources.
694  *
695  * @param periph_id	peripheral to start
696  * @param source	PLL id of required parent clock
697  * @param mux_bits	Set to number of bits in mux register: 2 or 4
698  * @param divider_bits Set to number of divider bits (8 or 16)
699  * @return mux value (0-4, or -1 if not found)
700  */
701 int get_periph_clock_source(enum periph_id periph_id,
702 	enum clock_id parent, int *mux_bits, int *divider_bits)
703 {
704 	enum clock_type_id type;
705 	int mux, err;
706 
707 	err = get_periph_clock_info(periph_id, mux_bits, divider_bits, &type);
708 	assert(!err);
709 
710 	for (mux = 0; mux < CLOCK_MAX_MUX; mux++)
711 		if (clock_source[type][mux] == parent)
712 			return mux;
713 
714 	/* if we get here, either us or the caller has made a mistake */
715 	printf("Caller requested bad clock: periph=%d, parent=%d\n", periph_id,
716 	       parent);
717 	return -1;
718 }
719 
720 void clock_set_enable(enum periph_id periph_id, int enable)
721 {
722 	struct clk_rst_ctlr *clkrst =
723 		(struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
724 	u32 *clk;
725 	u32 reg;
726 
727 	/* Enable/disable the clock to this peripheral */
728 	assert(clock_periph_id_isvalid(periph_id));
729 	if ((int)periph_id < (int)PERIPH_ID_VW_FIRST)
730 		clk = &clkrst->crc_clk_out_enb[PERIPH_REG(periph_id)];
731 	else if ((int)periph_id < PERIPH_ID_X_FIRST)
732 		clk = &clkrst->crc_clk_out_enb_vw[PERIPH_REG(periph_id)];
733 	else
734 		clk = &clkrst->crc_clk_out_enb_x;
735 	reg = readl(clk);
736 	if (enable)
737 		reg |= PERIPH_MASK(periph_id);
738 	else
739 		reg &= ~PERIPH_MASK(periph_id);
740 	writel(reg, clk);
741 }
742 
743 void reset_set_enable(enum periph_id periph_id, int enable)
744 {
745 	struct clk_rst_ctlr *clkrst =
746 		(struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
747 	u32 *reset;
748 	u32 reg;
749 
750 	/* Enable/disable reset to the peripheral */
751 	assert(clock_periph_id_isvalid(periph_id));
752 	if (periph_id < PERIPH_ID_VW_FIRST)
753 		reset = &clkrst->crc_rst_dev[PERIPH_REG(periph_id)];
754 	else if ((int)periph_id < PERIPH_ID_X_FIRST)
755 		reset = &clkrst->crc_rst_dev_vw[PERIPH_REG(periph_id)];
756 	else
757 		reset = &clkrst->crc_rst_devices_x;
758 	reg = readl(reset);
759 	if (enable)
760 		reg |= PERIPH_MASK(periph_id);
761 	else
762 		reg &= ~PERIPH_MASK(periph_id);
763 	writel(reg, reset);
764 }
765 
766 #if CONFIG_IS_ENABLED(OF_CONTROL)
767 /*
768  * Convert a device tree clock ID to our peripheral ID. They are mostly
769  * the same but we are very cautious so we check that a valid clock ID is
770  * provided.
771  *
772  * @param clk_id    Clock ID according to tegra124 device tree binding
773  * @return peripheral ID, or PERIPH_ID_NONE if the clock ID is invalid
774  */
775 enum periph_id clk_id_to_periph_id(int clk_id)
776 {
777 	if (clk_id > PERIPH_ID_COUNT)
778 		return PERIPH_ID_NONE;
779 
780 	switch (clk_id) {
781 	case PERIPH_ID_RESERVED4:
782 	case PERIPH_ID_RESERVED25:
783 	case PERIPH_ID_RESERVED35:
784 	case PERIPH_ID_RESERVED36:
785 	case PERIPH_ID_RESERVED38:
786 	case PERIPH_ID_RESERVED43:
787 	case PERIPH_ID_RESERVED49:
788 	case PERIPH_ID_RESERVED53:
789 	case PERIPH_ID_RESERVED64:
790 	case PERIPH_ID_RESERVED84:
791 	case PERIPH_ID_RESERVED85:
792 	case PERIPH_ID_RESERVED86:
793 	case PERIPH_ID_RESERVED88:
794 	case PERIPH_ID_RESERVED90:
795 	case PERIPH_ID_RESERVED92:
796 	case PERIPH_ID_RESERVED93:
797 	case PERIPH_ID_RESERVED94:
798 	case PERIPH_ID_V_RESERVED2:
799 	case PERIPH_ID_V_RESERVED4:
800 	case PERIPH_ID_V_RESERVED17:
801 	case PERIPH_ID_V_RESERVED18:
802 	case PERIPH_ID_V_RESERVED19:
803 	case PERIPH_ID_V_RESERVED20:
804 	case PERIPH_ID_V_RESERVED21:
805 	case PERIPH_ID_V_RESERVED22:
806 	case PERIPH_ID_W_RESERVED2:
807 	case PERIPH_ID_W_RESERVED3:
808 	case PERIPH_ID_W_RESERVED4:
809 	case PERIPH_ID_W_RESERVED5:
810 	case PERIPH_ID_W_RESERVED6:
811 	case PERIPH_ID_W_RESERVED7:
812 	case PERIPH_ID_W_RESERVED9:
813 	case PERIPH_ID_W_RESERVED10:
814 	case PERIPH_ID_W_RESERVED11:
815 	case PERIPH_ID_W_RESERVED12:
816 	case PERIPH_ID_W_RESERVED13:
817 	case PERIPH_ID_W_RESERVED15:
818 	case PERIPH_ID_W_RESERVED16:
819 	case PERIPH_ID_W_RESERVED17:
820 	case PERIPH_ID_W_RESERVED18:
821 	case PERIPH_ID_W_RESERVED19:
822 	case PERIPH_ID_W_RESERVED20:
823 	case PERIPH_ID_W_RESERVED23:
824 	case PERIPH_ID_W_RESERVED29:
825 	case PERIPH_ID_W_RESERVED30:
826 	case PERIPH_ID_W_RESERVED31:
827 		return PERIPH_ID_NONE;
828 	default:
829 		return clk_id;
830 	}
831 }
832 #endif /* CONFIG_IS_ENABLED(OF_CONTROL) */
833 
834 void clock_early_init(void)
835 {
836 	struct clk_rst_ctlr *clkrst =
837 		(struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
838 	struct clk_pll_info *pllinfo;
839 	u32 data;
840 
841 	tegra30_set_up_pllp();
842 
843 	/* clear IDDQ before accessing any other PLLC registers */
844 	pllinfo = &tegra_pll_info_table[CLOCK_ID_CGENERAL];
845 	clrbits_le32(&clkrst->crc_pll[CLOCK_ID_CGENERAL].pll_misc, PLLC_IDDQ);
846 	udelay(2);
847 
848 	/*
849 	 * PLLC output frequency set to 600Mhz
850 	 * PLLD output frequency set to 925Mhz
851 	 */
852 	switch (clock_get_osc_freq()) {
853 	case CLOCK_OSC_FREQ_12_0: /* OSC is 12Mhz */
854 		clock_set_rate(CLOCK_ID_CGENERAL, 600, 12, 0, 8);
855 		clock_set_rate(CLOCK_ID_DISPLAY, 925, 12, 0, 12);
856 		break;
857 
858 	case CLOCK_OSC_FREQ_26_0: /* OSC is 26Mhz */
859 		clock_set_rate(CLOCK_ID_CGENERAL, 600, 26, 0, 8);
860 		clock_set_rate(CLOCK_ID_DISPLAY, 925, 26, 0, 12);
861 		break;
862 
863 	case CLOCK_OSC_FREQ_13_0: /* OSC is 13Mhz */
864 		clock_set_rate(CLOCK_ID_CGENERAL, 600, 13, 0, 8);
865 		clock_set_rate(CLOCK_ID_DISPLAY, 925, 13, 0, 12);
866 		break;
867 	case CLOCK_OSC_FREQ_19_2:
868 	default:
869 		/*
870 		 * These are not supported. It is too early to print a
871 		 * message and the UART likely won't work anyway due to the
872 		 * oscillator being wrong.
873 		 */
874 		break;
875 	}
876 
877 	/* PLLC_MISC2: Set dynramp_stepA/B. MISC2 maps to pll_out[1] */
878 	writel(0x00561600, &clkrst->crc_pll[CLOCK_ID_CGENERAL].pll_out[1]);
879 
880 	/* PLLC_MISC: Set LOCK_ENABLE */
881 	pllinfo = &tegra_pll_info_table[CLOCK_ID_CGENERAL];
882 	setbits_le32(&clkrst->crc_pll[CLOCK_ID_CGENERAL].pll_misc, (1 << pllinfo->lock_ena));
883 	udelay(2);
884 
885 	/* PLLD_MISC: Set CLKENABLE, CPCON 12, LFCON 1, and enable lock */
886 	pllinfo = &tegra_pll_info_table[CLOCK_ID_DISPLAY];
887 	data = (12 << pllinfo->kcp_shift) | (1 << pllinfo->kvco_shift);
888 	data |= (1 << PLLD_CLKENABLE) | (1 << pllinfo->lock_ena);
889 	writel(data, &clkrst->crc_pll[CLOCK_ID_DISPLAY].pll_misc);
890 	udelay(2);
891 }
892 
893 /*
894  * clock_early_init_done - Check if clock_early_init() has been called
895  *
896  * Check a register that we set up to see if clock_early_init() has already
897  * been called.
898  *
899  * @return true if clock_early_init() was called, false if not
900  */
901 bool clock_early_init_done(void)
902 {
903 	struct clk_rst_ctlr *clkrst = (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
904 	u32 val;
905 
906 	val = readl(&clkrst->crc_sclk_brst_pol);
907 
908 	return val == 0x20002222;
909 }
910 
911 void arch_timer_init(void)
912 {
913 	struct sysctr_ctlr *sysctr = (struct sysctr_ctlr *)NV_PA_TSC_BASE;
914 	u32 freq, val;
915 
916 	freq = clock_get_rate(CLOCK_ID_CLK_M);
917 	debug("%s: clk_m freq is %dHz [0x%08X]\n", __func__, freq, freq);
918 
919 	/* ARM CNTFRQ */
920 	asm("mcr p15, 0, %0, c14, c0, 0\n" : : "r" (freq));
921 
922 	/* Only Tegra114+ has the System Counter regs */
923 	debug("%s: setting CNTFID0 to 0x%08X\n", __func__, freq);
924 	writel(freq, &sysctr->cntfid0);
925 
926 	val = readl(&sysctr->cntcr);
927 	val |= TSC_CNTCR_ENABLE | TSC_CNTCR_HDBG;
928 	writel(val, &sysctr->cntcr);
929 	debug("%s: TSC CNTCR = 0x%08X\n", __func__, val);
930 }
931 
932 #define PLLE_SS_CNTL 0x68
933 #define  PLLE_SS_CNTL_SSCINCINTR(x) (((x) & 0x3f) << 24)
934 #define  PLLE_SS_CNTL_SSCINC(x) (((x) & 0xff) << 16)
935 #define  PLLE_SS_CNTL_SSCINVERT (1 << 15)
936 #define  PLLE_SS_CNTL_SSCCENTER (1 << 14)
937 #define  PLLE_SS_CNTL_SSCBYP (1 << 12)
938 #define  PLLE_SS_CNTL_INTERP_RESET (1 << 11)
939 #define  PLLE_SS_CNTL_BYPASS_SS (1 << 10)
940 #define  PLLE_SS_CNTL_SSCMAX(x) (((x) & 0x1ff) << 0)
941 
942 #define PLLE_BASE 0x0e8
943 #define  PLLE_BASE_ENABLE (1 << 30)
944 #define  PLLE_BASE_LOCK_OVERRIDE (1 << 29)
945 #define  PLLE_BASE_PLDIV_CML(x) (((x) & 0xf) << 24)
946 #define  PLLE_BASE_NDIV(x) (((x) & 0xff) << 8)
947 #define  PLLE_BASE_MDIV(x) (((x) & 0xff) << 0)
948 
949 #define PLLE_MISC 0x0ec
950 #define  PLLE_MISC_IDDQ_SWCTL (1 << 14)
951 #define  PLLE_MISC_IDDQ_OVERRIDE (1 << 13)
952 #define  PLLE_MISC_LOCK_ENABLE (1 << 9)
953 #define  PLLE_MISC_PTS (1 << 8)
954 #define  PLLE_MISC_VREG_BG_CTRL(x) (((x) & 0x3) << 4)
955 #define  PLLE_MISC_VREG_CTRL(x) (((x) & 0x3) << 2)
956 
957 #define PLLE_AUX 0x48c
958 #define  PLLE_AUX_SEQ_ENABLE (1 << 24)
959 #define  PLLE_AUX_ENABLE_SWCTL (1 << 4)
960 
961 int tegra_plle_enable(void)
962 {
963 	unsigned int m = 1, n = 200, cpcon = 13;
964 	u32 value;
965 
966 	value = readl(NV_PA_CLK_RST_BASE + PLLE_BASE);
967 	value &= ~PLLE_BASE_LOCK_OVERRIDE;
968 	writel(value, NV_PA_CLK_RST_BASE + PLLE_BASE);
969 
970 	value = readl(NV_PA_CLK_RST_BASE + PLLE_AUX);
971 	value |= PLLE_AUX_ENABLE_SWCTL;
972 	value &= ~PLLE_AUX_SEQ_ENABLE;
973 	writel(value, NV_PA_CLK_RST_BASE + PLLE_AUX);
974 
975 	udelay(1);
976 
977 	value = readl(NV_PA_CLK_RST_BASE + PLLE_MISC);
978 	value |= PLLE_MISC_IDDQ_SWCTL;
979 	value &= ~PLLE_MISC_IDDQ_OVERRIDE;
980 	value |= PLLE_MISC_LOCK_ENABLE;
981 	value |= PLLE_MISC_PTS;
982 	value |= PLLE_MISC_VREG_BG_CTRL(3);
983 	value |= PLLE_MISC_VREG_CTRL(2);
984 	writel(value, NV_PA_CLK_RST_BASE + PLLE_MISC);
985 
986 	udelay(5);
987 
988 	value = readl(NV_PA_CLK_RST_BASE + PLLE_SS_CNTL);
989 	value |= PLLE_SS_CNTL_SSCBYP | PLLE_SS_CNTL_INTERP_RESET |
990 		 PLLE_SS_CNTL_BYPASS_SS;
991 	writel(value, NV_PA_CLK_RST_BASE + PLLE_SS_CNTL);
992 
993 	value = readl(NV_PA_CLK_RST_BASE + PLLE_BASE);
994 	value &= ~PLLE_BASE_PLDIV_CML(0xf);
995 	value &= ~PLLE_BASE_NDIV(0xff);
996 	value &= ~PLLE_BASE_MDIV(0xff);
997 	value |= PLLE_BASE_PLDIV_CML(cpcon);
998 	value |= PLLE_BASE_NDIV(n);
999 	value |= PLLE_BASE_MDIV(m);
1000 	writel(value, NV_PA_CLK_RST_BASE + PLLE_BASE);
1001 
1002 	udelay(1);
1003 
1004 	value = readl(NV_PA_CLK_RST_BASE + PLLE_BASE);
1005 	value |= PLLE_BASE_ENABLE;
1006 	writel(value, NV_PA_CLK_RST_BASE + PLLE_BASE);
1007 
1008 	/* wait for lock */
1009 	udelay(300);
1010 
1011 	value = readl(NV_PA_CLK_RST_BASE + PLLE_SS_CNTL);
1012 	value &= ~PLLE_SS_CNTL_SSCINVERT;
1013 	value &= ~PLLE_SS_CNTL_SSCCENTER;
1014 
1015 	value &= ~PLLE_SS_CNTL_SSCINCINTR(0x3f);
1016 	value &= ~PLLE_SS_CNTL_SSCINC(0xff);
1017 	value &= ~PLLE_SS_CNTL_SSCMAX(0x1ff);
1018 
1019 	value |= PLLE_SS_CNTL_SSCINCINTR(0x20);
1020 	value |= PLLE_SS_CNTL_SSCINC(0x01);
1021 	value |= PLLE_SS_CNTL_SSCMAX(0x25);
1022 
1023 	writel(value, NV_PA_CLK_RST_BASE + PLLE_SS_CNTL);
1024 
1025 	value = readl(NV_PA_CLK_RST_BASE + PLLE_SS_CNTL);
1026 	value &= ~PLLE_SS_CNTL_SSCBYP;
1027 	value &= ~PLLE_SS_CNTL_BYPASS_SS;
1028 	writel(value, NV_PA_CLK_RST_BASE + PLLE_SS_CNTL);
1029 
1030 	udelay(1);
1031 
1032 	value = readl(NV_PA_CLK_RST_BASE + PLLE_SS_CNTL);
1033 	value &= ~PLLE_SS_CNTL_INTERP_RESET;
1034 	writel(value, NV_PA_CLK_RST_BASE + PLLE_SS_CNTL);
1035 
1036 	udelay(1);
1037 
1038 	return 0;
1039 }
1040 
1041 void clock_sor_enable_edp_clock(void)
1042 {
1043 	u32 *reg;
1044 
1045 	/* uses PLLP, has a non-standard bit layout. */
1046 	reg = get_periph_source_reg(PERIPH_ID_SOR0);
1047 	setbits_le32(reg, SOR0_CLK_SEL0);
1048 }
1049 
1050 u32 clock_set_display_rate(u32 frequency)
1051 {
1052 	/**
1053 	 * plld (fo) = vco >> p, where 500MHz < vco < 1000MHz
1054 	 *           = (cf * n) >> p, where 1MHz < cf < 6MHz
1055 	 *           = ((ref / m) * n) >> p
1056 	 *
1057 	 * Iterate the possible values of p (3 bits, 2^7) to find out a minimum
1058 	 * safe vco, then find best (m, n). since m has only 5 bits, we can
1059 	 * iterate all possible values.  Note Tegra 124 supports 11 bits for n,
1060 	 * but our pll_fields has only 10 bits for n.
1061 	 *
1062 	 * Note values undershoot or overshoot target output frequency may not
1063 	 * work if the values are not in "safe" range by panel specification.
1064 	 */
1065 	u32 ref = clock_get_rate(CLOCK_ID_OSC);
1066 	u32 divm, divn, divp, cpcon;
1067 	u32 cf, vco, rounded_rate = frequency;
1068 	u32 diff, best_diff, best_m = 0, best_n = 0, best_p;
1069 	const u32 max_m = 1 << 5, max_n = 1 << 10, max_p = 1 << 3,
1070 		  mhz = 1000 * 1000, min_vco = 500 * mhz, max_vco = 1000 * mhz,
1071 		  min_cf = 1 * mhz, max_cf = 6 * mhz;
1072 	int mux_bits, divider_bits, source;
1073 
1074 	for (divp = 0, vco = frequency; vco < min_vco && divp < max_p; divp++)
1075 		vco <<= 1;
1076 
1077 	if (vco < min_vco || vco > max_vco) {
1078 		printf("%s: Cannot find out a supported VCO for Frequency (%u)\n",
1079 		       __func__, frequency);
1080 		return 0;
1081 	}
1082 
1083 	best_p = divp;
1084 	best_diff = vco;
1085 
1086 	for (divm = 1; divm < max_m && best_diff; divm++) {
1087 		cf = ref / divm;
1088 		if (cf < min_cf)
1089 			break;
1090 		if (cf > max_cf)
1091 			continue;
1092 
1093 		divn = vco / cf;
1094 		if (divn >= max_n)
1095 			continue;
1096 
1097 		diff = vco - divn * cf;
1098 		if (divn + 1 < max_n && diff > cf / 2) {
1099 			divn++;
1100 			diff = cf - diff;
1101 		}
1102 
1103 		if (diff >= best_diff)
1104 			continue;
1105 
1106 		best_diff = diff;
1107 		best_m = divm;
1108 		best_n = divn;
1109 	}
1110 
1111 	if (best_n < 50)
1112 		cpcon = 2;
1113 	else if (best_n < 300)
1114 		cpcon = 3;
1115 	else if (best_n < 600)
1116 		cpcon = 8;
1117 	else
1118 		cpcon = 12;
1119 
1120 	if (best_diff) {
1121 		printf("%s: Failed to match output frequency %u, best difference is %u\n",
1122 		       __func__, frequency, best_diff);
1123 		rounded_rate = (ref / best_m * best_n) >> best_p;
1124 	}
1125 
1126 	debug("%s: PLLD=%u ref=%u, m/n/p/cpcon=%u/%u/%u/%u\n",
1127 	      __func__, rounded_rate, ref, best_m, best_n, best_p, cpcon);
1128 
1129 	source = get_periph_clock_source(PERIPH_ID_DISP1, CLOCK_ID_DISPLAY,
1130 					 &mux_bits, &divider_bits);
1131 	clock_ll_set_source_bits(PERIPH_ID_DISP1, mux_bits, source);
1132 	clock_set_rate(CLOCK_ID_DISPLAY, best_n, best_m, best_p, cpcon);
1133 
1134 	return rounded_rate;
1135 }
1136 
1137 void clock_set_up_plldp(void)
1138 {
1139 	struct clk_rst_ctlr *clkrst =
1140 			(struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
1141 	u32 value;
1142 
1143 	value = PLLDP_SS_CFG_UNDOCUMENTED | PLLDP_SS_CFG_DITHER;
1144 	writel(value | PLLDP_SS_CFG_CLAMP, &clkrst->crc_plldp_ss_cfg);
1145 	clock_start_pll(CLOCK_ID_DP, 1, 90, 3, 0, 0);
1146 	writel(value, &clkrst->crc_plldp_ss_cfg);
1147 }
1148 
1149 struct clk_pll_simple *clock_get_simple_pll(enum clock_id clkid)
1150 {
1151 	struct clk_rst_ctlr *clkrst =
1152 			(struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
1153 
1154 	if (clkid == CLOCK_ID_DP)
1155 		return &clkrst->plldp;
1156 
1157 	return NULL;
1158 }
1159 
1160 struct periph_clk_init periph_clk_init_table[] = {
1161 	{ PERIPH_ID_SBC1, CLOCK_ID_PERIPH },
1162 	{ PERIPH_ID_SBC2, CLOCK_ID_PERIPH },
1163 	{ PERIPH_ID_SBC3, CLOCK_ID_PERIPH },
1164 	{ PERIPH_ID_SBC4, CLOCK_ID_PERIPH },
1165 	{ PERIPH_ID_SBC5, CLOCK_ID_PERIPH },
1166 	{ PERIPH_ID_SBC6, CLOCK_ID_PERIPH },
1167 	{ PERIPH_ID_HOST1X, CLOCK_ID_PERIPH },
1168 	{ PERIPH_ID_DISP1, CLOCK_ID_CGENERAL },
1169 	{ PERIPH_ID_SDMMC1, CLOCK_ID_PERIPH },
1170 	{ PERIPH_ID_SDMMC2, CLOCK_ID_PERIPH },
1171 	{ PERIPH_ID_SDMMC3, CLOCK_ID_PERIPH },
1172 	{ PERIPH_ID_SDMMC4, CLOCK_ID_PERIPH },
1173 	{ PERIPH_ID_PWM, CLOCK_ID_SFROM32KHZ },
1174 	{ PERIPH_ID_I2C1, CLOCK_ID_PERIPH },
1175 	{ PERIPH_ID_I2C2, CLOCK_ID_PERIPH },
1176 	{ PERIPH_ID_I2C3, CLOCK_ID_PERIPH },
1177 	{ PERIPH_ID_I2C4, CLOCK_ID_PERIPH },
1178 	{ PERIPH_ID_I2C5, CLOCK_ID_PERIPH },
1179 	{ PERIPH_ID_I2C6, CLOCK_ID_PERIPH },
1180 	{ -1, },
1181 };
1182