109f455dcSMasahiro Yamada /* 2*722e000cSTom Warren * (C) Copyright 2013-2015 309f455dcSMasahiro Yamada * NVIDIA Corporation <www.nvidia.com> 409f455dcSMasahiro Yamada * 509f455dcSMasahiro Yamada * SPDX-License-Identifier: GPL-2.0+ 609f455dcSMasahiro Yamada */ 709f455dcSMasahiro Yamada 809f455dcSMasahiro Yamada /* Tegra124 Clock control functions */ 909f455dcSMasahiro Yamada 1009f455dcSMasahiro Yamada #include <common.h> 1109f455dcSMasahiro Yamada #include <asm/io.h> 1209f455dcSMasahiro Yamada #include <asm/arch/clock.h> 1309f455dcSMasahiro Yamada #include <asm/arch/sysctr.h> 1409f455dcSMasahiro Yamada #include <asm/arch/tegra.h> 1509f455dcSMasahiro Yamada #include <asm/arch-tegra/clk_rst.h> 1609f455dcSMasahiro Yamada #include <asm/arch-tegra/timer.h> 1709f455dcSMasahiro Yamada #include <div64.h> 1809f455dcSMasahiro Yamada #include <fdtdec.h> 1909f455dcSMasahiro Yamada 2009f455dcSMasahiro Yamada /* 2109f455dcSMasahiro Yamada * Clock types that we can use as a source. The Tegra124 has muxes for the 2209f455dcSMasahiro Yamada * peripheral clocks, and in most cases there are four options for the clock 2309f455dcSMasahiro Yamada * source. This gives us a clock 'type' and exploits what commonality exists 2409f455dcSMasahiro Yamada * in the device. 2509f455dcSMasahiro Yamada * 2609f455dcSMasahiro Yamada * Letters are obvious, except for T which means CLK_M, and S which means the 2709f455dcSMasahiro Yamada * clock derived from 32KHz. Beware that CLK_M (also called OSC in the 2809f455dcSMasahiro Yamada * datasheet) and PLL_M are different things. The former is the basic 2909f455dcSMasahiro Yamada * clock supplied to the SOC from an external oscillator. The latter is the 3009f455dcSMasahiro Yamada * memory clock PLL. 3109f455dcSMasahiro Yamada * 3209f455dcSMasahiro Yamada * See definitions in clock_id in the header file. 3309f455dcSMasahiro Yamada */ 3409f455dcSMasahiro Yamada enum clock_type_id { 3509f455dcSMasahiro Yamada CLOCK_TYPE_AXPT, /* PLL_A, PLL_X, PLL_P, CLK_M */ 3609f455dcSMasahiro Yamada CLOCK_TYPE_MCPA, /* and so on */ 3709f455dcSMasahiro Yamada CLOCK_TYPE_MCPT, 3809f455dcSMasahiro Yamada CLOCK_TYPE_PCM, 3909f455dcSMasahiro Yamada CLOCK_TYPE_PCMT, 4009f455dcSMasahiro Yamada CLOCK_TYPE_PDCT, 4109f455dcSMasahiro Yamada CLOCK_TYPE_ACPT, 4209f455dcSMasahiro Yamada CLOCK_TYPE_ASPTE, 4309f455dcSMasahiro Yamada CLOCK_TYPE_PMDACD2T, 4409f455dcSMasahiro Yamada CLOCK_TYPE_PCST, 4596e82a25SSimon Glass CLOCK_TYPE_DP, 4609f455dcSMasahiro Yamada 4709f455dcSMasahiro Yamada CLOCK_TYPE_PC2CC3M, 4809f455dcSMasahiro Yamada CLOCK_TYPE_PC2CC3S_T, 4909f455dcSMasahiro Yamada CLOCK_TYPE_PC2CC3M_T, 5009f455dcSMasahiro Yamada CLOCK_TYPE_PC2CC3M_T16, /* PC2CC3M_T, but w/16-bit divisor (I2C) */ 5109f455dcSMasahiro Yamada CLOCK_TYPE_MC2CC3P_A, 5209f455dcSMasahiro Yamada CLOCK_TYPE_M, 5309f455dcSMasahiro Yamada CLOCK_TYPE_MCPTM2C2C3, 5409f455dcSMasahiro Yamada CLOCK_TYPE_PC2CC3T_S, 5509f455dcSMasahiro Yamada CLOCK_TYPE_AC2CC3P_TS2, 5609f455dcSMasahiro Yamada 5709f455dcSMasahiro Yamada CLOCK_TYPE_COUNT, 5809f455dcSMasahiro Yamada CLOCK_TYPE_NONE = -1, /* invalid clock type */ 5909f455dcSMasahiro Yamada }; 6009f455dcSMasahiro Yamada 6109f455dcSMasahiro Yamada enum { 6209f455dcSMasahiro Yamada CLOCK_MAX_MUX = 8 /* number of source options for each clock */ 6309f455dcSMasahiro Yamada }; 6409f455dcSMasahiro Yamada 6509f455dcSMasahiro Yamada /* 6609f455dcSMasahiro Yamada * Clock source mux for each clock type. This just converts our enum into 6709f455dcSMasahiro Yamada * a list of mux sources for use by the code. 6809f455dcSMasahiro Yamada * 6909f455dcSMasahiro Yamada * Note: 7009f455dcSMasahiro Yamada * The extra column in each clock source array is used to store the mask 7109f455dcSMasahiro Yamada * bits in its register for the source. 7209f455dcSMasahiro Yamada */ 7309f455dcSMasahiro Yamada #define CLK(x) CLOCK_ID_ ## x 7409f455dcSMasahiro Yamada static enum clock_id clock_source[CLOCK_TYPE_COUNT][CLOCK_MAX_MUX+1] = { 7509f455dcSMasahiro Yamada { CLK(AUDIO), CLK(XCPU), CLK(PERIPH), CLK(OSC), 7609f455dcSMasahiro Yamada CLK(NONE), CLK(NONE), CLK(NONE), CLK(NONE), 7709f455dcSMasahiro Yamada MASK_BITS_31_30}, 7809f455dcSMasahiro Yamada { CLK(MEMORY), CLK(CGENERAL), CLK(PERIPH), CLK(AUDIO), 7909f455dcSMasahiro Yamada CLK(NONE), CLK(NONE), CLK(NONE), CLK(NONE), 8009f455dcSMasahiro Yamada MASK_BITS_31_30}, 8109f455dcSMasahiro Yamada { CLK(MEMORY), CLK(CGENERAL), CLK(PERIPH), CLK(OSC), 8209f455dcSMasahiro Yamada CLK(NONE), CLK(NONE), CLK(NONE), CLK(NONE), 8309f455dcSMasahiro Yamada MASK_BITS_31_30}, 8409f455dcSMasahiro Yamada { CLK(PERIPH), CLK(CGENERAL), CLK(MEMORY), CLK(NONE), 8509f455dcSMasahiro Yamada CLK(NONE), CLK(NONE), CLK(NONE), CLK(NONE), 8609f455dcSMasahiro Yamada MASK_BITS_31_30}, 8709f455dcSMasahiro Yamada { CLK(PERIPH), CLK(CGENERAL), CLK(MEMORY), CLK(OSC), 8809f455dcSMasahiro Yamada CLK(NONE), CLK(NONE), CLK(NONE), CLK(NONE), 8909f455dcSMasahiro Yamada MASK_BITS_31_30}, 9009f455dcSMasahiro Yamada { CLK(PERIPH), CLK(DISPLAY), CLK(CGENERAL), CLK(OSC), 9109f455dcSMasahiro Yamada CLK(NONE), CLK(NONE), CLK(NONE), CLK(NONE), 9209f455dcSMasahiro Yamada MASK_BITS_31_30}, 9309f455dcSMasahiro Yamada { CLK(AUDIO), CLK(CGENERAL), CLK(PERIPH), CLK(OSC), 9409f455dcSMasahiro Yamada CLK(NONE), CLK(NONE), CLK(NONE), CLK(NONE), 9509f455dcSMasahiro Yamada MASK_BITS_31_30}, 9609f455dcSMasahiro Yamada { CLK(AUDIO), CLK(SFROM32KHZ), CLK(PERIPH), CLK(OSC), 9709f455dcSMasahiro Yamada CLK(EPCI), CLK(NONE), CLK(NONE), CLK(NONE), 9809f455dcSMasahiro Yamada MASK_BITS_31_29}, 9909f455dcSMasahiro Yamada { CLK(PERIPH), CLK(MEMORY), CLK(DISPLAY), CLK(AUDIO), 10009f455dcSMasahiro Yamada CLK(CGENERAL), CLK(DISPLAY2), CLK(OSC), CLK(NONE), 10109f455dcSMasahiro Yamada MASK_BITS_31_29}, 10209f455dcSMasahiro Yamada { CLK(PERIPH), CLK(CGENERAL), CLK(SFROM32KHZ), CLK(OSC), 10309f455dcSMasahiro Yamada CLK(NONE), CLK(NONE), CLK(NONE), CLK(NONE), 10409f455dcSMasahiro Yamada MASK_BITS_31_28}, 10596e82a25SSimon Glass /* CLOCK_TYPE_DP */ 10696e82a25SSimon Glass { CLK(NONE), CLK(NONE), CLK(NONE), CLK(NONE), 10796e82a25SSimon Glass CLK(NONE), CLK(NONE), CLK(NONE), CLK(NONE), 10896e82a25SSimon Glass MASK_BITS_31_28}, 10909f455dcSMasahiro Yamada 11009f455dcSMasahiro Yamada /* Additional clock types on Tegra114+ */ 11109f455dcSMasahiro Yamada /* CLOCK_TYPE_PC2CC3M */ 11209f455dcSMasahiro Yamada { CLK(PERIPH), CLK(CGENERAL2), CLK(CGENERAL), CLK(CGENERAL3), 11309f455dcSMasahiro Yamada CLK(MEMORY), CLK(NONE), CLK(NONE), CLK(NONE), 11409f455dcSMasahiro Yamada MASK_BITS_31_29}, 11509f455dcSMasahiro Yamada /* CLOCK_TYPE_PC2CC3S_T */ 11609f455dcSMasahiro Yamada { CLK(PERIPH), CLK(CGENERAL2), CLK(CGENERAL), CLK(CGENERAL3), 11709f455dcSMasahiro Yamada CLK(SFROM32KHZ), CLK(NONE), CLK(OSC), CLK(NONE), 11809f455dcSMasahiro Yamada MASK_BITS_31_29}, 11909f455dcSMasahiro Yamada /* CLOCK_TYPE_PC2CC3M_T */ 12009f455dcSMasahiro Yamada { CLK(PERIPH), CLK(CGENERAL2), CLK(CGENERAL), CLK(CGENERAL3), 12109f455dcSMasahiro Yamada CLK(MEMORY), CLK(NONE), CLK(OSC), CLK(NONE), 12209f455dcSMasahiro Yamada MASK_BITS_31_29}, 12309f455dcSMasahiro Yamada /* CLOCK_TYPE_PC2CC3M_T, w/16-bit divisor (I2C) */ 12409f455dcSMasahiro Yamada { CLK(PERIPH), CLK(CGENERAL2), CLK(CGENERAL), CLK(CGENERAL3), 12509f455dcSMasahiro Yamada CLK(MEMORY), CLK(NONE), CLK(OSC), CLK(NONE), 12609f455dcSMasahiro Yamada MASK_BITS_31_29}, 12709f455dcSMasahiro Yamada /* CLOCK_TYPE_MC2CC3P_A */ 12809f455dcSMasahiro Yamada { CLK(MEMORY), CLK(CGENERAL2), CLK(CGENERAL), CLK(CGENERAL3), 12909f455dcSMasahiro Yamada CLK(PERIPH), CLK(NONE), CLK(AUDIO), CLK(NONE), 13009f455dcSMasahiro Yamada MASK_BITS_31_29}, 13109f455dcSMasahiro Yamada /* CLOCK_TYPE_M */ 13209f455dcSMasahiro Yamada { CLK(MEMORY), CLK(NONE), CLK(NONE), CLK(NONE), 13309f455dcSMasahiro Yamada CLK(NONE), CLK(NONE), CLK(NONE), CLK(NONE), 13409f455dcSMasahiro Yamada MASK_BITS_31_30}, 13509f455dcSMasahiro Yamada /* CLOCK_TYPE_MCPTM2C2C3 */ 13609f455dcSMasahiro Yamada { CLK(MEMORY), CLK(CGENERAL), CLK(PERIPH), CLK(OSC), 13709f455dcSMasahiro Yamada CLK(MEMORY2), CLK(CGENERAL2), CLK(CGENERAL3), CLK(NONE), 13809f455dcSMasahiro Yamada MASK_BITS_31_29}, 13909f455dcSMasahiro Yamada /* CLOCK_TYPE_PC2CC3T_S */ 14009f455dcSMasahiro Yamada { CLK(PERIPH), CLK(CGENERAL2), CLK(CGENERAL), CLK(CGENERAL3), 14109f455dcSMasahiro Yamada CLK(OSC), CLK(NONE), CLK(SFROM32KHZ), CLK(NONE), 14209f455dcSMasahiro Yamada MASK_BITS_31_29}, 14309f455dcSMasahiro Yamada /* CLOCK_TYPE_AC2CC3P_TS2 */ 14409f455dcSMasahiro Yamada { CLK(AUDIO), CLK(CGENERAL2), CLK(CGENERAL), CLK(CGENERAL3), 14509f455dcSMasahiro Yamada CLK(PERIPH), CLK(NONE), CLK(OSC), CLK(SRC2), 14609f455dcSMasahiro Yamada MASK_BITS_31_29}, 14709f455dcSMasahiro Yamada }; 14809f455dcSMasahiro Yamada 14909f455dcSMasahiro Yamada /* 15009f455dcSMasahiro Yamada * Clock type for each peripheral clock source. We put the name in each 15109f455dcSMasahiro Yamada * record just so it is easy to match things up 15209f455dcSMasahiro Yamada */ 15309f455dcSMasahiro Yamada #define TYPE(name, type) type 15409f455dcSMasahiro Yamada static enum clock_type_id clock_periph_type[PERIPHC_COUNT] = { 15509f455dcSMasahiro Yamada /* 0x00 */ 15609f455dcSMasahiro Yamada TYPE(PERIPHC_I2S1, CLOCK_TYPE_AXPT), 15709f455dcSMasahiro Yamada TYPE(PERIPHC_I2S2, CLOCK_TYPE_AXPT), 15809f455dcSMasahiro Yamada TYPE(PERIPHC_SPDIF_OUT, CLOCK_TYPE_AXPT), 15909f455dcSMasahiro Yamada TYPE(PERIPHC_SPDIF_IN, CLOCK_TYPE_PC2CC3M), 16009f455dcSMasahiro Yamada TYPE(PERIPHC_PWM, CLOCK_TYPE_PC2CC3S_T), 16109f455dcSMasahiro Yamada TYPE(PERIPHC_05h, CLOCK_TYPE_NONE), 16209f455dcSMasahiro Yamada TYPE(PERIPHC_SBC2, CLOCK_TYPE_PC2CC3M_T), 16309f455dcSMasahiro Yamada TYPE(PERIPHC_SBC3, CLOCK_TYPE_PC2CC3M_T), 16409f455dcSMasahiro Yamada 16509f455dcSMasahiro Yamada /* 0x08 */ 16609f455dcSMasahiro Yamada TYPE(PERIPHC_08h, CLOCK_TYPE_NONE), 16709f455dcSMasahiro Yamada TYPE(PERIPHC_I2C1, CLOCK_TYPE_PC2CC3M_T16), 16809f455dcSMasahiro Yamada TYPE(PERIPHC_I2C5, CLOCK_TYPE_PC2CC3M_T16), 16909f455dcSMasahiro Yamada TYPE(PERIPHC_0bh, CLOCK_TYPE_NONE), 17009f455dcSMasahiro Yamada TYPE(PERIPHC_0ch, CLOCK_TYPE_NONE), 17109f455dcSMasahiro Yamada TYPE(PERIPHC_SBC1, CLOCK_TYPE_PC2CC3M_T), 17209f455dcSMasahiro Yamada TYPE(PERIPHC_DISP1, CLOCK_TYPE_PMDACD2T), 17309f455dcSMasahiro Yamada TYPE(PERIPHC_DISP2, CLOCK_TYPE_PMDACD2T), 17409f455dcSMasahiro Yamada 17509f455dcSMasahiro Yamada /* 0x10 */ 17609f455dcSMasahiro Yamada TYPE(PERIPHC_10h, CLOCK_TYPE_NONE), 17709f455dcSMasahiro Yamada TYPE(PERIPHC_11h, CLOCK_TYPE_NONE), 17809f455dcSMasahiro Yamada TYPE(PERIPHC_VI, CLOCK_TYPE_MC2CC3P_A), 17909f455dcSMasahiro Yamada TYPE(PERIPHC_13h, CLOCK_TYPE_NONE), 18009f455dcSMasahiro Yamada TYPE(PERIPHC_SDMMC1, CLOCK_TYPE_PC2CC3M_T), 18109f455dcSMasahiro Yamada TYPE(PERIPHC_SDMMC2, CLOCK_TYPE_PC2CC3M_T), 18209f455dcSMasahiro Yamada TYPE(PERIPHC_16h, CLOCK_TYPE_NONE), 18309f455dcSMasahiro Yamada TYPE(PERIPHC_17h, CLOCK_TYPE_NONE), 18409f455dcSMasahiro Yamada 18509f455dcSMasahiro Yamada /* 0x18 */ 18609f455dcSMasahiro Yamada TYPE(PERIPHC_18h, CLOCK_TYPE_NONE), 18709f455dcSMasahiro Yamada TYPE(PERIPHC_SDMMC4, CLOCK_TYPE_PC2CC3M_T), 18809f455dcSMasahiro Yamada TYPE(PERIPHC_VFIR, CLOCK_TYPE_PC2CC3M_T), 18909f455dcSMasahiro Yamada TYPE(PERIPHC_1Bh, CLOCK_TYPE_NONE), 19009f455dcSMasahiro Yamada TYPE(PERIPHC_1Ch, CLOCK_TYPE_NONE), 19109f455dcSMasahiro Yamada TYPE(PERIPHC_HSI, CLOCK_TYPE_PC2CC3M_T), 19209f455dcSMasahiro Yamada TYPE(PERIPHC_UART1, CLOCK_TYPE_PC2CC3M_T), 19309f455dcSMasahiro Yamada TYPE(PERIPHC_UART2, CLOCK_TYPE_PC2CC3M_T), 19409f455dcSMasahiro Yamada 19509f455dcSMasahiro Yamada /* 0x20 */ 19609f455dcSMasahiro Yamada TYPE(PERIPHC_HOST1X, CLOCK_TYPE_MC2CC3P_A), 19709f455dcSMasahiro Yamada TYPE(PERIPHC_21h, CLOCK_TYPE_NONE), 19809f455dcSMasahiro Yamada TYPE(PERIPHC_22h, CLOCK_TYPE_NONE), 19909f455dcSMasahiro Yamada TYPE(PERIPHC_HDMI, CLOCK_TYPE_PMDACD2T), 20009f455dcSMasahiro Yamada TYPE(PERIPHC_24h, CLOCK_TYPE_NONE), 20109f455dcSMasahiro Yamada TYPE(PERIPHC_25h, CLOCK_TYPE_NONE), 20209f455dcSMasahiro Yamada TYPE(PERIPHC_I2C2, CLOCK_TYPE_PC2CC3M_T16), 20309f455dcSMasahiro Yamada TYPE(PERIPHC_EMC, CLOCK_TYPE_MCPTM2C2C3), 20409f455dcSMasahiro Yamada 20509f455dcSMasahiro Yamada /* 0x28 */ 20609f455dcSMasahiro Yamada TYPE(PERIPHC_UART3, CLOCK_TYPE_PC2CC3M_T), 20709f455dcSMasahiro Yamada TYPE(PERIPHC_29h, CLOCK_TYPE_NONE), 20809f455dcSMasahiro Yamada TYPE(PERIPHC_VI_SENSOR, CLOCK_TYPE_MC2CC3P_A), 20909f455dcSMasahiro Yamada TYPE(PERIPHC_2bh, CLOCK_TYPE_NONE), 21009f455dcSMasahiro Yamada TYPE(PERIPHC_2ch, CLOCK_TYPE_NONE), 21109f455dcSMasahiro Yamada TYPE(PERIPHC_SBC4, CLOCK_TYPE_PC2CC3M_T), 21209f455dcSMasahiro Yamada TYPE(PERIPHC_I2C3, CLOCK_TYPE_PC2CC3M_T16), 21309f455dcSMasahiro Yamada TYPE(PERIPHC_SDMMC3, CLOCK_TYPE_PC2CC3M_T), 21409f455dcSMasahiro Yamada 21509f455dcSMasahiro Yamada /* 0x30 */ 21609f455dcSMasahiro Yamada TYPE(PERIPHC_UART4, CLOCK_TYPE_PC2CC3M_T), 21709f455dcSMasahiro Yamada TYPE(PERIPHC_UART5, CLOCK_TYPE_PC2CC3M_T), 21809f455dcSMasahiro Yamada TYPE(PERIPHC_VDE, CLOCK_TYPE_PC2CC3M_T), 21909f455dcSMasahiro Yamada TYPE(PERIPHC_OWR, CLOCK_TYPE_PC2CC3M_T), 22009f455dcSMasahiro Yamada TYPE(PERIPHC_NOR, CLOCK_TYPE_PC2CC3M_T), 22109f455dcSMasahiro Yamada TYPE(PERIPHC_CSITE, CLOCK_TYPE_PC2CC3M_T), 22209f455dcSMasahiro Yamada TYPE(PERIPHC_I2S0, CLOCK_TYPE_AXPT), 22309f455dcSMasahiro Yamada TYPE(PERIPHC_DTV, CLOCK_TYPE_NONE), 22409f455dcSMasahiro Yamada 22509f455dcSMasahiro Yamada /* 0x38 */ 22609f455dcSMasahiro Yamada TYPE(PERIPHC_38h, CLOCK_TYPE_NONE), 22709f455dcSMasahiro Yamada TYPE(PERIPHC_39h, CLOCK_TYPE_NONE), 22809f455dcSMasahiro Yamada TYPE(PERIPHC_3ah, CLOCK_TYPE_NONE), 22909f455dcSMasahiro Yamada TYPE(PERIPHC_3bh, CLOCK_TYPE_NONE), 23009f455dcSMasahiro Yamada TYPE(PERIPHC_MSENC, CLOCK_TYPE_MC2CC3P_A), 23109f455dcSMasahiro Yamada TYPE(PERIPHC_TSEC, CLOCK_TYPE_PC2CC3M_T), 23209f455dcSMasahiro Yamada TYPE(PERIPHC_3eh, CLOCK_TYPE_NONE), 23309f455dcSMasahiro Yamada TYPE(PERIPHC_OSC, CLOCK_TYPE_NONE), 23409f455dcSMasahiro Yamada 23509f455dcSMasahiro Yamada /* 0x40 */ 23609f455dcSMasahiro Yamada TYPE(PERIPHC_40h, CLOCK_TYPE_NONE), /* start with 0x3b0 */ 23709f455dcSMasahiro Yamada TYPE(PERIPHC_MSELECT, CLOCK_TYPE_PC2CC3M_T), 23809f455dcSMasahiro Yamada TYPE(PERIPHC_TSENSOR, CLOCK_TYPE_PC2CC3T_S), 23909f455dcSMasahiro Yamada TYPE(PERIPHC_I2S3, CLOCK_TYPE_AXPT), 24009f455dcSMasahiro Yamada TYPE(PERIPHC_I2S4, CLOCK_TYPE_AXPT), 24109f455dcSMasahiro Yamada TYPE(PERIPHC_I2C4, CLOCK_TYPE_PC2CC3M_T16), 24209f455dcSMasahiro Yamada TYPE(PERIPHC_SBC5, CLOCK_TYPE_PC2CC3M_T), 24309f455dcSMasahiro Yamada TYPE(PERIPHC_SBC6, CLOCK_TYPE_PC2CC3M_T), 24409f455dcSMasahiro Yamada 24509f455dcSMasahiro Yamada /* 0x48 */ 24609f455dcSMasahiro Yamada TYPE(PERIPHC_AUDIO, CLOCK_TYPE_AC2CC3P_TS2), 24709f455dcSMasahiro Yamada TYPE(PERIPHC_49h, CLOCK_TYPE_NONE), 24809f455dcSMasahiro Yamada TYPE(PERIPHC_DAM0, CLOCK_TYPE_AC2CC3P_TS2), 24909f455dcSMasahiro Yamada TYPE(PERIPHC_DAM1, CLOCK_TYPE_AC2CC3P_TS2), 25009f455dcSMasahiro Yamada TYPE(PERIPHC_DAM2, CLOCK_TYPE_AC2CC3P_TS2), 25109f455dcSMasahiro Yamada TYPE(PERIPHC_HDA2CODEC2X, CLOCK_TYPE_PC2CC3M_T), 25209f455dcSMasahiro Yamada TYPE(PERIPHC_ACTMON, CLOCK_TYPE_PC2CC3S_T), 25309f455dcSMasahiro Yamada TYPE(PERIPHC_EXTPERIPH1, CLOCK_TYPE_ASPTE), 25409f455dcSMasahiro Yamada 25509f455dcSMasahiro Yamada /* 0x50 */ 25609f455dcSMasahiro Yamada TYPE(PERIPHC_EXTPERIPH2, CLOCK_TYPE_ASPTE), 25709f455dcSMasahiro Yamada TYPE(PERIPHC_EXTPERIPH3, CLOCK_TYPE_ASPTE), 25809f455dcSMasahiro Yamada TYPE(PERIPHC_52h, CLOCK_TYPE_NONE), 25909f455dcSMasahiro Yamada TYPE(PERIPHC_I2CSLOW, CLOCK_TYPE_PC2CC3S_T), 26009f455dcSMasahiro Yamada TYPE(PERIPHC_SYS, CLOCK_TYPE_NONE), 26109f455dcSMasahiro Yamada TYPE(PERIPHC_55h, CLOCK_TYPE_NONE), 26209f455dcSMasahiro Yamada TYPE(PERIPHC_56h, CLOCK_TYPE_NONE), 26309f455dcSMasahiro Yamada TYPE(PERIPHC_57h, CLOCK_TYPE_NONE), 26409f455dcSMasahiro Yamada 26509f455dcSMasahiro Yamada /* 0x58 */ 26609f455dcSMasahiro Yamada TYPE(PERIPHC_58h, CLOCK_TYPE_NONE), 26796e82a25SSimon Glass TYPE(PERIPHC_SOR, CLOCK_TYPE_NONE), 26809f455dcSMasahiro Yamada TYPE(PERIPHC_5ah, CLOCK_TYPE_NONE), 26909f455dcSMasahiro Yamada TYPE(PERIPHC_5bh, CLOCK_TYPE_NONE), 27009f455dcSMasahiro Yamada TYPE(PERIPHC_SATAOOB, CLOCK_TYPE_PCMT), 27109f455dcSMasahiro Yamada TYPE(PERIPHC_SATA, CLOCK_TYPE_PCMT), 27209f455dcSMasahiro Yamada TYPE(PERIPHC_HDA, CLOCK_TYPE_PC2CC3M_T), 27309f455dcSMasahiro Yamada TYPE(PERIPHC_5fh, CLOCK_TYPE_NONE), 27409f455dcSMasahiro Yamada 27509f455dcSMasahiro Yamada /* 0x60 */ 27609f455dcSMasahiro Yamada TYPE(PERIPHC_XUSB_CORE_HOST, CLOCK_TYPE_NONE), 27709f455dcSMasahiro Yamada TYPE(PERIPHC_XUSB_FALCON, CLOCK_TYPE_NONE), 27809f455dcSMasahiro Yamada TYPE(PERIPHC_XUSB_FS, CLOCK_TYPE_NONE), 27909f455dcSMasahiro Yamada TYPE(PERIPHC_XUSB_CORE_DEV, CLOCK_TYPE_NONE), 28009f455dcSMasahiro Yamada TYPE(PERIPHC_XUSB_SS, CLOCK_TYPE_NONE), 28109f455dcSMasahiro Yamada TYPE(PERIPHC_CILAB, CLOCK_TYPE_NONE), 28209f455dcSMasahiro Yamada TYPE(PERIPHC_CILCD, CLOCK_TYPE_NONE), 28309f455dcSMasahiro Yamada TYPE(PERIPHC_CILE, CLOCK_TYPE_NONE), 28409f455dcSMasahiro Yamada 28509f455dcSMasahiro Yamada /* 0x68 */ 28609f455dcSMasahiro Yamada TYPE(PERIPHC_DSIA_LP, CLOCK_TYPE_NONE), 28709f455dcSMasahiro Yamada TYPE(PERIPHC_DSIB_LP, CLOCK_TYPE_NONE), 28809f455dcSMasahiro Yamada TYPE(PERIPHC_ENTROPY, CLOCK_TYPE_NONE), 28909f455dcSMasahiro Yamada TYPE(PERIPHC_DVFS_REF, CLOCK_TYPE_NONE), 29009f455dcSMasahiro Yamada TYPE(PERIPHC_DVFS_SOC, CLOCK_TYPE_NONE), 29109f455dcSMasahiro Yamada TYPE(PERIPHC_TRACECLKIN, CLOCK_TYPE_NONE), 29209f455dcSMasahiro Yamada TYPE(PERIPHC_ADX0, CLOCK_TYPE_NONE), 29309f455dcSMasahiro Yamada TYPE(PERIPHC_AMX0, CLOCK_TYPE_NONE), 29409f455dcSMasahiro Yamada 29509f455dcSMasahiro Yamada /* 0x70 */ 29609f455dcSMasahiro Yamada TYPE(PERIPHC_EMC_LATENCY, CLOCK_TYPE_NONE), 29709f455dcSMasahiro Yamada TYPE(PERIPHC_SOC_THERM, CLOCK_TYPE_NONE), 29809f455dcSMasahiro Yamada TYPE(PERIPHC_72h, CLOCK_TYPE_NONE), 29909f455dcSMasahiro Yamada TYPE(PERIPHC_73h, CLOCK_TYPE_NONE), 30009f455dcSMasahiro Yamada TYPE(PERIPHC_74h, CLOCK_TYPE_NONE), 30109f455dcSMasahiro Yamada TYPE(PERIPHC_75h, CLOCK_TYPE_NONE), 30209f455dcSMasahiro Yamada TYPE(PERIPHC_VI_SENSOR2, CLOCK_TYPE_NONE), 30309f455dcSMasahiro Yamada TYPE(PERIPHC_I2C6, CLOCK_TYPE_PC2CC3M_T16), 30409f455dcSMasahiro Yamada 30509f455dcSMasahiro Yamada /* 0x78 */ 30609f455dcSMasahiro Yamada TYPE(PERIPHC_78h, CLOCK_TYPE_NONE), 30709f455dcSMasahiro Yamada TYPE(PERIPHC_EMC_DLL, CLOCK_TYPE_MCPTM2C2C3), 30809f455dcSMasahiro Yamada TYPE(PERIPHC_HDMI_AUDIO, CLOCK_TYPE_NONE), 30909f455dcSMasahiro Yamada TYPE(PERIPHC_CLK72MHZ, CLOCK_TYPE_NONE), 31009f455dcSMasahiro Yamada TYPE(PERIPHC_ADX1, CLOCK_TYPE_AC2CC3P_TS2), 31109f455dcSMasahiro Yamada TYPE(PERIPHC_AMX1, CLOCK_TYPE_AC2CC3P_TS2), 31209f455dcSMasahiro Yamada TYPE(PERIPHC_VIC, CLOCK_TYPE_NONE), 31309f455dcSMasahiro Yamada TYPE(PERIPHC_7Fh, CLOCK_TYPE_NONE), 31409f455dcSMasahiro Yamada }; 31509f455dcSMasahiro Yamada 31609f455dcSMasahiro Yamada /* 31709f455dcSMasahiro Yamada * This array translates a periph_id to a periphc_internal_id 31809f455dcSMasahiro Yamada * 31909f455dcSMasahiro Yamada * Not present/matched up: 32009f455dcSMasahiro Yamada * uint vi_sensor; _VI_SENSOR_0, 0x1A8 32109f455dcSMasahiro Yamada * SPDIF - which is both 0x08 and 0x0c 32209f455dcSMasahiro Yamada * 32309f455dcSMasahiro Yamada */ 32409f455dcSMasahiro Yamada #define NONE(name) (-1) 32509f455dcSMasahiro Yamada #define OFFSET(name, value) PERIPHC_ ## name 32609f455dcSMasahiro Yamada static s8 periph_id_to_internal_id[PERIPH_ID_COUNT] = { 32709f455dcSMasahiro Yamada /* Low word: 31:0 */ 32809f455dcSMasahiro Yamada NONE(CPU), 32909f455dcSMasahiro Yamada NONE(COP), 33009f455dcSMasahiro Yamada NONE(TRIGSYS), 33109f455dcSMasahiro Yamada NONE(ISPB), 33209f455dcSMasahiro Yamada NONE(RESERVED4), 33309f455dcSMasahiro Yamada NONE(TMR), 33409f455dcSMasahiro Yamada PERIPHC_UART1, 33509f455dcSMasahiro Yamada PERIPHC_UART2, /* and vfir 0x68 */ 33609f455dcSMasahiro Yamada 33709f455dcSMasahiro Yamada /* 8 */ 33809f455dcSMasahiro Yamada NONE(GPIO), 33909f455dcSMasahiro Yamada PERIPHC_SDMMC2, 34009f455dcSMasahiro Yamada PERIPHC_SPDIF_IN, 34109f455dcSMasahiro Yamada PERIPHC_I2S1, 34209f455dcSMasahiro Yamada PERIPHC_I2C1, 34309f455dcSMasahiro Yamada NONE(RESERVED13), 34409f455dcSMasahiro Yamada PERIPHC_SDMMC1, 34509f455dcSMasahiro Yamada PERIPHC_SDMMC4, 34609f455dcSMasahiro Yamada 34709f455dcSMasahiro Yamada /* 16 */ 34809f455dcSMasahiro Yamada NONE(TCW), 34909f455dcSMasahiro Yamada PERIPHC_PWM, 35009f455dcSMasahiro Yamada PERIPHC_I2S2, 35109f455dcSMasahiro Yamada NONE(RESERVED19), 35209f455dcSMasahiro Yamada PERIPHC_VI, 35309f455dcSMasahiro Yamada NONE(RESERVED21), 35409f455dcSMasahiro Yamada NONE(USBD), 35509f455dcSMasahiro Yamada NONE(ISP), 35609f455dcSMasahiro Yamada 35709f455dcSMasahiro Yamada /* 24 */ 35809f455dcSMasahiro Yamada NONE(RESERVED24), 35909f455dcSMasahiro Yamada NONE(RESERVED25), 36009f455dcSMasahiro Yamada PERIPHC_DISP2, 36109f455dcSMasahiro Yamada PERIPHC_DISP1, 36209f455dcSMasahiro Yamada PERIPHC_HOST1X, 36309f455dcSMasahiro Yamada NONE(VCP), 36409f455dcSMasahiro Yamada PERIPHC_I2S0, 36509f455dcSMasahiro Yamada NONE(CACHE2), 36609f455dcSMasahiro Yamada 36709f455dcSMasahiro Yamada /* Middle word: 63:32 */ 36809f455dcSMasahiro Yamada NONE(MEM), 36909f455dcSMasahiro Yamada NONE(AHBDMA), 37009f455dcSMasahiro Yamada NONE(APBDMA), 37109f455dcSMasahiro Yamada NONE(RESERVED35), 37209f455dcSMasahiro Yamada NONE(RESERVED36), 37309f455dcSMasahiro Yamada NONE(STAT_MON), 37409f455dcSMasahiro Yamada NONE(RESERVED38), 37509f455dcSMasahiro Yamada NONE(FUSE), 37609f455dcSMasahiro Yamada 37709f455dcSMasahiro Yamada /* 40 */ 37809f455dcSMasahiro Yamada NONE(KFUSE), 37909f455dcSMasahiro Yamada PERIPHC_SBC1, /* SBCx = SPIx */ 38009f455dcSMasahiro Yamada PERIPHC_NOR, 38109f455dcSMasahiro Yamada NONE(RESERVED43), 38209f455dcSMasahiro Yamada PERIPHC_SBC2, 38309f455dcSMasahiro Yamada NONE(XIO), 38409f455dcSMasahiro Yamada PERIPHC_SBC3, 38509f455dcSMasahiro Yamada PERIPHC_I2C5, 38609f455dcSMasahiro Yamada 38709f455dcSMasahiro Yamada /* 48 */ 38809f455dcSMasahiro Yamada NONE(DSI), 38909f455dcSMasahiro Yamada NONE(RESERVED49), 39009f455dcSMasahiro Yamada PERIPHC_HSI, 39109f455dcSMasahiro Yamada PERIPHC_HDMI, 39209f455dcSMasahiro Yamada NONE(CSI), 39309f455dcSMasahiro Yamada NONE(RESERVED53), 39409f455dcSMasahiro Yamada PERIPHC_I2C2, 39509f455dcSMasahiro Yamada PERIPHC_UART3, 39609f455dcSMasahiro Yamada 39709f455dcSMasahiro Yamada /* 56 */ 39809f455dcSMasahiro Yamada NONE(MIPI_CAL), 39909f455dcSMasahiro Yamada PERIPHC_EMC, 40009f455dcSMasahiro Yamada NONE(USB2), 40109f455dcSMasahiro Yamada NONE(USB3), 40209f455dcSMasahiro Yamada NONE(RESERVED60), 40309f455dcSMasahiro Yamada PERIPHC_VDE, 40409f455dcSMasahiro Yamada NONE(BSEA), 40509f455dcSMasahiro Yamada NONE(BSEV), 40609f455dcSMasahiro Yamada 40709f455dcSMasahiro Yamada /* Upper word 95:64 */ 40809f455dcSMasahiro Yamada NONE(RESERVED64), 40909f455dcSMasahiro Yamada PERIPHC_UART4, 41009f455dcSMasahiro Yamada PERIPHC_UART5, 41109f455dcSMasahiro Yamada PERIPHC_I2C3, 41209f455dcSMasahiro Yamada PERIPHC_SBC4, 41309f455dcSMasahiro Yamada PERIPHC_SDMMC3, 41409f455dcSMasahiro Yamada NONE(PCIE), 41509f455dcSMasahiro Yamada PERIPHC_OWR, 41609f455dcSMasahiro Yamada 41709f455dcSMasahiro Yamada /* 72 */ 41809f455dcSMasahiro Yamada NONE(AFI), 41909f455dcSMasahiro Yamada PERIPHC_CSITE, 42009f455dcSMasahiro Yamada NONE(PCIEXCLK), 42109f455dcSMasahiro Yamada NONE(AVPUCQ), 42209f455dcSMasahiro Yamada NONE(LA), 42309f455dcSMasahiro Yamada NONE(TRACECLKIN), 42409f455dcSMasahiro Yamada NONE(SOC_THERM), 42509f455dcSMasahiro Yamada NONE(DTV), 42609f455dcSMasahiro Yamada 42709f455dcSMasahiro Yamada /* 80 */ 42809f455dcSMasahiro Yamada NONE(RESERVED80), 42909f455dcSMasahiro Yamada PERIPHC_I2CSLOW, 43009f455dcSMasahiro Yamada NONE(DSIB), 43109f455dcSMasahiro Yamada PERIPHC_TSEC, 43209f455dcSMasahiro Yamada NONE(RESERVED84), 43309f455dcSMasahiro Yamada NONE(RESERVED85), 43409f455dcSMasahiro Yamada NONE(RESERVED86), 43509f455dcSMasahiro Yamada NONE(EMUCIF), 43609f455dcSMasahiro Yamada 43709f455dcSMasahiro Yamada /* 88 */ 43809f455dcSMasahiro Yamada NONE(RESERVED88), 43909f455dcSMasahiro Yamada NONE(XUSB_HOST), 44009f455dcSMasahiro Yamada NONE(RESERVED90), 44109f455dcSMasahiro Yamada PERIPHC_MSENC, 44209f455dcSMasahiro Yamada NONE(RESERVED92), 44309f455dcSMasahiro Yamada NONE(RESERVED93), 44409f455dcSMasahiro Yamada NONE(RESERVED94), 44509f455dcSMasahiro Yamada NONE(XUSB_DEV), 44609f455dcSMasahiro Yamada 44709f455dcSMasahiro Yamada /* V word: 31:0 */ 44809f455dcSMasahiro Yamada NONE(CPUG), 44909f455dcSMasahiro Yamada NONE(CPULP), 45009f455dcSMasahiro Yamada NONE(V_RESERVED2), 45109f455dcSMasahiro Yamada PERIPHC_MSELECT, 45209f455dcSMasahiro Yamada NONE(V_RESERVED4), 45309f455dcSMasahiro Yamada PERIPHC_I2S3, 45409f455dcSMasahiro Yamada PERIPHC_I2S4, 45509f455dcSMasahiro Yamada PERIPHC_I2C4, 45609f455dcSMasahiro Yamada 45709f455dcSMasahiro Yamada /* 104 */ 45809f455dcSMasahiro Yamada PERIPHC_SBC5, 45909f455dcSMasahiro Yamada PERIPHC_SBC6, 46009f455dcSMasahiro Yamada PERIPHC_AUDIO, 46109f455dcSMasahiro Yamada NONE(APBIF), 46209f455dcSMasahiro Yamada PERIPHC_DAM0, 46309f455dcSMasahiro Yamada PERIPHC_DAM1, 46409f455dcSMasahiro Yamada PERIPHC_DAM2, 46509f455dcSMasahiro Yamada PERIPHC_HDA2CODEC2X, 46609f455dcSMasahiro Yamada 46709f455dcSMasahiro Yamada /* 112 */ 46809f455dcSMasahiro Yamada NONE(ATOMICS), 46909f455dcSMasahiro Yamada NONE(V_RESERVED17), 47009f455dcSMasahiro Yamada NONE(V_RESERVED18), 47109f455dcSMasahiro Yamada NONE(V_RESERVED19), 47209f455dcSMasahiro Yamada NONE(V_RESERVED20), 47309f455dcSMasahiro Yamada NONE(V_RESERVED21), 47409f455dcSMasahiro Yamada NONE(V_RESERVED22), 47509f455dcSMasahiro Yamada PERIPHC_ACTMON, 47609f455dcSMasahiro Yamada 47709f455dcSMasahiro Yamada /* 120 */ 478057772b7SSimon Glass PERIPHC_EXTPERIPH1, 47909f455dcSMasahiro Yamada NONE(EXTPERIPH2), 48009f455dcSMasahiro Yamada NONE(EXTPERIPH3), 48109f455dcSMasahiro Yamada NONE(OOB), 48209f455dcSMasahiro Yamada PERIPHC_SATA, 48309f455dcSMasahiro Yamada PERIPHC_HDA, 48409f455dcSMasahiro Yamada NONE(TZRAM), 48509f455dcSMasahiro Yamada NONE(SE), 48609f455dcSMasahiro Yamada 48709f455dcSMasahiro Yamada /* W word: 31:0 */ 48809f455dcSMasahiro Yamada NONE(HDA2HDMICODEC), 48909f455dcSMasahiro Yamada NONE(SATACOLD), 49009f455dcSMasahiro Yamada NONE(W_RESERVED2), 49109f455dcSMasahiro Yamada NONE(W_RESERVED3), 49209f455dcSMasahiro Yamada NONE(W_RESERVED4), 49309f455dcSMasahiro Yamada NONE(W_RESERVED5), 49409f455dcSMasahiro Yamada NONE(W_RESERVED6), 49509f455dcSMasahiro Yamada NONE(W_RESERVED7), 49609f455dcSMasahiro Yamada 49709f455dcSMasahiro Yamada /* 136 */ 49809f455dcSMasahiro Yamada NONE(CEC), 49909f455dcSMasahiro Yamada NONE(W_RESERVED9), 50009f455dcSMasahiro Yamada NONE(W_RESERVED10), 50109f455dcSMasahiro Yamada NONE(W_RESERVED11), 50209f455dcSMasahiro Yamada NONE(W_RESERVED12), 50309f455dcSMasahiro Yamada NONE(W_RESERVED13), 50409f455dcSMasahiro Yamada NONE(XUSB_PADCTL), 50509f455dcSMasahiro Yamada NONE(W_RESERVED15), 50609f455dcSMasahiro Yamada 50709f455dcSMasahiro Yamada /* 144 */ 50809f455dcSMasahiro Yamada NONE(W_RESERVED16), 50909f455dcSMasahiro Yamada NONE(W_RESERVED17), 51009f455dcSMasahiro Yamada NONE(W_RESERVED18), 51109f455dcSMasahiro Yamada NONE(W_RESERVED19), 51209f455dcSMasahiro Yamada NONE(W_RESERVED20), 51309f455dcSMasahiro Yamada NONE(ENTROPY), 51409f455dcSMasahiro Yamada NONE(DDS), 51509f455dcSMasahiro Yamada NONE(W_RESERVED23), 51609f455dcSMasahiro Yamada 51709f455dcSMasahiro Yamada /* 152 */ 51809f455dcSMasahiro Yamada NONE(DP2), 51909f455dcSMasahiro Yamada NONE(AMX0), 52009f455dcSMasahiro Yamada NONE(ADX0), 52109f455dcSMasahiro Yamada NONE(DVFS), 52209f455dcSMasahiro Yamada NONE(XUSB_SS), 52309f455dcSMasahiro Yamada NONE(W_RESERVED29), 52409f455dcSMasahiro Yamada NONE(W_RESERVED30), 52509f455dcSMasahiro Yamada NONE(W_RESERVED31), 52609f455dcSMasahiro Yamada 52709f455dcSMasahiro Yamada /* X word: 31:0 */ 52809f455dcSMasahiro Yamada NONE(SPARE), 52909f455dcSMasahiro Yamada NONE(X_RESERVED1), 53009f455dcSMasahiro Yamada NONE(X_RESERVED2), 53109f455dcSMasahiro Yamada NONE(X_RESERVED3), 53209f455dcSMasahiro Yamada NONE(CAM_MCLK), 53309f455dcSMasahiro Yamada NONE(CAM_MCLK2), 53409f455dcSMasahiro Yamada PERIPHC_I2C6, 53509f455dcSMasahiro Yamada NONE(X_RESERVED7), 53609f455dcSMasahiro Yamada 53709f455dcSMasahiro Yamada /* 168 */ 53809f455dcSMasahiro Yamada NONE(X_RESERVED8), 53909f455dcSMasahiro Yamada NONE(X_RESERVED9), 54009f455dcSMasahiro Yamada NONE(X_RESERVED10), 54109f455dcSMasahiro Yamada NONE(VIM2_CLK), 54209f455dcSMasahiro Yamada NONE(X_RESERVED12), 54309f455dcSMasahiro Yamada NONE(X_RESERVED13), 54409f455dcSMasahiro Yamada NONE(EMC_DLL), 54509f455dcSMasahiro Yamada NONE(X_RESERVED15), 54609f455dcSMasahiro Yamada 54709f455dcSMasahiro Yamada /* 176 */ 54809f455dcSMasahiro Yamada NONE(HDMI_AUDIO), 54909f455dcSMasahiro Yamada NONE(CLK72MHZ), 55009f455dcSMasahiro Yamada NONE(VIC), 55109f455dcSMasahiro Yamada NONE(X_RESERVED19), 55209f455dcSMasahiro Yamada NONE(ADX1), 55309f455dcSMasahiro Yamada NONE(DPAUX), 55496e82a25SSimon Glass PERIPHC_SOR, 55509f455dcSMasahiro Yamada NONE(X_RESERVED23), 55609f455dcSMasahiro Yamada 55709f455dcSMasahiro Yamada /* 184 */ 55809f455dcSMasahiro Yamada NONE(GPU), 55909f455dcSMasahiro Yamada NONE(AMX1), 56009f455dcSMasahiro Yamada NONE(X_RESERVED26), 56109f455dcSMasahiro Yamada NONE(X_RESERVED27), 56209f455dcSMasahiro Yamada NONE(X_RESERVED28), 56309f455dcSMasahiro Yamada NONE(X_RESERVED29), 56409f455dcSMasahiro Yamada NONE(X_RESERVED30), 56509f455dcSMasahiro Yamada NONE(X_RESERVED31), 56609f455dcSMasahiro Yamada }; 56709f455dcSMasahiro Yamada 56809f455dcSMasahiro Yamada /* 569*722e000cSTom Warren * PLL divider shift/mask tables for all PLL IDs. 570*722e000cSTom Warren */ 571*722e000cSTom Warren struct clk_pll_info tegra_pll_info_table[CLOCK_ID_PLL_COUNT] = { 572*722e000cSTom Warren /* 573*722e000cSTom Warren * T124: same as T114, some deviations from T2x/T30. 574*722e000cSTom Warren * NOTE: If kcp_mask/kvco_mask == 0, they're not used in that PLL (PLLX, etc.) 575*722e000cSTom Warren * If lock_ena or lock_det are >31, they're not used in that PLL. 576*722e000cSTom Warren */ 577*722e000cSTom Warren 578*722e000cSTom Warren { .m_shift = 0, .m_mask = 0xFF, .n_shift = 8, .n_mask = 0xFF, .p_shift = 20, .p_mask = 0x0F, 579*722e000cSTom Warren .lock_ena = 24, .lock_det = 27, .kcp_shift = 28, .kcp_mask = 3, .kvco_shift = 27, .kvco_mask = 1 }, /* PLLC */ 580*722e000cSTom Warren { .m_shift = 0, .m_mask = 0xFF, .n_shift = 8, .n_mask = 0xFF, .p_shift = 0, .p_mask = 0, 581*722e000cSTom Warren .lock_ena = 0, .lock_det = 27, .kcp_shift = 1, .kcp_mask = 3, .kvco_shift = 0, .kvco_mask = 1 }, /* PLLM */ 582*722e000cSTom Warren { .m_shift = 0, .m_mask = 0x1F, .n_shift = 8, .n_mask = 0x3FF, .p_shift = 20, .p_mask = 0x07, 583*722e000cSTom Warren .lock_ena = 18, .lock_det = 27, .kcp_shift = 8, .kcp_mask = 0xF, .kvco_shift = 4, .kvco_mask = 0xF }, /* PLLP */ 584*722e000cSTom Warren { .m_shift = 0, .m_mask = 0x1F, .n_shift = 8, .n_mask = 0x3FF, .p_shift = 20, .p_mask = 0x07, 585*722e000cSTom Warren .lock_ena = 18, .lock_det = 27, .kcp_shift = 8, .kcp_mask = 0xF, .kvco_shift = 4, .kvco_mask = 0xF }, /* PLLA */ 586*722e000cSTom Warren { .m_shift = 0, .m_mask = 0x1F, .n_shift = 8, .n_mask = 0x3FF, .p_shift = 20, .p_mask = 0x01, 587*722e000cSTom Warren .lock_ena = 22, .lock_det = 27, .kcp_shift = 8, .kcp_mask = 0xF, .kvco_shift = 4, .kvco_mask = 0xF }, /* PLLU */ 588*722e000cSTom Warren { .m_shift = 0, .m_mask = 0x1F, .n_shift = 8, .n_mask = 0x3FF, .p_shift = 20, .p_mask = 0x07, 589*722e000cSTom Warren .lock_ena = 22, .lock_det = 27, .kcp_shift = 8, .kcp_mask = 0xF, .kvco_shift = 4, .kvco_mask = 0xF }, /* PLLD */ 590*722e000cSTom Warren { .m_shift = 0, .m_mask = 0xFF, .n_shift = 8, .n_mask = 0xFF, .p_shift = 20, .p_mask = 0x0F, 591*722e000cSTom Warren .lock_ena = 18, .lock_det = 27, .kcp_shift = 0, .kcp_mask = 0, .kvco_shift = 0, .kvco_mask = 0 }, /* PLLX */ 592*722e000cSTom Warren { .m_shift = 0, .m_mask = 0xFF, .n_shift = 8, .n_mask = 0xFF, .p_shift = 0, .p_mask = 0, 593*722e000cSTom Warren .lock_ena = 9, .lock_det = 11, .kcp_shift = 6, .kcp_mask = 3, .kvco_shift = 0, .kvco_mask = 1 }, /* PLLE */ 594*722e000cSTom Warren { .m_shift = 0, .m_mask = 0x0F, .n_shift = 8, .n_mask = 0x3FF, .p_shift = 20, .p_mask = 0x07, 595*722e000cSTom Warren .lock_ena = 18, .lock_det = 27, .kcp_shift = 8, .kcp_mask = 0xF, .kvco_shift = 4, .kvco_mask = 0xF }, /* PLLS (RESERVED) */ 596*722e000cSTom Warren }; 597*722e000cSTom Warren 598*722e000cSTom Warren /* 59909f455dcSMasahiro Yamada * Get the oscillator frequency, from the corresponding hardware configuration 60009f455dcSMasahiro Yamada * field. Note that Tegra30+ support 3 new higher freqs, but we map back 60109f455dcSMasahiro Yamada * to the old T20 freqs. Support for the higher oscillators is TBD. 60209f455dcSMasahiro Yamada */ 60309f455dcSMasahiro Yamada enum clock_osc_freq clock_get_osc_freq(void) 60409f455dcSMasahiro Yamada { 60509f455dcSMasahiro Yamada struct clk_rst_ctlr *clkrst = 60609f455dcSMasahiro Yamada (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE; 60709f455dcSMasahiro Yamada u32 reg; 60809f455dcSMasahiro Yamada 60909f455dcSMasahiro Yamada reg = readl(&clkrst->crc_osc_ctrl); 61009f455dcSMasahiro Yamada reg = (reg & OSC_FREQ_MASK) >> OSC_FREQ_SHIFT; 61109f455dcSMasahiro Yamada 61209f455dcSMasahiro Yamada if (reg & 1) /* one of the newer freqs */ 61309f455dcSMasahiro Yamada printf("Warning: OSC_FREQ is unsupported! (%d)\n", reg); 61409f455dcSMasahiro Yamada 61509f455dcSMasahiro Yamada return reg >> 2; /* Map to most common (T20) freqs */ 61609f455dcSMasahiro Yamada } 61709f455dcSMasahiro Yamada 61809f455dcSMasahiro Yamada /* Returns a pointer to the clock source register for a peripheral */ 61909f455dcSMasahiro Yamada u32 *get_periph_source_reg(enum periph_id periph_id) 62009f455dcSMasahiro Yamada { 62109f455dcSMasahiro Yamada struct clk_rst_ctlr *clkrst = 62209f455dcSMasahiro Yamada (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE; 62309f455dcSMasahiro Yamada enum periphc_internal_id internal_id; 62409f455dcSMasahiro Yamada 62509f455dcSMasahiro Yamada /* Coresight is a special case */ 62609f455dcSMasahiro Yamada if (periph_id == PERIPH_ID_CSI) 62709f455dcSMasahiro Yamada return &clkrst->crc_clk_src[PERIPH_ID_CSI+1]; 62809f455dcSMasahiro Yamada 62909f455dcSMasahiro Yamada assert(periph_id >= PERIPH_ID_FIRST && periph_id < PERIPH_ID_COUNT); 63009f455dcSMasahiro Yamada internal_id = periph_id_to_internal_id[periph_id]; 63109f455dcSMasahiro Yamada assert(internal_id != -1); 63296e82a25SSimon Glass if (internal_id >= PERIPHC_X_FIRST) { 63396e82a25SSimon Glass internal_id -= PERIPHC_X_FIRST; 63496e82a25SSimon Glass return &clkrst->crc_clk_src_x[internal_id]; 63596e82a25SSimon Glass } else if (internal_id >= PERIPHC_VW_FIRST) { 63609f455dcSMasahiro Yamada internal_id -= PERIPHC_VW_FIRST; 63709f455dcSMasahiro Yamada return &clkrst->crc_clk_src_vw[internal_id]; 63809f455dcSMasahiro Yamada } else { 63909f455dcSMasahiro Yamada return &clkrst->crc_clk_src[internal_id]; 64009f455dcSMasahiro Yamada } 64109f455dcSMasahiro Yamada } 64209f455dcSMasahiro Yamada 64309f455dcSMasahiro Yamada /** 64409f455dcSMasahiro Yamada * Given a peripheral ID and the required source clock, this returns which 64509f455dcSMasahiro Yamada * value should be programmed into the source mux for that peripheral. 64609f455dcSMasahiro Yamada * 64709f455dcSMasahiro Yamada * There is special code here to handle the one source type with 5 sources. 64809f455dcSMasahiro Yamada * 64909f455dcSMasahiro Yamada * @param periph_id peripheral to start 65009f455dcSMasahiro Yamada * @param source PLL id of required parent clock 65109f455dcSMasahiro Yamada * @param mux_bits Set to number of bits in mux register: 2 or 4 65209f455dcSMasahiro Yamada * @param divider_bits Set to number of divider bits (8 or 16) 65309f455dcSMasahiro Yamada * @return mux value (0-4, or -1 if not found) 65409f455dcSMasahiro Yamada */ 65509f455dcSMasahiro Yamada int get_periph_clock_source(enum periph_id periph_id, 65609f455dcSMasahiro Yamada enum clock_id parent, int *mux_bits, int *divider_bits) 65709f455dcSMasahiro Yamada { 65809f455dcSMasahiro Yamada enum clock_type_id type; 65909f455dcSMasahiro Yamada enum periphc_internal_id internal_id; 66009f455dcSMasahiro Yamada int mux; 66109f455dcSMasahiro Yamada 66209f455dcSMasahiro Yamada assert(clock_periph_id_isvalid(periph_id)); 66309f455dcSMasahiro Yamada 66409f455dcSMasahiro Yamada internal_id = periph_id_to_internal_id[periph_id]; 66509f455dcSMasahiro Yamada assert(periphc_internal_id_isvalid(internal_id)); 66609f455dcSMasahiro Yamada 66709f455dcSMasahiro Yamada type = clock_periph_type[internal_id]; 66809f455dcSMasahiro Yamada assert(clock_type_id_isvalid(type)); 66909f455dcSMasahiro Yamada 67009f455dcSMasahiro Yamada *mux_bits = clock_source[type][CLOCK_MAX_MUX]; 67109f455dcSMasahiro Yamada 67209f455dcSMasahiro Yamada if (type == CLOCK_TYPE_PC2CC3M_T16) 67309f455dcSMasahiro Yamada *divider_bits = 16; 67409f455dcSMasahiro Yamada else 67509f455dcSMasahiro Yamada *divider_bits = 8; 67609f455dcSMasahiro Yamada 67709f455dcSMasahiro Yamada for (mux = 0; mux < CLOCK_MAX_MUX; mux++) 67809f455dcSMasahiro Yamada if (clock_source[type][mux] == parent) 67909f455dcSMasahiro Yamada return mux; 68009f455dcSMasahiro Yamada 68109f455dcSMasahiro Yamada /* if we get here, either us or the caller has made a mistake */ 68209f455dcSMasahiro Yamada printf("Caller requested bad clock: periph=%d, parent=%d\n", periph_id, 68309f455dcSMasahiro Yamada parent); 68409f455dcSMasahiro Yamada return -1; 68509f455dcSMasahiro Yamada } 68609f455dcSMasahiro Yamada 68709f455dcSMasahiro Yamada void clock_set_enable(enum periph_id periph_id, int enable) 68809f455dcSMasahiro Yamada { 68909f455dcSMasahiro Yamada struct clk_rst_ctlr *clkrst = 69009f455dcSMasahiro Yamada (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE; 69109f455dcSMasahiro Yamada u32 *clk; 69209f455dcSMasahiro Yamada u32 reg; 69309f455dcSMasahiro Yamada 69409f455dcSMasahiro Yamada /* Enable/disable the clock to this peripheral */ 69509f455dcSMasahiro Yamada assert(clock_periph_id_isvalid(periph_id)); 69609f455dcSMasahiro Yamada if ((int)periph_id < (int)PERIPH_ID_VW_FIRST) 69709f455dcSMasahiro Yamada clk = &clkrst->crc_clk_out_enb[PERIPH_REG(periph_id)]; 69896e82a25SSimon Glass else if ((int)periph_id < PERIPH_ID_X_FIRST) 69909f455dcSMasahiro Yamada clk = &clkrst->crc_clk_out_enb_vw[PERIPH_REG(periph_id)]; 70096e82a25SSimon Glass else 70196e82a25SSimon Glass clk = &clkrst->crc_clk_out_enb_x; 70209f455dcSMasahiro Yamada reg = readl(clk); 70309f455dcSMasahiro Yamada if (enable) 70409f455dcSMasahiro Yamada reg |= PERIPH_MASK(periph_id); 70509f455dcSMasahiro Yamada else 70609f455dcSMasahiro Yamada reg &= ~PERIPH_MASK(periph_id); 70709f455dcSMasahiro Yamada writel(reg, clk); 70809f455dcSMasahiro Yamada } 70909f455dcSMasahiro Yamada 71009f455dcSMasahiro Yamada void reset_set_enable(enum periph_id periph_id, int enable) 71109f455dcSMasahiro Yamada { 71209f455dcSMasahiro Yamada struct clk_rst_ctlr *clkrst = 71309f455dcSMasahiro Yamada (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE; 71409f455dcSMasahiro Yamada u32 *reset; 71509f455dcSMasahiro Yamada u32 reg; 71609f455dcSMasahiro Yamada 71709f455dcSMasahiro Yamada /* Enable/disable reset to the peripheral */ 71809f455dcSMasahiro Yamada assert(clock_periph_id_isvalid(periph_id)); 71909f455dcSMasahiro Yamada if (periph_id < PERIPH_ID_VW_FIRST) 72009f455dcSMasahiro Yamada reset = &clkrst->crc_rst_dev[PERIPH_REG(periph_id)]; 72196e82a25SSimon Glass else if ((int)periph_id < PERIPH_ID_X_FIRST) 72209f455dcSMasahiro Yamada reset = &clkrst->crc_rst_dev_vw[PERIPH_REG(periph_id)]; 72396e82a25SSimon Glass else 72496e82a25SSimon Glass reset = &clkrst->crc_rst_devices_x; 72509f455dcSMasahiro Yamada reg = readl(reset); 72609f455dcSMasahiro Yamada if (enable) 72709f455dcSMasahiro Yamada reg |= PERIPH_MASK(periph_id); 72809f455dcSMasahiro Yamada else 72909f455dcSMasahiro Yamada reg &= ~PERIPH_MASK(periph_id); 73009f455dcSMasahiro Yamada writel(reg, reset); 73109f455dcSMasahiro Yamada } 73209f455dcSMasahiro Yamada 73309f455dcSMasahiro Yamada #ifdef CONFIG_OF_CONTROL 73409f455dcSMasahiro Yamada /* 73509f455dcSMasahiro Yamada * Convert a device tree clock ID to our peripheral ID. They are mostly 73609f455dcSMasahiro Yamada * the same but we are very cautious so we check that a valid clock ID is 73709f455dcSMasahiro Yamada * provided. 73809f455dcSMasahiro Yamada * 73909f455dcSMasahiro Yamada * @param clk_id Clock ID according to tegra124 device tree binding 74009f455dcSMasahiro Yamada * @return peripheral ID, or PERIPH_ID_NONE if the clock ID is invalid 74109f455dcSMasahiro Yamada */ 74209f455dcSMasahiro Yamada enum periph_id clk_id_to_periph_id(int clk_id) 74309f455dcSMasahiro Yamada { 74409f455dcSMasahiro Yamada if (clk_id > PERIPH_ID_COUNT) 74509f455dcSMasahiro Yamada return PERIPH_ID_NONE; 74609f455dcSMasahiro Yamada 74709f455dcSMasahiro Yamada switch (clk_id) { 74809f455dcSMasahiro Yamada case PERIPH_ID_RESERVED4: 74909f455dcSMasahiro Yamada case PERIPH_ID_RESERVED25: 75009f455dcSMasahiro Yamada case PERIPH_ID_RESERVED35: 75109f455dcSMasahiro Yamada case PERIPH_ID_RESERVED36: 75209f455dcSMasahiro Yamada case PERIPH_ID_RESERVED38: 75309f455dcSMasahiro Yamada case PERIPH_ID_RESERVED43: 75409f455dcSMasahiro Yamada case PERIPH_ID_RESERVED49: 75509f455dcSMasahiro Yamada case PERIPH_ID_RESERVED53: 75609f455dcSMasahiro Yamada case PERIPH_ID_RESERVED64: 75709f455dcSMasahiro Yamada case PERIPH_ID_RESERVED84: 75809f455dcSMasahiro Yamada case PERIPH_ID_RESERVED85: 75909f455dcSMasahiro Yamada case PERIPH_ID_RESERVED86: 76009f455dcSMasahiro Yamada case PERIPH_ID_RESERVED88: 76109f455dcSMasahiro Yamada case PERIPH_ID_RESERVED90: 76209f455dcSMasahiro Yamada case PERIPH_ID_RESERVED92: 76309f455dcSMasahiro Yamada case PERIPH_ID_RESERVED93: 76409f455dcSMasahiro Yamada case PERIPH_ID_RESERVED94: 76509f455dcSMasahiro Yamada case PERIPH_ID_V_RESERVED2: 76609f455dcSMasahiro Yamada case PERIPH_ID_V_RESERVED4: 76709f455dcSMasahiro Yamada case PERIPH_ID_V_RESERVED17: 76809f455dcSMasahiro Yamada case PERIPH_ID_V_RESERVED18: 76909f455dcSMasahiro Yamada case PERIPH_ID_V_RESERVED19: 77009f455dcSMasahiro Yamada case PERIPH_ID_V_RESERVED20: 77109f455dcSMasahiro Yamada case PERIPH_ID_V_RESERVED21: 77209f455dcSMasahiro Yamada case PERIPH_ID_V_RESERVED22: 77309f455dcSMasahiro Yamada case PERIPH_ID_W_RESERVED2: 77409f455dcSMasahiro Yamada case PERIPH_ID_W_RESERVED3: 77509f455dcSMasahiro Yamada case PERIPH_ID_W_RESERVED4: 77609f455dcSMasahiro Yamada case PERIPH_ID_W_RESERVED5: 77709f455dcSMasahiro Yamada case PERIPH_ID_W_RESERVED6: 77809f455dcSMasahiro Yamada case PERIPH_ID_W_RESERVED7: 77909f455dcSMasahiro Yamada case PERIPH_ID_W_RESERVED9: 78009f455dcSMasahiro Yamada case PERIPH_ID_W_RESERVED10: 78109f455dcSMasahiro Yamada case PERIPH_ID_W_RESERVED11: 78209f455dcSMasahiro Yamada case PERIPH_ID_W_RESERVED12: 78309f455dcSMasahiro Yamada case PERIPH_ID_W_RESERVED13: 78409f455dcSMasahiro Yamada case PERIPH_ID_W_RESERVED15: 78509f455dcSMasahiro Yamada case PERIPH_ID_W_RESERVED16: 78609f455dcSMasahiro Yamada case PERIPH_ID_W_RESERVED17: 78709f455dcSMasahiro Yamada case PERIPH_ID_W_RESERVED18: 78809f455dcSMasahiro Yamada case PERIPH_ID_W_RESERVED19: 78909f455dcSMasahiro Yamada case PERIPH_ID_W_RESERVED20: 79009f455dcSMasahiro Yamada case PERIPH_ID_W_RESERVED23: 79109f455dcSMasahiro Yamada case PERIPH_ID_W_RESERVED29: 79209f455dcSMasahiro Yamada case PERIPH_ID_W_RESERVED30: 79309f455dcSMasahiro Yamada case PERIPH_ID_W_RESERVED31: 79409f455dcSMasahiro Yamada return PERIPH_ID_NONE; 79509f455dcSMasahiro Yamada default: 79609f455dcSMasahiro Yamada return clk_id; 79709f455dcSMasahiro Yamada } 79809f455dcSMasahiro Yamada } 79909f455dcSMasahiro Yamada #endif /* CONFIG_OF_CONTROL */ 80009f455dcSMasahiro Yamada 80109f455dcSMasahiro Yamada void clock_early_init(void) 80209f455dcSMasahiro Yamada { 80309f455dcSMasahiro Yamada struct clk_rst_ctlr *clkrst = 80409f455dcSMasahiro Yamada (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE; 805*722e000cSTom Warren struct clk_pll_info *pllinfo; 806*722e000cSTom Warren u32 data; 80709f455dcSMasahiro Yamada 80809f455dcSMasahiro Yamada tegra30_set_up_pllp(); 80909f455dcSMasahiro Yamada 81009f455dcSMasahiro Yamada /* 81109f455dcSMasahiro Yamada * PLLC output frequency set to 600Mhz 81209f455dcSMasahiro Yamada * PLLD output frequency set to 925Mhz 81309f455dcSMasahiro Yamada */ 81409f455dcSMasahiro Yamada switch (clock_get_osc_freq()) { 81509f455dcSMasahiro Yamada case CLOCK_OSC_FREQ_12_0: /* OSC is 12Mhz */ 81609f455dcSMasahiro Yamada clock_set_rate(CLOCK_ID_CGENERAL, 600, 12, 0, 8); 81709f455dcSMasahiro Yamada clock_set_rate(CLOCK_ID_DISPLAY, 925, 12, 0, 12); 81809f455dcSMasahiro Yamada break; 81909f455dcSMasahiro Yamada 82009f455dcSMasahiro Yamada case CLOCK_OSC_FREQ_26_0: /* OSC is 26Mhz */ 82109f455dcSMasahiro Yamada clock_set_rate(CLOCK_ID_CGENERAL, 600, 26, 0, 8); 82209f455dcSMasahiro Yamada clock_set_rate(CLOCK_ID_DISPLAY, 925, 26, 0, 12); 82309f455dcSMasahiro Yamada break; 82409f455dcSMasahiro Yamada 82509f455dcSMasahiro Yamada case CLOCK_OSC_FREQ_13_0: /* OSC is 13Mhz */ 82609f455dcSMasahiro Yamada clock_set_rate(CLOCK_ID_CGENERAL, 600, 13, 0, 8); 82709f455dcSMasahiro Yamada clock_set_rate(CLOCK_ID_DISPLAY, 925, 13, 0, 12); 82809f455dcSMasahiro Yamada break; 82909f455dcSMasahiro Yamada case CLOCK_OSC_FREQ_19_2: 83009f455dcSMasahiro Yamada default: 83109f455dcSMasahiro Yamada /* 83209f455dcSMasahiro Yamada * These are not supported. It is too early to print a 83309f455dcSMasahiro Yamada * message and the UART likely won't work anyway due to the 83409f455dcSMasahiro Yamada * oscillator being wrong. 83509f455dcSMasahiro Yamada */ 83609f455dcSMasahiro Yamada break; 83709f455dcSMasahiro Yamada } 83809f455dcSMasahiro Yamada 83909f455dcSMasahiro Yamada /* PLLC_MISC2: Set dynramp_stepA/B. MISC2 maps to pll_out[1] */ 84009f455dcSMasahiro Yamada writel(0x00561600, &clkrst->crc_pll[CLOCK_ID_CGENERAL].pll_out[1]); 84109f455dcSMasahiro Yamada 84209f455dcSMasahiro Yamada /* PLLC_MISC: Set LOCK_ENABLE */ 843*722e000cSTom Warren pllinfo = &tegra_pll_info_table[CLOCK_ID_CGENERAL]; 844*722e000cSTom Warren setbits_le32(&clkrst->crc_pll[CLOCK_ID_CGENERAL].pll_misc, (1 << pllinfo->lock_ena)); 84509f455dcSMasahiro Yamada udelay(2); 84609f455dcSMasahiro Yamada 847*722e000cSTom Warren /* PLLD_MISC: Set CLKENABLE, CPCON 12, LFCON 1, and enable lock */ 848*722e000cSTom Warren pllinfo = &tegra_pll_info_table[CLOCK_ID_DISPLAY]; 849*722e000cSTom Warren data = (12 << pllinfo->kcp_shift) | (1 << pllinfo->kvco_shift); 850*722e000cSTom Warren data |= (1 << PLLD_CLKENABLE) | (1 << pllinfo->lock_ena); 851*722e000cSTom Warren writel(data, &clkrst->crc_pll[CLOCK_ID_DISPLAY].pll_misc); 85209f455dcSMasahiro Yamada udelay(2); 85309f455dcSMasahiro Yamada } 85409f455dcSMasahiro Yamada 85509f455dcSMasahiro Yamada void arch_timer_init(void) 85609f455dcSMasahiro Yamada { 85709f455dcSMasahiro Yamada struct sysctr_ctlr *sysctr = (struct sysctr_ctlr *)NV_PA_TSC_BASE; 85809f455dcSMasahiro Yamada u32 freq, val; 85909f455dcSMasahiro Yamada 86009f455dcSMasahiro Yamada freq = clock_get_rate(CLOCK_ID_OSC); 86109f455dcSMasahiro Yamada debug("%s: osc freq is %dHz [0x%08X]\n", __func__, freq, freq); 86209f455dcSMasahiro Yamada 86309f455dcSMasahiro Yamada /* ARM CNTFRQ */ 86409f455dcSMasahiro Yamada asm("mcr p15, 0, %0, c14, c0, 0\n" : : "r" (freq)); 86509f455dcSMasahiro Yamada 86609f455dcSMasahiro Yamada /* Only Tegra114+ has the System Counter regs */ 86709f455dcSMasahiro Yamada debug("%s: setting CNTFID0 to 0x%08X\n", __func__, freq); 86809f455dcSMasahiro Yamada writel(freq, &sysctr->cntfid0); 86909f455dcSMasahiro Yamada 87009f455dcSMasahiro Yamada val = readl(&sysctr->cntcr); 87109f455dcSMasahiro Yamada val |= TSC_CNTCR_ENABLE | TSC_CNTCR_HDBG; 87209f455dcSMasahiro Yamada writel(val, &sysctr->cntcr); 87309f455dcSMasahiro Yamada debug("%s: TSC CNTCR = 0x%08X\n", __func__, val); 87409f455dcSMasahiro Yamada } 87509f455dcSMasahiro Yamada 87609f455dcSMasahiro Yamada #define PLLE_SS_CNTL 0x68 87709f455dcSMasahiro Yamada #define PLLE_SS_CNTL_SSCINCINTR(x) (((x) & 0x3f) << 24) 87809f455dcSMasahiro Yamada #define PLLE_SS_CNTL_SSCINC(x) (((x) & 0xff) << 16) 87909f455dcSMasahiro Yamada #define PLLE_SS_CNTL_SSCINVERT (1 << 15) 88009f455dcSMasahiro Yamada #define PLLE_SS_CNTL_SSCCENTER (1 << 14) 88109f455dcSMasahiro Yamada #define PLLE_SS_CNTL_SSCBYP (1 << 12) 88209f455dcSMasahiro Yamada #define PLLE_SS_CNTL_INTERP_RESET (1 << 11) 88309f455dcSMasahiro Yamada #define PLLE_SS_CNTL_BYPASS_SS (1 << 10) 88409f455dcSMasahiro Yamada #define PLLE_SS_CNTL_SSCMAX(x) (((x) & 0x1ff) << 0) 88509f455dcSMasahiro Yamada 88609f455dcSMasahiro Yamada #define PLLE_BASE 0x0e8 88709f455dcSMasahiro Yamada #define PLLE_BASE_ENABLE (1 << 30) 88809f455dcSMasahiro Yamada #define PLLE_BASE_LOCK_OVERRIDE (1 << 29) 88909f455dcSMasahiro Yamada #define PLLE_BASE_PLDIV_CML(x) (((x) & 0xf) << 24) 89009f455dcSMasahiro Yamada #define PLLE_BASE_NDIV(x) (((x) & 0xff) << 8) 89109f455dcSMasahiro Yamada #define PLLE_BASE_MDIV(x) (((x) & 0xff) << 0) 89209f455dcSMasahiro Yamada 89309f455dcSMasahiro Yamada #define PLLE_MISC 0x0ec 89409f455dcSMasahiro Yamada #define PLLE_MISC_IDDQ_SWCTL (1 << 14) 89509f455dcSMasahiro Yamada #define PLLE_MISC_IDDQ_OVERRIDE (1 << 13) 89609f455dcSMasahiro Yamada #define PLLE_MISC_LOCK_ENABLE (1 << 9) 89709f455dcSMasahiro Yamada #define PLLE_MISC_PTS (1 << 8) 89809f455dcSMasahiro Yamada #define PLLE_MISC_VREG_BG_CTRL(x) (((x) & 0x3) << 4) 89909f455dcSMasahiro Yamada #define PLLE_MISC_VREG_CTRL(x) (((x) & 0x3) << 2) 90009f455dcSMasahiro Yamada 90109f455dcSMasahiro Yamada #define PLLE_AUX 0x48c 90209f455dcSMasahiro Yamada #define PLLE_AUX_SEQ_ENABLE (1 << 24) 90309f455dcSMasahiro Yamada #define PLLE_AUX_ENABLE_SWCTL (1 << 4) 90409f455dcSMasahiro Yamada 90509f455dcSMasahiro Yamada int tegra_plle_enable(void) 90609f455dcSMasahiro Yamada { 90709f455dcSMasahiro Yamada unsigned int m = 1, n = 200, cpcon = 13; 90809f455dcSMasahiro Yamada u32 value; 90909f455dcSMasahiro Yamada 91009f455dcSMasahiro Yamada value = readl(NV_PA_CLK_RST_BASE + PLLE_BASE); 91109f455dcSMasahiro Yamada value &= ~PLLE_BASE_LOCK_OVERRIDE; 91209f455dcSMasahiro Yamada writel(value, NV_PA_CLK_RST_BASE + PLLE_BASE); 91309f455dcSMasahiro Yamada 91409f455dcSMasahiro Yamada value = readl(NV_PA_CLK_RST_BASE + PLLE_AUX); 91509f455dcSMasahiro Yamada value |= PLLE_AUX_ENABLE_SWCTL; 91609f455dcSMasahiro Yamada value &= ~PLLE_AUX_SEQ_ENABLE; 91709f455dcSMasahiro Yamada writel(value, NV_PA_CLK_RST_BASE + PLLE_AUX); 91809f455dcSMasahiro Yamada 91909f455dcSMasahiro Yamada udelay(1); 92009f455dcSMasahiro Yamada 92109f455dcSMasahiro Yamada value = readl(NV_PA_CLK_RST_BASE + PLLE_MISC); 92209f455dcSMasahiro Yamada value |= PLLE_MISC_IDDQ_SWCTL; 92309f455dcSMasahiro Yamada value &= ~PLLE_MISC_IDDQ_OVERRIDE; 92409f455dcSMasahiro Yamada value |= PLLE_MISC_LOCK_ENABLE; 92509f455dcSMasahiro Yamada value |= PLLE_MISC_PTS; 92609f455dcSMasahiro Yamada value |= PLLE_MISC_VREG_BG_CTRL(3); 92709f455dcSMasahiro Yamada value |= PLLE_MISC_VREG_CTRL(2); 92809f455dcSMasahiro Yamada writel(value, NV_PA_CLK_RST_BASE + PLLE_MISC); 92909f455dcSMasahiro Yamada 93009f455dcSMasahiro Yamada udelay(5); 93109f455dcSMasahiro Yamada 93209f455dcSMasahiro Yamada value = readl(NV_PA_CLK_RST_BASE + PLLE_SS_CNTL); 93309f455dcSMasahiro Yamada value |= PLLE_SS_CNTL_SSCBYP | PLLE_SS_CNTL_INTERP_RESET | 93409f455dcSMasahiro Yamada PLLE_SS_CNTL_BYPASS_SS; 93509f455dcSMasahiro Yamada writel(value, NV_PA_CLK_RST_BASE + PLLE_SS_CNTL); 93609f455dcSMasahiro Yamada 93709f455dcSMasahiro Yamada value = readl(NV_PA_CLK_RST_BASE + PLLE_BASE); 93809f455dcSMasahiro Yamada value &= ~PLLE_BASE_PLDIV_CML(0xf); 93909f455dcSMasahiro Yamada value &= ~PLLE_BASE_NDIV(0xff); 94009f455dcSMasahiro Yamada value &= ~PLLE_BASE_MDIV(0xff); 94109f455dcSMasahiro Yamada value |= PLLE_BASE_PLDIV_CML(cpcon); 94209f455dcSMasahiro Yamada value |= PLLE_BASE_NDIV(n); 94309f455dcSMasahiro Yamada value |= PLLE_BASE_MDIV(m); 94409f455dcSMasahiro Yamada writel(value, NV_PA_CLK_RST_BASE + PLLE_BASE); 94509f455dcSMasahiro Yamada 94609f455dcSMasahiro Yamada udelay(1); 94709f455dcSMasahiro Yamada 94809f455dcSMasahiro Yamada value = readl(NV_PA_CLK_RST_BASE + PLLE_BASE); 94909f455dcSMasahiro Yamada value |= PLLE_BASE_ENABLE; 95009f455dcSMasahiro Yamada writel(value, NV_PA_CLK_RST_BASE + PLLE_BASE); 95109f455dcSMasahiro Yamada 95209f455dcSMasahiro Yamada /* wait for lock */ 95309f455dcSMasahiro Yamada udelay(300); 95409f455dcSMasahiro Yamada 95509f455dcSMasahiro Yamada value = readl(NV_PA_CLK_RST_BASE + PLLE_SS_CNTL); 95609f455dcSMasahiro Yamada value &= ~PLLE_SS_CNTL_SSCINVERT; 95709f455dcSMasahiro Yamada value &= ~PLLE_SS_CNTL_SSCCENTER; 95809f455dcSMasahiro Yamada 95909f455dcSMasahiro Yamada value &= ~PLLE_SS_CNTL_SSCINCINTR(0x3f); 96009f455dcSMasahiro Yamada value &= ~PLLE_SS_CNTL_SSCINC(0xff); 96109f455dcSMasahiro Yamada value &= ~PLLE_SS_CNTL_SSCMAX(0x1ff); 96209f455dcSMasahiro Yamada 96309f455dcSMasahiro Yamada value |= PLLE_SS_CNTL_SSCINCINTR(0x20); 96409f455dcSMasahiro Yamada value |= PLLE_SS_CNTL_SSCINC(0x01); 96509f455dcSMasahiro Yamada value |= PLLE_SS_CNTL_SSCMAX(0x25); 96609f455dcSMasahiro Yamada 96709f455dcSMasahiro Yamada writel(value, NV_PA_CLK_RST_BASE + PLLE_SS_CNTL); 96809f455dcSMasahiro Yamada 96909f455dcSMasahiro Yamada value = readl(NV_PA_CLK_RST_BASE + PLLE_SS_CNTL); 97009f455dcSMasahiro Yamada value &= ~PLLE_SS_CNTL_SSCBYP; 97109f455dcSMasahiro Yamada value &= ~PLLE_SS_CNTL_BYPASS_SS; 97209f455dcSMasahiro Yamada writel(value, NV_PA_CLK_RST_BASE + PLLE_SS_CNTL); 97309f455dcSMasahiro Yamada 97409f455dcSMasahiro Yamada udelay(1); 97509f455dcSMasahiro Yamada 97609f455dcSMasahiro Yamada value = readl(NV_PA_CLK_RST_BASE + PLLE_SS_CNTL); 97709f455dcSMasahiro Yamada value &= ~PLLE_SS_CNTL_INTERP_RESET; 97809f455dcSMasahiro Yamada writel(value, NV_PA_CLK_RST_BASE + PLLE_SS_CNTL); 97909f455dcSMasahiro Yamada 98009f455dcSMasahiro Yamada udelay(1); 98109f455dcSMasahiro Yamada 98209f455dcSMasahiro Yamada return 0; 98309f455dcSMasahiro Yamada } 98496e82a25SSimon Glass 98596e82a25SSimon Glass void clock_sor_enable_edp_clock(void) 98696e82a25SSimon Glass { 98796e82a25SSimon Glass u32 *reg; 98896e82a25SSimon Glass 98996e82a25SSimon Glass /* uses PLLP, has a non-standard bit layout. */ 99096e82a25SSimon Glass reg = get_periph_source_reg(PERIPH_ID_SOR0); 99196e82a25SSimon Glass setbits_le32(reg, SOR0_CLK_SEL0); 99296e82a25SSimon Glass } 99396e82a25SSimon Glass 99496e82a25SSimon Glass u32 clock_set_display_rate(u32 frequency) 99596e82a25SSimon Glass { 99696e82a25SSimon Glass /** 99796e82a25SSimon Glass * plld (fo) = vco >> p, where 500MHz < vco < 1000MHz 99896e82a25SSimon Glass * = (cf * n) >> p, where 1MHz < cf < 6MHz 99996e82a25SSimon Glass * = ((ref / m) * n) >> p 100096e82a25SSimon Glass * 100196e82a25SSimon Glass * Iterate the possible values of p (3 bits, 2^7) to find out a minimum 100296e82a25SSimon Glass * safe vco, then find best (m, n). since m has only 5 bits, we can 100396e82a25SSimon Glass * iterate all possible values. Note Tegra 124 supports 11 bits for n, 100496e82a25SSimon Glass * but our pll_fields has only 10 bits for n. 100596e82a25SSimon Glass * 100696e82a25SSimon Glass * Note values undershoot or overshoot target output frequency may not 100796e82a25SSimon Glass * work if the values are not in "safe" range by panel specification. 100896e82a25SSimon Glass */ 100996e82a25SSimon Glass u32 ref = clock_get_rate(CLOCK_ID_OSC); 101096e82a25SSimon Glass u32 divm, divn, divp, cpcon; 101196e82a25SSimon Glass u32 cf, vco, rounded_rate = frequency; 101296e82a25SSimon Glass u32 diff, best_diff, best_m = 0, best_n = 0, best_p; 101396e82a25SSimon Glass const u32 max_m = 1 << 5, max_n = 1 << 10, max_p = 1 << 3, 101496e82a25SSimon Glass mhz = 1000 * 1000, min_vco = 500 * mhz, max_vco = 1000 * mhz, 101596e82a25SSimon Glass min_cf = 1 * mhz, max_cf = 6 * mhz; 101696e82a25SSimon Glass int mux_bits, divider_bits, source; 101796e82a25SSimon Glass 101896e82a25SSimon Glass for (divp = 0, vco = frequency; vco < min_vco && divp < max_p; divp++) 101996e82a25SSimon Glass vco <<= 1; 102096e82a25SSimon Glass 102196e82a25SSimon Glass if (vco < min_vco || vco > max_vco) { 102296e82a25SSimon Glass printf("%s: Cannot find out a supported VCO for Frequency (%u)\n", 102396e82a25SSimon Glass __func__, frequency); 102496e82a25SSimon Glass return 0; 102596e82a25SSimon Glass } 102696e82a25SSimon Glass 102796e82a25SSimon Glass best_p = divp; 102896e82a25SSimon Glass best_diff = vco; 102996e82a25SSimon Glass 103096e82a25SSimon Glass for (divm = 1; divm < max_m && best_diff; divm++) { 103196e82a25SSimon Glass cf = ref / divm; 103296e82a25SSimon Glass if (cf < min_cf) 103396e82a25SSimon Glass break; 103496e82a25SSimon Glass if (cf > max_cf) 103596e82a25SSimon Glass continue; 103696e82a25SSimon Glass 103796e82a25SSimon Glass divn = vco / cf; 103896e82a25SSimon Glass if (divn >= max_n) 103996e82a25SSimon Glass continue; 104096e82a25SSimon Glass 104196e82a25SSimon Glass diff = vco - divn * cf; 104296e82a25SSimon Glass if (divn + 1 < max_n && diff > cf / 2) { 104396e82a25SSimon Glass divn++; 104496e82a25SSimon Glass diff = cf - diff; 104596e82a25SSimon Glass } 104696e82a25SSimon Glass 104796e82a25SSimon Glass if (diff >= best_diff) 104896e82a25SSimon Glass continue; 104996e82a25SSimon Glass 105096e82a25SSimon Glass best_diff = diff; 105196e82a25SSimon Glass best_m = divm; 105296e82a25SSimon Glass best_n = divn; 105396e82a25SSimon Glass } 105496e82a25SSimon Glass 105596e82a25SSimon Glass if (best_n < 50) 105696e82a25SSimon Glass cpcon = 2; 105796e82a25SSimon Glass else if (best_n < 300) 105896e82a25SSimon Glass cpcon = 3; 105996e82a25SSimon Glass else if (best_n < 600) 106096e82a25SSimon Glass cpcon = 8; 106196e82a25SSimon Glass else 106296e82a25SSimon Glass cpcon = 12; 106396e82a25SSimon Glass 106496e82a25SSimon Glass if (best_diff) { 106596e82a25SSimon Glass printf("%s: Failed to match output frequency %u, best difference is %u\n", 106696e82a25SSimon Glass __func__, frequency, best_diff); 106796e82a25SSimon Glass rounded_rate = (ref / best_m * best_n) >> best_p; 106896e82a25SSimon Glass } 106996e82a25SSimon Glass 107096e82a25SSimon Glass debug("%s: PLLD=%u ref=%u, m/n/p/cpcon=%u/%u/%u/%u\n", 107196e82a25SSimon Glass __func__, rounded_rate, ref, best_m, best_n, best_p, cpcon); 107296e82a25SSimon Glass 107396e82a25SSimon Glass source = get_periph_clock_source(PERIPH_ID_DISP1, CLOCK_ID_DISPLAY, 107496e82a25SSimon Glass &mux_bits, ÷r_bits); 107596e82a25SSimon Glass clock_ll_set_source_bits(PERIPH_ID_DISP1, mux_bits, source); 107696e82a25SSimon Glass clock_set_rate(CLOCK_ID_DISPLAY, best_n, best_m, best_p, cpcon); 107796e82a25SSimon Glass 107896e82a25SSimon Glass return rounded_rate; 107996e82a25SSimon Glass } 108096e82a25SSimon Glass 108196e82a25SSimon Glass void clock_set_up_plldp(void) 108296e82a25SSimon Glass { 108396e82a25SSimon Glass struct clk_rst_ctlr *clkrst = 108496e82a25SSimon Glass (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE; 108596e82a25SSimon Glass u32 value; 108696e82a25SSimon Glass 108796e82a25SSimon Glass value = PLLDP_SS_CFG_UNDOCUMENTED | PLLDP_SS_CFG_DITHER; 108896e82a25SSimon Glass writel(value | PLLDP_SS_CFG_CLAMP, &clkrst->crc_plldp_ss_cfg); 108996e82a25SSimon Glass clock_start_pll(CLOCK_ID_DP, 1, 90, 3, 0, 0); 109096e82a25SSimon Glass writel(value, &clkrst->crc_plldp_ss_cfg); 109196e82a25SSimon Glass } 109296e82a25SSimon Glass 109396e82a25SSimon Glass struct clk_pll_simple *clock_get_simple_pll(enum clock_id clkid) 109496e82a25SSimon Glass { 109596e82a25SSimon Glass struct clk_rst_ctlr *clkrst = 109696e82a25SSimon Glass (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE; 109796e82a25SSimon Glass 109896e82a25SSimon Glass if (clkid == CLOCK_ID_DP) 109996e82a25SSimon Glass return &clkrst->plldp; 110096e82a25SSimon Glass 110196e82a25SSimon Glass return NULL; 110296e82a25SSimon Glass } 1103