1 /* 2 * Copyright (c) 2010-2014, NVIDIA CORPORATION. All rights reserved. 3 * 4 * This program is free software; you can redistribute it and/or modify it 5 * under the terms and conditions of the GNU General Public License, 6 * version 2, as published by the Free Software Foundation. 7 * 8 * This program is distributed in the hope it will be useful, but WITHOUT 9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 11 * more details. 12 * 13 * You should have received a copy of the GNU General Public License 14 * along with this program. If not, see <http://www.gnu.org/licenses/>. 15 */ 16 17 #include <common.h> 18 #include <asm/io.h> 19 #include <asm/arch/clock.h> 20 #include <asm/arch/flow.h> 21 #include <asm/arch/pinmux.h> 22 #include <asm/arch/tegra.h> 23 #include <asm/arch-tegra/clk_rst.h> 24 #include <asm/arch-tegra/pmc.h> 25 #include "../cpu.h" 26 27 /* Tegra114-specific CPU init code */ 28 static void enable_cpu_power_rail(void) 29 { 30 struct pmc_ctlr *pmc = (struct pmc_ctlr *)NV_PA_PMC_BASE; 31 struct clk_rst_ctlr *clkrst = (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE; 32 u32 reg; 33 34 debug("enable_cpu_power_rail entry\n"); 35 36 /* un-tristate PWR_I2C SCL/SDA, rest of the defaults are correct */ 37 pinmux_tristate_disable(PMUX_PINGRP_PWR_I2C_SCL_PZ6); 38 pinmux_tristate_disable(PMUX_PINGRP_PWR_I2C_SDA_PZ7); 39 40 /* 41 * Set CPUPWRGOOD_TIMER - APB clock is 1/2 of SCLK (102MHz), 42 * set it for 25ms (102MHz * .025) 43 */ 44 reg = 0x26E8F0; 45 writel(reg, &pmc->pmc_cpupwrgood_timer); 46 47 /* Set polarity to 0 (normal) and enable CPUPWRREQ_OE */ 48 clrbits_le32(&pmc->pmc_cntrl, CPUPWRREQ_POL); 49 setbits_le32(&pmc->pmc_cntrl, CPUPWRREQ_OE); 50 51 /* 52 * Set CLK_RST_CONTROLLER_CPU_SOFTRST_CTRL2_0_CAR2PMC_CPU_ACK_WIDTH 53 * to 408 to satisfy the requirement of having at least 16 CPU clock 54 * cycles before clamp removal. 55 */ 56 57 clrbits_le32(&clkrst->crc_cpu_softrst_ctrl2, 0xFFF); 58 setbits_le32(&clkrst->crc_cpu_softrst_ctrl2, 408); 59 } 60 61 static void enable_cpu_clocks(void) 62 { 63 struct clk_rst_ctlr *clkrst = (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE; 64 u32 reg; 65 66 debug("enable_cpu_clocks entry\n"); 67 68 /* Wait for PLL-X to lock */ 69 do { 70 reg = readl(&clkrst->crc_pll_simple[SIMPLE_PLLX].pll_base); 71 } while ((reg & PLL_LOCK_MASK) == 0); 72 73 /* Wait until all clocks are stable */ 74 udelay(PLL_STABILIZATION_DELAY); 75 76 writel(CCLK_BURST_POLICY, &clkrst->crc_cclk_brst_pol); 77 writel(SUPER_CCLK_DIVIDER, &clkrst->crc_super_cclk_div); 78 79 /* Always enable the main CPU complex clocks */ 80 clock_enable(PERIPH_ID_CPU); 81 clock_enable(PERIPH_ID_CPULP); 82 clock_enable(PERIPH_ID_CPUG); 83 } 84 85 static void remove_cpu_resets(void) 86 { 87 struct clk_rst_ctlr *clkrst = (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE; 88 u32 reg; 89 90 debug("remove_cpu_resets entry\n"); 91 /* Take the slow non-CPU partition out of reset */ 92 reg = readl(&clkrst->crc_rst_cpulp_cmplx_clr); 93 writel((reg | CLR_NONCPURESET), &clkrst->crc_rst_cpulp_cmplx_clr); 94 95 /* Take the fast non-CPU partition out of reset */ 96 reg = readl(&clkrst->crc_rst_cpug_cmplx_clr); 97 writel((reg | CLR_NONCPURESET), &clkrst->crc_rst_cpug_cmplx_clr); 98 99 /* Clear the SW-controlled reset of the slow cluster */ 100 reg = readl(&clkrst->crc_rst_cpulp_cmplx_clr); 101 reg |= (CLR_CPURESET0+CLR_DBGRESET0+CLR_CORERESET0+CLR_CXRESET0); 102 writel(reg, &clkrst->crc_rst_cpulp_cmplx_clr); 103 104 /* Clear the SW-controlled reset of the fast cluster */ 105 reg = readl(&clkrst->crc_rst_cpug_cmplx_clr); 106 reg |= (CLR_CPURESET0+CLR_DBGRESET0+CLR_CORERESET0+CLR_CXRESET0); 107 reg |= (CLR_CPURESET1+CLR_DBGRESET1+CLR_CORERESET1+CLR_CXRESET1); 108 reg |= (CLR_CPURESET2+CLR_DBGRESET2+CLR_CORERESET2+CLR_CXRESET2); 109 reg |= (CLR_CPURESET3+CLR_DBGRESET3+CLR_CORERESET3+CLR_CXRESET3); 110 writel(reg, &clkrst->crc_rst_cpug_cmplx_clr); 111 } 112 113 /** 114 * The T114 requires some special clock initialization, including setting up 115 * the DVC I2C, turning on MSELECT and selecting the G CPU cluster 116 */ 117 void t114_init_clocks(void) 118 { 119 struct clk_rst_ctlr *clkrst = 120 (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE; 121 struct flow_ctlr *flow = (struct flow_ctlr *)NV_PA_FLOW_BASE; 122 u32 val; 123 124 debug("t114_init_clocks entry\n"); 125 126 /* Set active CPU cluster to G */ 127 clrbits_le32(&flow->cluster_control, 1); 128 129 writel(SUPER_SCLK_ENB_MASK, &clkrst->crc_super_sclk_div); 130 131 debug("Setting up PLLX\n"); 132 init_pllx(); 133 134 val = (1 << CLK_SYS_RATE_AHB_RATE_SHIFT); 135 writel(val, &clkrst->crc_clk_sys_rate); 136 137 /* Enable clocks to required peripherals. TBD - minimize this list */ 138 debug("Enabling clocks\n"); 139 140 clock_set_enable(PERIPH_ID_CACHE2, 1); 141 clock_set_enable(PERIPH_ID_GPIO, 1); 142 clock_set_enable(PERIPH_ID_TMR, 1); 143 clock_set_enable(PERIPH_ID_RTC, 1); 144 clock_set_enable(PERIPH_ID_CPU, 1); 145 clock_set_enable(PERIPH_ID_EMC, 1); 146 clock_set_enable(PERIPH_ID_I2C5, 1); 147 clock_set_enable(PERIPH_ID_FUSE, 1); 148 clock_set_enable(PERIPH_ID_PMC, 1); 149 clock_set_enable(PERIPH_ID_APBDMA, 1); 150 clock_set_enable(PERIPH_ID_MEM, 1); 151 clock_set_enable(PERIPH_ID_IRAMA, 1); 152 clock_set_enable(PERIPH_ID_IRAMB, 1); 153 clock_set_enable(PERIPH_ID_IRAMC, 1); 154 clock_set_enable(PERIPH_ID_IRAMD, 1); 155 clock_set_enable(PERIPH_ID_CORESIGHT, 1); 156 clock_set_enable(PERIPH_ID_MSELECT, 1); 157 clock_set_enable(PERIPH_ID_EMC1, 1); 158 clock_set_enable(PERIPH_ID_MC1, 1); 159 clock_set_enable(PERIPH_ID_DVFS, 1); 160 161 /* 162 * Set MSELECT clock source as PLLP (00), and ask for a clock 163 * divider that would set the MSELECT clock at 102MHz for a 164 * PLLP base of 408MHz. 165 */ 166 clock_ll_set_source_divisor(PERIPH_ID_MSELECT, 0, 167 CLK_DIVIDER(NVBL_PLLP_KHZ, 102000)); 168 169 /* I2C5 (DVC) gets CLK_M and a divisor of 17 */ 170 clock_ll_set_source_divisor(PERIPH_ID_I2C5, 3, 16); 171 172 /* Give clocks time to stabilize */ 173 udelay(1000); 174 175 /* Take required peripherals out of reset */ 176 debug("Taking periphs out of reset\n"); 177 reset_set_enable(PERIPH_ID_CACHE2, 0); 178 reset_set_enable(PERIPH_ID_GPIO, 0); 179 reset_set_enable(PERIPH_ID_TMR, 0); 180 reset_set_enable(PERIPH_ID_COP, 0); 181 reset_set_enable(PERIPH_ID_EMC, 0); 182 reset_set_enable(PERIPH_ID_I2C5, 0); 183 reset_set_enable(PERIPH_ID_FUSE, 0); 184 reset_set_enable(PERIPH_ID_APBDMA, 0); 185 reset_set_enable(PERIPH_ID_MEM, 0); 186 reset_set_enable(PERIPH_ID_CORESIGHT, 0); 187 reset_set_enable(PERIPH_ID_MSELECT, 0); 188 reset_set_enable(PERIPH_ID_EMC1, 0); 189 reset_set_enable(PERIPH_ID_MC1, 0); 190 reset_set_enable(PERIPH_ID_DVFS, 0); 191 192 debug("t114_init_clocks exit\n"); 193 } 194 195 static bool is_partition_powered(u32 partid) 196 { 197 struct pmc_ctlr *pmc = (struct pmc_ctlr *)NV_PA_PMC_BASE; 198 u32 reg; 199 200 /* Get power gate status */ 201 reg = readl(&pmc->pmc_pwrgate_status); 202 return !!(reg & (1 << partid)); 203 } 204 205 static bool is_clamp_enabled(u32 partid) 206 { 207 struct pmc_ctlr *pmc = (struct pmc_ctlr *)NV_PA_PMC_BASE; 208 u32 reg; 209 210 /* Get clamp status. */ 211 reg = readl(&pmc->pmc_clamp_status); 212 return !!(reg & (1 << partid)); 213 } 214 215 static void power_partition(u32 partid) 216 { 217 struct pmc_ctlr *pmc = (struct pmc_ctlr *)NV_PA_PMC_BASE; 218 219 debug("%s: part ID = %08X\n", __func__, partid); 220 /* Is the partition already on? */ 221 if (!is_partition_powered(partid)) { 222 /* No, toggle the partition power state (OFF -> ON) */ 223 debug("power_partition, toggling state\n"); 224 writel(START_CP | partid, &pmc->pmc_pwrgate_toggle); 225 226 /* Wait for the power to come up */ 227 while (!is_partition_powered(partid)) 228 ; 229 230 /* Wait for the clamp status to be cleared */ 231 while (is_clamp_enabled(partid)) 232 ; 233 234 /* Give I/O signals time to stabilize */ 235 udelay(IO_STABILIZATION_DELAY); 236 } 237 } 238 239 void powerup_cpus(void) 240 { 241 debug("powerup_cpus entry\n"); 242 243 /* We boot to the fast cluster */ 244 debug("powerup_cpus entry: G cluster\n"); 245 /* Power up the fast cluster rail partition */ 246 power_partition(CRAIL); 247 248 /* Power up the fast cluster non-CPU partition */ 249 power_partition(C0NC); 250 251 /* Power up the fast cluster CPU0 partition */ 252 power_partition(CE0); 253 } 254 255 void start_cpu(u32 reset_vector) 256 { 257 u32 imme, inst; 258 259 debug("start_cpu entry, reset_vector = %x\n", reset_vector); 260 261 t114_init_clocks(); 262 263 /* Enable VDD_CPU */ 264 enable_cpu_power_rail(); 265 266 /* Get the CPU(s) running */ 267 enable_cpu_clocks(); 268 269 /* Enable CoreSight */ 270 clock_enable_coresight(1); 271 272 /* Take CPU(s) out of reset */ 273 remove_cpu_resets(); 274 275 /* Set the entry point for CPU execution from reset */ 276 277 /* 278 * A01P with patched boot ROM; vector hard-coded to 0x4003fffc. 279 * See nvbug 1193357 for details. 280 */ 281 282 /* mov r0, #lsb(reset_vector) */ 283 imme = reset_vector & 0xffff; 284 inst = imme & 0xfff; 285 inst |= ((imme >> 12) << 16); 286 inst |= 0xe3000000; 287 writel(inst, 0x4003fff0); 288 289 /* movt r0, #msb(reset_vector) */ 290 imme = (reset_vector >> 16) & 0xffff; 291 inst = imme & 0xfff; 292 inst |= ((imme >> 12) << 16); 293 inst |= 0xe3400000; 294 writel(inst, 0x4003fff4); 295 296 /* bx r0 */ 297 writel(0xe12fff10, 0x4003fff8); 298 299 /* b -12 */ 300 imme = (u32)-20; 301 inst = (imme >> 2) & 0xffffff; 302 inst |= 0xea000000; 303 writel(inst, 0x4003fffc); 304 305 /* Write to orignal location for compatibility */ 306 writel(reset_vector, EXCEP_VECTOR_CPU_RESET_VECTOR); 307 308 /* If the CPU(s) don't already have power, power 'em up */ 309 powerup_cpus(); 310 } 311