1 /* 2 * (C) Copyright 2010-2014 3 * NVIDIA Corporation <www.nvidia.com> 4 * 5 * SPDX-License-Identifier: GPL-2.0+ 6 */ 7 8 #include <common.h> 9 #include <asm/io.h> 10 #include <asm/arch/clock.h> 11 #include <asm/arch/flow.h> 12 #include <asm/arch/pinmux.h> 13 #include <asm/arch/tegra.h> 14 #include <asm/arch-tegra/clk_rst.h> 15 #include <asm/arch-tegra/pmc.h> 16 #include "../cpu.h" 17 18 /* Tegra114-specific CPU init code */ 19 static void enable_cpu_power_rail(void) 20 { 21 struct pmc_ctlr *pmc = (struct pmc_ctlr *)NV_PA_PMC_BASE; 22 struct clk_rst_ctlr *clkrst = (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE; 23 u32 reg; 24 25 debug("%s entry\n", __func__); 26 27 /* un-tristate PWR_I2C SCL/SDA, rest of the defaults are correct */ 28 pinmux_tristate_disable(PMUX_PINGRP_PWR_I2C_SCL_PZ6); 29 pinmux_tristate_disable(PMUX_PINGRP_PWR_I2C_SDA_PZ7); 30 31 /* 32 * Set CPUPWRGOOD_TIMER - APB clock is 1/2 of SCLK (102MHz), 33 * set it for 25ms (102MHz * .025) 34 */ 35 reg = 0x26E8F0; 36 writel(reg, &pmc->pmc_cpupwrgood_timer); 37 38 /* Set polarity to 0 (normal) and enable CPUPWRREQ_OE */ 39 clrbits_le32(&pmc->pmc_cntrl, CPUPWRREQ_POL); 40 setbits_le32(&pmc->pmc_cntrl, CPUPWRREQ_OE); 41 42 /* 43 * Set CLK_RST_CONTROLLER_CPU_SOFTRST_CTRL2_0_CAR2PMC_CPU_ACK_WIDTH 44 * to 408 to satisfy the requirement of having at least 16 CPU clock 45 * cycles before clamp removal. 46 */ 47 48 clrbits_le32(&clkrst->crc_cpu_softrst_ctrl2, 0xFFF); 49 setbits_le32(&clkrst->crc_cpu_softrst_ctrl2, 408); 50 } 51 52 static void enable_cpu_clocks(void) 53 { 54 struct clk_rst_ctlr *clkrst = (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE; 55 struct clk_pll_info *pllinfo = &tegra_pll_info_table[CLOCK_ID_XCPU]; 56 u32 reg; 57 58 debug("%s entry\n", __func__); 59 60 /* Wait for PLL-X to lock */ 61 do { 62 reg = readl(&clkrst->crc_pll_simple[SIMPLE_PLLX].pll_base); 63 } while ((reg & (1 << pllinfo->lock_det)) == 0); 64 65 /* Wait until all clocks are stable */ 66 udelay(PLL_STABILIZATION_DELAY); 67 68 writel(CCLK_BURST_POLICY, &clkrst->crc_cclk_brst_pol); 69 writel(SUPER_CCLK_DIVIDER, &clkrst->crc_super_cclk_div); 70 71 /* Always enable the main CPU complex clocks */ 72 clock_enable(PERIPH_ID_CPU); 73 clock_enable(PERIPH_ID_CPULP); 74 clock_enable(PERIPH_ID_CPUG); 75 } 76 77 static void remove_cpu_resets(void) 78 { 79 struct clk_rst_ctlr *clkrst = (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE; 80 u32 reg; 81 82 debug("%s entry\n", __func__); 83 /* Take the slow non-CPU partition out of reset */ 84 reg = readl(&clkrst->crc_rst_cpulp_cmplx_clr); 85 writel((reg | CLR_NONCPURESET), &clkrst->crc_rst_cpulp_cmplx_clr); 86 87 /* Take the fast non-CPU partition out of reset */ 88 reg = readl(&clkrst->crc_rst_cpug_cmplx_clr); 89 writel((reg | CLR_NONCPURESET), &clkrst->crc_rst_cpug_cmplx_clr); 90 91 /* Clear the SW-controlled reset of the slow cluster */ 92 reg = readl(&clkrst->crc_rst_cpulp_cmplx_clr); 93 reg |= (CLR_CPURESET0+CLR_DBGRESET0+CLR_CORERESET0+CLR_CXRESET0); 94 writel(reg, &clkrst->crc_rst_cpulp_cmplx_clr); 95 96 /* Clear the SW-controlled reset of the fast cluster */ 97 reg = readl(&clkrst->crc_rst_cpug_cmplx_clr); 98 reg |= (CLR_CPURESET0+CLR_DBGRESET0+CLR_CORERESET0+CLR_CXRESET0); 99 reg |= (CLR_CPURESET1+CLR_DBGRESET1+CLR_CORERESET1+CLR_CXRESET1); 100 reg |= (CLR_CPURESET2+CLR_DBGRESET2+CLR_CORERESET2+CLR_CXRESET2); 101 reg |= (CLR_CPURESET3+CLR_DBGRESET3+CLR_CORERESET3+CLR_CXRESET3); 102 writel(reg, &clkrst->crc_rst_cpug_cmplx_clr); 103 } 104 105 /** 106 * Tegra114 requires some special clock initialization, including setting up 107 * the DVC I2C, turning on MSELECT and selecting the G CPU cluster 108 */ 109 void t114_init_clocks(void) 110 { 111 struct clk_rst_ctlr *clkrst = 112 (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE; 113 struct flow_ctlr *flow = (struct flow_ctlr *)NV_PA_FLOW_BASE; 114 u32 val; 115 116 debug("%s entry\n", __func__); 117 118 /* Set active CPU cluster to G */ 119 clrbits_le32(&flow->cluster_control, 1); 120 121 writel(SUPER_SCLK_ENB_MASK, &clkrst->crc_super_sclk_div); 122 123 debug("Setting up PLLX\n"); 124 init_pllx(); 125 126 val = (1 << CLK_SYS_RATE_AHB_RATE_SHIFT); 127 writel(val, &clkrst->crc_clk_sys_rate); 128 129 /* Enable clocks to required peripherals. TBD - minimize this list */ 130 debug("Enabling clocks\n"); 131 132 clock_set_enable(PERIPH_ID_CACHE2, 1); 133 clock_set_enable(PERIPH_ID_GPIO, 1); 134 clock_set_enable(PERIPH_ID_TMR, 1); 135 clock_set_enable(PERIPH_ID_RTC, 1); 136 clock_set_enable(PERIPH_ID_CPU, 1); 137 clock_set_enable(PERIPH_ID_EMC, 1); 138 clock_set_enable(PERIPH_ID_I2C5, 1); 139 clock_set_enable(PERIPH_ID_FUSE, 1); 140 clock_set_enable(PERIPH_ID_PMC, 1); 141 clock_set_enable(PERIPH_ID_APBDMA, 1); 142 clock_set_enable(PERIPH_ID_MEM, 1); 143 clock_set_enable(PERIPH_ID_IRAMA, 1); 144 clock_set_enable(PERIPH_ID_IRAMB, 1); 145 clock_set_enable(PERIPH_ID_IRAMC, 1); 146 clock_set_enable(PERIPH_ID_IRAMD, 1); 147 clock_set_enable(PERIPH_ID_CORESIGHT, 1); 148 clock_set_enable(PERIPH_ID_MSELECT, 1); 149 clock_set_enable(PERIPH_ID_EMC1, 1); 150 clock_set_enable(PERIPH_ID_MC1, 1); 151 clock_set_enable(PERIPH_ID_DVFS, 1); 152 153 /* 154 * Set MSELECT clock source as PLLP (00), and ask for a clock 155 * divider that would set the MSELECT clock at 102MHz for a 156 * PLLP base of 408MHz. 157 */ 158 clock_ll_set_source_divisor(PERIPH_ID_MSELECT, 0, 159 CLK_DIVIDER(NVBL_PLLP_KHZ, 102000)); 160 161 /* I2C5 (DVC) gets CLK_M and a divisor of 17 */ 162 clock_ll_set_source_divisor(PERIPH_ID_I2C5, 3, 16); 163 164 /* Give clocks time to stabilize */ 165 udelay(1000); 166 167 /* Take required peripherals out of reset */ 168 debug("Taking periphs out of reset\n"); 169 reset_set_enable(PERIPH_ID_CACHE2, 0); 170 reset_set_enable(PERIPH_ID_GPIO, 0); 171 reset_set_enable(PERIPH_ID_TMR, 0); 172 reset_set_enable(PERIPH_ID_COP, 0); 173 reset_set_enable(PERIPH_ID_EMC, 0); 174 reset_set_enable(PERIPH_ID_I2C5, 0); 175 reset_set_enable(PERIPH_ID_FUSE, 0); 176 reset_set_enable(PERIPH_ID_APBDMA, 0); 177 reset_set_enable(PERIPH_ID_MEM, 0); 178 reset_set_enable(PERIPH_ID_CORESIGHT, 0); 179 reset_set_enable(PERIPH_ID_MSELECT, 0); 180 reset_set_enable(PERIPH_ID_EMC1, 0); 181 reset_set_enable(PERIPH_ID_MC1, 0); 182 reset_set_enable(PERIPH_ID_DVFS, 0); 183 184 debug("%s exit\n", __func__); 185 } 186 187 static bool is_partition_powered(u32 partid) 188 { 189 struct pmc_ctlr *pmc = (struct pmc_ctlr *)NV_PA_PMC_BASE; 190 u32 reg; 191 192 /* Get power gate status */ 193 reg = readl(&pmc->pmc_pwrgate_status); 194 return !!(reg & (1 << partid)); 195 } 196 197 static bool is_clamp_enabled(u32 partid) 198 { 199 struct pmc_ctlr *pmc = (struct pmc_ctlr *)NV_PA_PMC_BASE; 200 u32 reg; 201 202 /* Get clamp status. */ 203 reg = readl(&pmc->pmc_clamp_status); 204 return !!(reg & (1 << partid)); 205 } 206 207 static void power_partition(u32 partid) 208 { 209 struct pmc_ctlr *pmc = (struct pmc_ctlr *)NV_PA_PMC_BASE; 210 211 debug("%s: part ID = %08X\n", __func__, partid); 212 /* Is the partition already on? */ 213 if (!is_partition_powered(partid)) { 214 /* No, toggle the partition power state (OFF -> ON) */ 215 debug("power_partition, toggling state\n"); 216 writel(START_CP | partid, &pmc->pmc_pwrgate_toggle); 217 218 /* Wait for the power to come up */ 219 while (!is_partition_powered(partid)) 220 ; 221 222 /* Wait for the clamp status to be cleared */ 223 while (is_clamp_enabled(partid)) 224 ; 225 226 /* Give I/O signals time to stabilize */ 227 udelay(IO_STABILIZATION_DELAY); 228 } 229 } 230 231 void powerup_cpus(void) 232 { 233 /* We boot to the fast cluster */ 234 debug("%s entry: G cluster\n", __func__); 235 236 /* Power up the fast cluster rail partition */ 237 power_partition(CRAIL); 238 239 /* Power up the fast cluster non-CPU partition */ 240 power_partition(C0NC); 241 242 /* Power up the fast cluster CPU0 partition */ 243 power_partition(CE0); 244 } 245 246 void start_cpu(u32 reset_vector) 247 { 248 u32 imme, inst; 249 250 debug("%s entry, reset_vector = %x\n", __func__, reset_vector); 251 252 t114_init_clocks(); 253 254 /* Enable VDD_CPU */ 255 enable_cpu_power_rail(); 256 257 /* Get the CPU(s) running */ 258 enable_cpu_clocks(); 259 260 /* Enable CoreSight */ 261 clock_enable_coresight(1); 262 263 /* Take CPU(s) out of reset */ 264 remove_cpu_resets(); 265 266 /* Set the entry point for CPU execution from reset */ 267 268 /* 269 * A01P with patched boot ROM; vector hard-coded to 0x4003fffc. 270 * See nvbug 1193357 for details. 271 */ 272 273 /* mov r0, #lsb(reset_vector) */ 274 imme = reset_vector & 0xffff; 275 inst = imme & 0xfff; 276 inst |= ((imme >> 12) << 16); 277 inst |= 0xe3000000; 278 writel(inst, 0x4003fff0); 279 280 /* movt r0, #msb(reset_vector) */ 281 imme = (reset_vector >> 16) & 0xffff; 282 inst = imme & 0xfff; 283 inst |= ((imme >> 12) << 16); 284 inst |= 0xe3400000; 285 writel(inst, 0x4003fff4); 286 287 /* bx r0 */ 288 writel(0xe12fff10, 0x4003fff8); 289 290 /* b -12 */ 291 imme = (u32)-20; 292 inst = (imme >> 2) & 0xffffff; 293 inst |= 0xea000000; 294 writel(inst, 0x4003fffc); 295 296 /* Write to original location for compatibility */ 297 writel(reset_vector, EXCEP_VECTOR_CPU_RESET_VECTOR); 298 299 /* If the CPU(s) don't already have power, power 'em up */ 300 powerup_cpus(); 301 } 302