1 /* 2 * Copyright (c) 2014-2015, NVIDIA CORPORATION. All rights reserved. 3 * 4 * SPDX-License-Identifier: GPL-2.0 5 */ 6 7 /* Tegra vpr routines */ 8 9 #include <common.h> 10 #include <asm/io.h> 11 #include <asm/arch/tegra.h> 12 #include <asm/arch/mc.h> 13 14 #include <fdt_support.h> 15 16 static bool _configured; 17 18 void tegra_gpu_config(void) 19 { 20 struct mc_ctlr *mc = (struct mc_ctlr *)NV_PA_MC_BASE; 21 22 /* Turn VPR off */ 23 writel(0, &mc->mc_video_protect_size_mb); 24 writel(TEGRA_MC_VIDEO_PROTECT_REG_WRITE_ACCESS_DISABLED, 25 &mc->mc_video_protect_reg_ctrl); 26 /* read back to ensure the write went through */ 27 readl(&mc->mc_video_protect_reg_ctrl); 28 29 debug("configured VPR\n"); 30 31 _configured = true; 32 } 33 34 #if defined(CONFIG_OF_LIBFDT) 35 36 int tegra_gpu_enable_node(void *blob, const char *gpupath) 37 { 38 int offset; 39 40 if (_configured) { 41 offset = fdt_path_offset(blob, gpupath); 42 if (offset > 0) { 43 fdt_status_okay(blob, offset); 44 debug("enabled GPU node %s\n", gpupath); 45 } 46 } 47 48 return 0; 49 } 50 51 #endif 52