1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* 3 * (C) Copyright 2010-2015 4 * NVIDIA Corporation <www.nvidia.com> 5 */ 6 #include <asm/types.h> 7 8 /* Stabilization delays, in usec */ 9 #define PLL_STABILIZATION_DELAY (300) 10 #define IO_STABILIZATION_DELAY (1000) 11 12 #if defined(CONFIG_TEGRA20) 13 #define NVBL_PLLP_KHZ 216000 14 #define CSITE_KHZ 144000 15 #elif defined(CONFIG_TEGRA30) || defined(CONFIG_TEGRA114) || \ 16 defined(CONFIG_TEGRA124) || defined(CONFIG_TEGRA210) 17 #define NVBL_PLLP_KHZ 408000 18 #define CSITE_KHZ 136000 19 #else 20 #error "Unknown Tegra chip!" 21 #endif 22 23 #define PLLX_ENABLED (1 << 30) 24 #define CCLK_BURST_POLICY 0x20008888 25 #define SUPER_CCLK_DIVIDER 0x80000000 26 27 /* Calculate clock fractional divider value from ref and target frequencies */ 28 #define CLK_DIVIDER(REF, FREQ) ((((REF) * 2) / FREQ) - 2) 29 30 /* Calculate clock frequency value from reference and clock divider value */ 31 #define CLK_FREQUENCY(REF, REG) (((REF) * 2) / (REG + 2)) 32 33 /* AVP/CPU ID */ 34 #define PG_UP_TAG_0_PID_CPU 0x55555555 /* CPU aka "a9" aka "mpcore" */ 35 #define PG_UP_TAG_0 0x0 36 37 #define CORESIGHT_UNLOCK 0xC5ACCE55 38 39 #define EXCEP_VECTOR_CPU_RESET_VECTOR (NV_PA_EVP_BASE + 0x100) 40 #define CSITE_CPU_DBG0_LAR (NV_PA_CSITE_BASE + 0x10FB0) 41 #define CSITE_CPU_DBG1_LAR (NV_PA_CSITE_BASE + 0x12FB0) 42 #define CSITE_CPU_DBG2_LAR (NV_PA_CSITE_BASE + 0x14FB0) 43 #define CSITE_CPU_DBG3_LAR (NV_PA_CSITE_BASE + 0x16FB0) 44 45 #define FLOW_CTLR_HALT_COP_EVENTS (NV_PA_FLOW_BASE + 4) 46 #define FLOW_MODE_STOP 2 47 #define HALT_COP_EVENT_JTAG (1 << 28) 48 #define HALT_COP_EVENT_IRQ_1 (1 << 11) 49 #define HALT_COP_EVENT_FIQ_1 (1 << 9) 50 51 #define FLOW_MODE_NONE 0 52 53 #define SIMPLE_PLLX (CLOCK_ID_XCPU - CLOCK_ID_FIRST_SIMPLE) 54 55 /* SB_AA64_RESET_LOW and _HIGH defines for CPU reset vector */ 56 #define SB_AA64_RESET_LOW 0x6000C230 57 #define SB_AA64_RESET_HIGH 0x6000C234 58 59 struct clk_pll_table { 60 u16 n; 61 u16 m; 62 u8 p; 63 u8 cpcon; 64 }; 65 66 void clock_enable_coresight(int enable); 67 void enable_cpu_clock(int enable); 68 void halt_avp(void) __attribute__ ((noreturn)); 69 void init_pllx(void); 70 void powerup_cpu(void); 71 void reset_A9_cpu(int reset); 72 void start_cpu(u32 reset_vector); 73 int tegra_get_chip(void); 74 int tegra_get_sku_info(void); 75 int tegra_get_chip_sku(void); 76 void adjust_pllp_out_freqs(void); 77 void pmic_enable_cpu_vdd(void); 78