1 /* 2 * (C) Copyright 2010-2015 3 * NVIDIA Corporation <www.nvidia.com> 4 * 5 * SPDX-License-Identifier: GPL-2.0+ 6 */ 7 #include <asm/types.h> 8 9 /* Stabilization delays, in usec */ 10 #define PLL_STABILIZATION_DELAY (300) 11 #define IO_STABILIZATION_DELAY (1000) 12 13 #if defined(CONFIG_TEGRA20) 14 #define NVBL_PLLP_KHZ 216000 15 #define CSITE_KHZ 144000 16 #elif defined(CONFIG_TEGRA30) || defined(CONFIG_TEGRA114) || \ 17 defined(CONFIG_TEGRA124) || defined(CONFIG_TEGRA210) 18 #define NVBL_PLLP_KHZ 408000 19 #define CSITE_KHZ 136000 20 #else 21 #error "Unknown Tegra chip!" 22 #endif 23 24 #define PLLX_ENABLED (1 << 30) 25 #define CCLK_BURST_POLICY 0x20008888 26 #define SUPER_CCLK_DIVIDER 0x80000000 27 28 /* Calculate clock fractional divider value from ref and target frequencies */ 29 #define CLK_DIVIDER(REF, FREQ) ((((REF) * 2) / FREQ) - 2) 30 31 /* Calculate clock frequency value from reference and clock divider value */ 32 #define CLK_FREQUENCY(REF, REG) (((REF) * 2) / (REG + 2)) 33 34 /* AVP/CPU ID */ 35 #define PG_UP_TAG_0_PID_CPU 0x55555555 /* CPU aka "a9" aka "mpcore" */ 36 #define PG_UP_TAG_0 0x0 37 38 #define CORESIGHT_UNLOCK 0xC5ACCE55 39 40 #define EXCEP_VECTOR_CPU_RESET_VECTOR (NV_PA_EVP_BASE + 0x100) 41 #define CSITE_CPU_DBG0_LAR (NV_PA_CSITE_BASE + 0x10FB0) 42 #define CSITE_CPU_DBG1_LAR (NV_PA_CSITE_BASE + 0x12FB0) 43 #define CSITE_CPU_DBG2_LAR (NV_PA_CSITE_BASE + 0x14FB0) 44 #define CSITE_CPU_DBG3_LAR (NV_PA_CSITE_BASE + 0x16FB0) 45 46 #define FLOW_CTLR_HALT_COP_EVENTS (NV_PA_FLOW_BASE + 4) 47 #define FLOW_MODE_STOP 2 48 #define HALT_COP_EVENT_JTAG (1 << 28) 49 #define HALT_COP_EVENT_IRQ_1 (1 << 11) 50 #define HALT_COP_EVENT_FIQ_1 (1 << 9) 51 52 #define FLOW_MODE_NONE 0 53 54 #define SIMPLE_PLLX (CLOCK_ID_XCPU - CLOCK_ID_FIRST_SIMPLE) 55 56 /* SB_AA64_RESET_LOW and _HIGH defines for CPU reset vector */ 57 #define SB_AA64_RESET_LOW 0x6000C230 58 #define SB_AA64_RESET_HIGH 0x6000C234 59 60 struct clk_pll_table { 61 u16 n; 62 u16 m; 63 u8 p; 64 u8 cpcon; 65 }; 66 67 void clock_enable_coresight(int enable); 68 void enable_cpu_clock(int enable); 69 void halt_avp(void) __attribute__ ((noreturn)); 70 void init_pllx(void); 71 void powerup_cpu(void); 72 void reset_A9_cpu(int reset); 73 void start_cpu(u32 reset_vector); 74 int tegra_get_chip(void); 75 int tegra_get_sku_info(void); 76 int tegra_get_chip_sku(void); 77 void adjust_pllp_out_freqs(void); 78 void pmic_enable_cpu_vdd(void); 79