1 /* 2 * Copyright (c) 2010-2015, NVIDIA CORPORATION. All rights reserved. 3 * 4 * This program is free software; you can redistribute it and/or modify it 5 * under the terms and conditions of the GNU General Public License, 6 * version 2, as published by the Free Software Foundation. 7 * 8 * This program is distributed in the hope it will be useful, but WITHOUT 9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 11 * more details. 12 * 13 * You should have received a copy of the GNU General Public License 14 * along with this program. If not, see <http://www.gnu.org/licenses/>. 15 */ 16 17 #include <common.h> 18 #include <asm/io.h> 19 #include <asm/arch/clock.h> 20 #include <asm/arch/gp_padctrl.h> 21 #include <asm/arch/pinmux.h> 22 #include <asm/arch/tegra.h> 23 #include <asm/arch-tegra/clk_rst.h> 24 #include <asm/arch-tegra/pmc.h> 25 #include <asm/arch-tegra/scu.h> 26 #include "cpu.h" 27 28 int get_num_cpus(void) 29 { 30 struct apb_misc_gp_ctlr *gp; 31 uint rev; 32 debug("%s entry\n", __func__); 33 34 gp = (struct apb_misc_gp_ctlr *)NV_PA_APB_MISC_GP_BASE; 35 rev = (readl(&gp->hidrev) & HIDREV_CHIPID_MASK) >> HIDREV_CHIPID_SHIFT; 36 37 switch (rev) { 38 case CHIPID_TEGRA20: 39 return 2; 40 break; 41 case CHIPID_TEGRA30: 42 case CHIPID_TEGRA114: 43 case CHIPID_TEGRA124: 44 case CHIPID_TEGRA210: 45 default: 46 return 4; 47 break; 48 } 49 } 50 51 /* 52 * Timing tables for each SOC for all four oscillator options. 53 */ 54 struct clk_pll_table tegra_pll_x_table[TEGRA_SOC_CNT][CLOCK_OSC_FREQ_COUNT] = { 55 /* 56 * T20: 1 GHz 57 * 58 * Register Field Bits Width 59 * ------------------------------ 60 * PLLX_BASE p 22:20 3 61 * PLLX_BASE n 17: 8 10 62 * PLLX_BASE m 4: 0 5 63 * PLLX_MISC cpcon 11: 8 4 64 */ 65 { 66 { .n = 1000, .m = 13, .p = 0, .cpcon = 12 }, /* OSC: 13.0 MHz */ 67 { .n = 625, .m = 12, .p = 0, .cpcon = 8 }, /* OSC: 19.2 MHz */ 68 { .n = 1000, .m = 12, .p = 0, .cpcon = 12 }, /* OSC: 12.0 MHz */ 69 { .n = 1000, .m = 26, .p = 0, .cpcon = 12 }, /* OSC: 26.0 MHz */ 70 }, 71 /* 72 * T25: 1.2 GHz 73 * 74 * Register Field Bits Width 75 * ------------------------------ 76 * PLLX_BASE p 22:20 3 77 * PLLX_BASE n 17: 8 10 78 * PLLX_BASE m 4: 0 5 79 * PLLX_MISC cpcon 11: 8 4 80 */ 81 { 82 { .n = 923, .m = 10, .p = 0, .cpcon = 12 }, /* OSC: 13.0 MHz */ 83 { .n = 750, .m = 12, .p = 0, .cpcon = 8 }, /* OSC: 19.2 MHz */ 84 { .n = 600, .m = 6, .p = 0, .cpcon = 12 }, /* OSC: 12.0 MHz */ 85 { .n = 600, .m = 13, .p = 0, .cpcon = 12 }, /* OSC: 26.0 MHz */ 86 }, 87 /* 88 * T30: 600 MHz 89 * 90 * Register Field Bits Width 91 * ------------------------------ 92 * PLLX_BASE p 22:20 3 93 * PLLX_BASE n 17: 8 10 94 * PLLX_BASE m 4: 0 5 95 * PLLX_MISC cpcon 11: 8 4 96 */ 97 { 98 { .n = 600, .m = 13, .p = 0, .cpcon = 8 }, /* OSC: 13.0 MHz */ 99 { .n = 500, .m = 16, .p = 0, .cpcon = 8 }, /* OSC: 19.2 MHz */ 100 { .n = 600, .m = 12, .p = 0, .cpcon = 8 }, /* OSC: 12.0 MHz */ 101 { .n = 600, .m = 26, .p = 0, .cpcon = 8 }, /* OSC: 26.0 MHz */ 102 }, 103 /* 104 * T114: 700 MHz 105 * 106 * Register Field Bits Width 107 * ------------------------------ 108 * PLLX_BASE p 23:20 4 109 * PLLX_BASE n 15: 8 8 110 * PLLX_BASE m 7: 0 8 111 */ 112 { 113 { .n = 108, .m = 1, .p = 1 }, /* OSC: 13.0 MHz */ 114 { .n = 73, .m = 1, .p = 1 }, /* OSC: 19.2 MHz */ 115 { .n = 116, .m = 1, .p = 1 }, /* OSC: 12.0 MHz */ 116 { .n = 108, .m = 2, .p = 1 }, /* OSC: 26.0 MHz */ 117 }, 118 119 /* 120 * T124: 700 MHz 121 * 122 * Register Field Bits Width 123 * ------------------------------ 124 * PLLX_BASE p 23:20 4 125 * PLLX_BASE n 15: 8 8 126 * PLLX_BASE m 7: 0 8 127 */ 128 { 129 { .n = 108, .m = 1, .p = 1 }, /* OSC: 13.0 MHz */ 130 { .n = 73, .m = 1, .p = 1 }, /* OSC: 19.2 MHz */ 131 { .n = 116, .m = 1, .p = 1 }, /* OSC: 12.0 MHz */ 132 { .n = 108, .m = 2, .p = 1 }, /* OSC: 26.0 MHz */ 133 }, 134 135 /* 136 * T210: 700 MHz 137 * 138 * Register Field Bits Width 139 * ------------------------------ 140 * PLLX_BASE p 24:20 5 141 * PLLX_BASE n 15: 8 8 142 * PLLX_BASE m 7: 0 8 143 */ 144 { 145 { .n = 108, .m = 1, .p = 1 }, /* OSC: 13.0 MHz = 702 MHz*/ 146 { .n = 73, .m = 1, .p = 1 }, /* OSC: 19.2 MHz = 700.8 MHz*/ 147 { .n = 116, .m = 1, .p = 1 }, /* OSC: 12.0 MHz = 696 MHz*/ 148 { .n = 108, .m = 2, .p = 1 }, /* OSC: 26.0 MHz = 702 MHz*/ 149 }, 150 }; 151 152 static inline void pllx_set_iddq(void) 153 { 154 #if defined(CONFIG_TEGRA124) || defined(CONFIG_TEGRA210) 155 struct clk_rst_ctlr *clkrst = (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE; 156 u32 reg; 157 debug("%s entry\n", __func__); 158 159 /* Disable IDDQ */ 160 reg = readl(&clkrst->crc_pllx_misc3); 161 reg &= ~PLLX_IDDQ_MASK; 162 writel(reg, &clkrst->crc_pllx_misc3); 163 udelay(2); 164 debug("%s: IDDQ: PLLX IDDQ = 0x%08X\n", __func__, 165 readl(&clkrst->crc_pllx_misc3)); 166 #endif 167 } 168 169 int pllx_set_rate(struct clk_pll_simple *pll , u32 divn, u32 divm, 170 u32 divp, u32 cpcon) 171 { 172 int chip = tegra_get_chip(); 173 u32 reg; 174 debug("%s entry\n", __func__); 175 176 /* If PLLX is already enabled, just return */ 177 if (readl(&pll->pll_base) & PLL_ENABLE_MASK) { 178 debug("%s: PLLX already enabled, returning\n", __func__); 179 return 0; 180 } 181 182 pllx_set_iddq(); 183 184 /* Set BYPASS, m, n and p to PLLX_BASE */ 185 reg = PLL_BYPASS_MASK | (divm << PLL_DIVM_SHIFT); 186 reg |= ((divn << PLL_DIVN_SHIFT) | (divp << PLL_DIVP_SHIFT)); 187 writel(reg, &pll->pll_base); 188 189 /* Set cpcon to PLLX_MISC */ 190 if (chip == CHIPID_TEGRA20 || chip == CHIPID_TEGRA30) 191 reg = (cpcon << PLL_CPCON_SHIFT); 192 else 193 reg = 0; 194 195 /* Set dccon to PLLX_MISC if freq > 600MHz */ 196 if (divn > 600) 197 reg |= (1 << PLL_DCCON_SHIFT); 198 writel(reg, &pll->pll_misc); 199 200 /* Disable BYPASS */ 201 reg = readl(&pll->pll_base); 202 reg &= ~PLL_BYPASS_MASK; 203 writel(reg, &pll->pll_base); 204 debug("%s: base = 0x%08X\n", __func__, reg); 205 206 /* Set lock_enable to PLLX_MISC */ 207 reg = readl(&pll->pll_misc); 208 reg |= PLL_LOCK_ENABLE_MASK; 209 writel(reg, &pll->pll_misc); 210 debug("%s: misc = 0x%08X\n", __func__, reg); 211 212 /* Enable PLLX last, once it's all configured */ 213 reg = readl(&pll->pll_base); 214 reg |= PLL_ENABLE_MASK; 215 writel(reg, &pll->pll_base); 216 debug("%s: base final = 0x%08X\n", __func__, reg); 217 218 return 0; 219 } 220 221 void init_pllx(void) 222 { 223 struct clk_rst_ctlr *clkrst = (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE; 224 struct clk_pll_simple *pll = &clkrst->crc_pll_simple[SIMPLE_PLLX]; 225 int soc_type, sku_info, chip_sku; 226 enum clock_osc_freq osc; 227 struct clk_pll_table *sel; 228 debug("%s entry\n", __func__); 229 230 /* get SOC (chip) type */ 231 soc_type = tegra_get_chip(); 232 debug("%s: SoC = 0x%02X\n", __func__, soc_type); 233 234 /* get SKU info */ 235 sku_info = tegra_get_sku_info(); 236 debug("%s: SKU info byte = 0x%02X\n", __func__, sku_info); 237 238 /* get chip SKU, combo of the above info */ 239 chip_sku = tegra_get_chip_sku(); 240 debug("%s: Chip SKU = %d\n", __func__, chip_sku); 241 242 /* get osc freq */ 243 osc = clock_get_osc_freq(); 244 debug("%s: osc = %d\n", __func__, osc); 245 246 /* set pllx */ 247 sel = &tegra_pll_x_table[chip_sku][osc]; 248 pllx_set_rate(pll, sel->n, sel->m, sel->p, sel->cpcon); 249 } 250 251 void enable_cpu_clock(int enable) 252 { 253 struct clk_rst_ctlr *clkrst = (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE; 254 u32 clk; 255 debug("%s entry\n", __func__); 256 257 /* 258 * NOTE: 259 * Regardless of whether the request is to enable or disable the CPU 260 * clock, every processor in the CPU complex except the master (CPU 0) 261 * will have it's clock stopped because the AVP only talks to the 262 * master. 263 */ 264 265 if (enable) { 266 /* Initialize PLLX */ 267 init_pllx(); 268 269 /* Wait until all clocks are stable */ 270 udelay(PLL_STABILIZATION_DELAY); 271 272 writel(CCLK_BURST_POLICY, &clkrst->crc_cclk_brst_pol); 273 writel(SUPER_CCLK_DIVIDER, &clkrst->crc_super_cclk_div); 274 } 275 276 /* 277 * Read the register containing the individual CPU clock enables and 278 * always stop the clocks to CPUs > 0. 279 */ 280 clk = readl(&clkrst->crc_clk_cpu_cmplx); 281 clk |= 1 << CPU1_CLK_STP_SHIFT; 282 if (get_num_cpus() == 4) 283 clk |= (1 << CPU2_CLK_STP_SHIFT) + (1 << CPU3_CLK_STP_SHIFT); 284 285 /* Stop/Unstop the CPU clock */ 286 clk &= ~CPU0_CLK_STP_MASK; 287 clk |= !enable << CPU0_CLK_STP_SHIFT; 288 writel(clk, &clkrst->crc_clk_cpu_cmplx); 289 290 clock_enable(PERIPH_ID_CPU); 291 } 292 293 static int is_cpu_powered(void) 294 { 295 struct pmc_ctlr *pmc = (struct pmc_ctlr *)NV_PA_PMC_BASE; 296 297 return (readl(&pmc->pmc_pwrgate_status) & CPU_PWRED) ? 1 : 0; 298 } 299 300 static void remove_cpu_io_clamps(void) 301 { 302 struct pmc_ctlr *pmc = (struct pmc_ctlr *)NV_PA_PMC_BASE; 303 u32 reg; 304 debug("%s entry\n", __func__); 305 306 /* Remove the clamps on the CPU I/O signals */ 307 reg = readl(&pmc->pmc_remove_clamping); 308 reg |= CPU_CLMP; 309 writel(reg, &pmc->pmc_remove_clamping); 310 311 /* Give I/O signals time to stabilize */ 312 udelay(IO_STABILIZATION_DELAY); 313 } 314 315 void powerup_cpu(void) 316 { 317 struct pmc_ctlr *pmc = (struct pmc_ctlr *)NV_PA_PMC_BASE; 318 u32 reg; 319 int timeout = IO_STABILIZATION_DELAY; 320 debug("%s entry\n", __func__); 321 322 if (!is_cpu_powered()) { 323 /* Toggle the CPU power state (OFF -> ON) */ 324 reg = readl(&pmc->pmc_pwrgate_toggle); 325 reg &= PARTID_CP; 326 reg |= START_CP; 327 writel(reg, &pmc->pmc_pwrgate_toggle); 328 329 /* Wait for the power to come up */ 330 while (!is_cpu_powered()) { 331 if (timeout-- == 0) 332 printf("CPU failed to power up!\n"); 333 else 334 udelay(10); 335 } 336 337 /* 338 * Remove the I/O clamps from CPU power partition. 339 * Recommended only on a Warm boot, if the CPU partition gets 340 * power gated. Shouldn't cause any harm when called after a 341 * cold boot according to HW, probably just redundant. 342 */ 343 remove_cpu_io_clamps(); 344 } 345 } 346 347 void reset_A9_cpu(int reset) 348 { 349 /* 350 * NOTE: Regardless of whether the request is to hold the CPU in reset 351 * or take it out of reset, every processor in the CPU complex 352 * except the master (CPU 0) will be held in reset because the 353 * AVP only talks to the master. The AVP does not know that there 354 * are multiple processors in the CPU complex. 355 */ 356 int mask = crc_rst_cpu | crc_rst_de | crc_rst_debug; 357 int num_cpus = get_num_cpus(); 358 int cpu; 359 360 debug("%s entry\n", __func__); 361 /* Hold CPUs 1 onwards in reset, and CPU 0 if asked */ 362 for (cpu = 1; cpu < num_cpus; cpu++) 363 reset_cmplx_set_enable(cpu, mask, 1); 364 reset_cmplx_set_enable(0, mask, reset); 365 366 /* Enable/Disable master CPU reset */ 367 reset_set_enable(PERIPH_ID_CPU, reset); 368 } 369 370 void clock_enable_coresight(int enable) 371 { 372 u32 rst, src = 2; 373 374 debug("%s entry\n", __func__); 375 clock_set_enable(PERIPH_ID_CORESIGHT, enable); 376 reset_set_enable(PERIPH_ID_CORESIGHT, !enable); 377 378 if (enable) { 379 /* 380 * Put CoreSight on PLLP_OUT0 and divide it down as per 381 * PLLP base frequency based on SoC type (T20/T30+). 382 * Clock divider request would setup CSITE clock as 144MHz 383 * for PLLP base 216MHz and 204MHz for PLLP base 408MHz 384 */ 385 src = CLK_DIVIDER(NVBL_PLLP_KHZ, CSITE_KHZ); 386 clock_ll_set_source_divisor(PERIPH_ID_CSI, 0, src); 387 388 /* Unlock the CPU CoreSight interfaces */ 389 rst = CORESIGHT_UNLOCK; 390 writel(rst, CSITE_CPU_DBG0_LAR); 391 writel(rst, CSITE_CPU_DBG1_LAR); 392 if (get_num_cpus() == 4) { 393 writel(rst, CSITE_CPU_DBG2_LAR); 394 writel(rst, CSITE_CPU_DBG3_LAR); 395 } 396 } 397 } 398 399 void halt_avp(void) 400 { 401 debug("%s entry\n", __func__); 402 403 for (;;) { 404 writel(HALT_COP_EVENT_JTAG | (FLOW_MODE_STOP << 29), 405 FLOW_CTLR_HALT_COP_EVENTS); 406 } 407 } 408