1 /* 2 * Copyright (c) 2010-2015, NVIDIA CORPORATION. All rights reserved. 3 * 4 * This program is free software; you can redistribute it and/or modify it 5 * under the terms and conditions of the GNU General Public License, 6 * version 2, as published by the Free Software Foundation. 7 * 8 * This program is distributed in the hope it will be useful, but WITHOUT 9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 11 * more details. 12 * 13 * You should have received a copy of the GNU General Public License 14 * along with this program. If not, see <http://www.gnu.org/licenses/>. 15 */ 16 17 #include <common.h> 18 #include <asm/io.h> 19 #include <asm/arch/clock.h> 20 #include <asm/arch/gp_padctrl.h> 21 #include <asm/arch/pinmux.h> 22 #include <asm/arch/tegra.h> 23 #include <asm/arch-tegra/clk_rst.h> 24 #include <asm/arch-tegra/pmc.h> 25 #include <asm/arch-tegra/scu.h> 26 #include "cpu.h" 27 28 int get_num_cpus(void) 29 { 30 struct apb_misc_gp_ctlr *gp; 31 uint rev; 32 debug("%s entry\n", __func__); 33 34 gp = (struct apb_misc_gp_ctlr *)NV_PA_APB_MISC_GP_BASE; 35 rev = (readl(&gp->hidrev) & HIDREV_CHIPID_MASK) >> HIDREV_CHIPID_SHIFT; 36 37 switch (rev) { 38 case CHIPID_TEGRA20: 39 return 2; 40 break; 41 case CHIPID_TEGRA30: 42 case CHIPID_TEGRA114: 43 case CHIPID_TEGRA124: 44 case CHIPID_TEGRA210: 45 default: 46 return 4; 47 break; 48 } 49 } 50 51 /* 52 * Timing tables for each SOC for all four oscillator options. 53 */ 54 struct clk_pll_table tegra_pll_x_table[TEGRA_SOC_CNT][CLOCK_OSC_FREQ_COUNT] = { 55 /* 56 * T20: 1 GHz 57 * 58 * Register Field Bits Width 59 * ------------------------------ 60 * PLLX_BASE p 22:20 3 61 * PLLX_BASE n 17: 8 10 62 * PLLX_BASE m 4: 0 5 63 * PLLX_MISC cpcon 11: 8 4 64 */ 65 { 66 { .n = 1000, .m = 13, .p = 0, .cpcon = 12 }, /* OSC: 13.0 MHz */ 67 { .n = 625, .m = 12, .p = 0, .cpcon = 8 }, /* OSC: 19.2 MHz */ 68 { .n = 1000, .m = 12, .p = 0, .cpcon = 12 }, /* OSC: 12.0 MHz */ 69 { .n = 1000, .m = 26, .p = 0, .cpcon = 12 }, /* OSC: 26.0 MHz */ 70 { .n = 0, .m = 0, .p = 0, .cpcon = 0 }, /* OSC: 38.4 MHz (N/A) */ 71 { .n = 0, .m = 0, .p = 0, .cpcon = 0 }, /* OSC: 48.0 MHz (N/A) */ 72 }, 73 /* 74 * T25: 1.2 GHz 75 * 76 * Register Field Bits Width 77 * ------------------------------ 78 * PLLX_BASE p 22:20 3 79 * PLLX_BASE n 17: 8 10 80 * PLLX_BASE m 4: 0 5 81 * PLLX_MISC cpcon 11: 8 4 82 */ 83 { 84 { .n = 923, .m = 10, .p = 0, .cpcon = 12 }, /* OSC: 13.0 MHz */ 85 { .n = 750, .m = 12, .p = 0, .cpcon = 8 }, /* OSC: 19.2 MHz */ 86 { .n = 600, .m = 6, .p = 0, .cpcon = 12 }, /* OSC: 12.0 MHz */ 87 { .n = 600, .m = 13, .p = 0, .cpcon = 12 }, /* OSC: 26.0 MHz */ 88 { .n = 0, .m = 0, .p = 0, .cpcon = 0 }, /* OSC: 38.4 MHz (N/A) */ 89 { .n = 0, .m = 0, .p = 0, .cpcon = 0 }, /* OSC: 48.0 MHz (N/A) */ 90 }, 91 /* 92 * T30: 600 MHz 93 * 94 * Register Field Bits Width 95 * ------------------------------ 96 * PLLX_BASE p 22:20 3 97 * PLLX_BASE n 17: 8 10 98 * PLLX_BASE m 4: 0 5 99 * PLLX_MISC cpcon 11: 8 4 100 */ 101 { 102 { .n = 600, .m = 13, .p = 0, .cpcon = 8 }, /* OSC: 13.0 MHz */ 103 { .n = 500, .m = 16, .p = 0, .cpcon = 8 }, /* OSC: 19.2 MHz */ 104 { .n = 600, .m = 12, .p = 0, .cpcon = 8 }, /* OSC: 12.0 MHz */ 105 { .n = 600, .m = 26, .p = 0, .cpcon = 8 }, /* OSC: 26.0 MHz */ 106 { .n = 0, .m = 0, .p = 0, .cpcon = 0 }, /* OSC: 38.4 MHz (N/A) */ 107 { .n = 0, .m = 0, .p = 0, .cpcon = 0 }, /* OSC: 48.0 MHz (N/A) */ 108 }, 109 /* 110 * T114: 700 MHz 111 * 112 * Register Field Bits Width 113 * ------------------------------ 114 * PLLX_BASE p 23:20 4 115 * PLLX_BASE n 15: 8 8 116 * PLLX_BASE m 7: 0 8 117 */ 118 { 119 { .n = 108, .m = 1, .p = 1 }, /* OSC: 13.0 MHz */ 120 { .n = 73, .m = 1, .p = 1 }, /* OSC: 19.2 MHz */ 121 { .n = 116, .m = 1, .p = 1 }, /* OSC: 12.0 MHz */ 122 { .n = 108, .m = 2, .p = 1 }, /* OSC: 26.0 MHz */ 123 { .n = 0, .m = 0, .p = 0 }, /* OSC: 38.4 MHz (N/A) */ 124 { .n = 0, .m = 0, .p = 0 }, /* OSC: 48.0 MHz (N/A) */ 125 }, 126 127 /* 128 * T124: 700 MHz 129 * 130 * Register Field Bits Width 131 * ------------------------------ 132 * PLLX_BASE p 23:20 4 133 * PLLX_BASE n 15: 8 8 134 * PLLX_BASE m 7: 0 8 135 */ 136 { 137 { .n = 108, .m = 1, .p = 1 }, /* OSC: 13.0 MHz */ 138 { .n = 73, .m = 1, .p = 1 }, /* OSC: 19.2 MHz */ 139 { .n = 116, .m = 1, .p = 1 }, /* OSC: 12.0 MHz */ 140 { .n = 108, .m = 2, .p = 1 }, /* OSC: 26.0 MHz */ 141 { .n = 0, .m = 0, .p = 0 }, /* OSC: 38.4 MHz (N/A) */ 142 { .n = 0, .m = 0, .p = 0 }, /* OSC: 48.0 MHz (N/A) */ 143 }, 144 145 /* 146 * T210: 700 MHz 147 * 148 * Register Field Bits Width 149 * ------------------------------ 150 * PLLX_BASE p 24:20 5 151 * PLLX_BASE n 15: 8 8 152 * PLLX_BASE m 7: 0 8 153 */ 154 { 155 { .n = 108, .m = 1, .p = 1 }, /* OSC: 13.0 MHz = 702 MHz*/ 156 { .n = 73, .m = 1, .p = 1 }, /* OSC: 19.2 MHz = 700.8 MHz*/ 157 { .n = 116, .m = 1, .p = 1 }, /* OSC: 12.0 MHz = 696 MHz*/ 158 { .n = 108, .m = 2, .p = 1 }, /* OSC: 26.0 MHz = 702 MHz*/ 159 { .n = 36, .m = 1, .p = 1 }, /* OSC: 38.4 MHz = 691.2 MHz */ 160 { .n = 58, .m = 2, .p = 1 }, /* OSC: 48.0 MHz = 696 MHz */ 161 }, 162 }; 163 164 static inline void pllx_set_iddq(void) 165 { 166 #if defined(CONFIG_TEGRA124) || defined(CONFIG_TEGRA210) 167 struct clk_rst_ctlr *clkrst = (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE; 168 u32 reg; 169 debug("%s entry\n", __func__); 170 171 /* Disable IDDQ */ 172 reg = readl(&clkrst->crc_pllx_misc3); 173 reg &= ~PLLX_IDDQ_MASK; 174 writel(reg, &clkrst->crc_pllx_misc3); 175 udelay(2); 176 debug("%s: IDDQ: PLLX IDDQ = 0x%08X\n", __func__, 177 readl(&clkrst->crc_pllx_misc3)); 178 #endif 179 } 180 181 int pllx_set_rate(struct clk_pll_simple *pll , u32 divn, u32 divm, 182 u32 divp, u32 cpcon) 183 { 184 struct clk_pll_info *pllinfo = &tegra_pll_info_table[CLOCK_ID_XCPU]; 185 int chip = tegra_get_chip(); 186 u32 reg; 187 debug("%s entry\n", __func__); 188 189 /* If PLLX is already enabled, just return */ 190 if (readl(&pll->pll_base) & PLL_ENABLE_MASK) { 191 debug("%s: PLLX already enabled, returning\n", __func__); 192 return 0; 193 } 194 195 pllx_set_iddq(); 196 197 /* Set BYPASS, m, n and p to PLLX_BASE */ 198 reg = PLL_BYPASS_MASK | (divm << pllinfo->m_shift); 199 reg |= (divn << pllinfo->n_shift) | (divp << pllinfo->p_shift); 200 writel(reg, &pll->pll_base); 201 202 /* Set cpcon to PLLX_MISC */ 203 if (chip == CHIPID_TEGRA20 || chip == CHIPID_TEGRA30) 204 reg = (cpcon << pllinfo->kcp_shift); 205 else 206 reg = 0; 207 208 /* 209 * TODO(twarren@nvidia.com) Check which SoCs use DCCON 210 * and add to pllinfo table if needed! 211 */ 212 /* Set dccon to PLLX_MISC if freq > 600MHz */ 213 if (divn > 600) 214 reg |= (1 << PLL_DCCON_SHIFT); 215 writel(reg, &pll->pll_misc); 216 217 /* Disable BYPASS */ 218 reg = readl(&pll->pll_base); 219 reg &= ~PLL_BYPASS_MASK; 220 writel(reg, &pll->pll_base); 221 debug("%s: base = 0x%08X\n", __func__, reg); 222 223 /* Set lock_enable to PLLX_MISC if lock_ena is valid (i.e. 0-31) */ 224 reg = readl(&pll->pll_misc); 225 if (pllinfo->lock_ena < 32) 226 reg |= (1 << pllinfo->lock_ena); 227 writel(reg, &pll->pll_misc); 228 debug("%s: misc = 0x%08X\n", __func__, reg); 229 230 /* Enable PLLX last, once it's all configured */ 231 reg = readl(&pll->pll_base); 232 reg |= PLL_ENABLE_MASK; 233 writel(reg, &pll->pll_base); 234 debug("%s: base final = 0x%08X\n", __func__, reg); 235 236 return 0; 237 } 238 239 void init_pllx(void) 240 { 241 struct clk_rst_ctlr *clkrst = (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE; 242 struct clk_pll_simple *pll = &clkrst->crc_pll_simple[SIMPLE_PLLX]; 243 int soc_type, sku_info, chip_sku; 244 enum clock_osc_freq osc; 245 struct clk_pll_table *sel; 246 debug("%s entry\n", __func__); 247 248 /* get SOC (chip) type */ 249 soc_type = tegra_get_chip(); 250 debug("%s: SoC = 0x%02X\n", __func__, soc_type); 251 252 /* get SKU info */ 253 sku_info = tegra_get_sku_info(); 254 debug("%s: SKU info byte = 0x%02X\n", __func__, sku_info); 255 256 /* get chip SKU, combo of the above info */ 257 chip_sku = tegra_get_chip_sku(); 258 debug("%s: Chip SKU = %d\n", __func__, chip_sku); 259 260 /* get osc freq */ 261 osc = clock_get_osc_freq(); 262 debug("%s: osc = %d\n", __func__, osc); 263 264 /* set pllx */ 265 sel = &tegra_pll_x_table[chip_sku][osc]; 266 pllx_set_rate(pll, sel->n, sel->m, sel->p, sel->cpcon); 267 } 268 269 void enable_cpu_clock(int enable) 270 { 271 struct clk_rst_ctlr *clkrst = (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE; 272 u32 clk; 273 debug("%s entry\n", __func__); 274 275 /* 276 * NOTE: 277 * Regardless of whether the request is to enable or disable the CPU 278 * clock, every processor in the CPU complex except the master (CPU 0) 279 * will have it's clock stopped because the AVP only talks to the 280 * master. 281 */ 282 283 if (enable) { 284 /* Initialize PLLX */ 285 init_pllx(); 286 287 /* Wait until all clocks are stable */ 288 udelay(PLL_STABILIZATION_DELAY); 289 290 writel(CCLK_BURST_POLICY, &clkrst->crc_cclk_brst_pol); 291 writel(SUPER_CCLK_DIVIDER, &clkrst->crc_super_cclk_div); 292 } 293 294 /* 295 * Read the register containing the individual CPU clock enables and 296 * always stop the clocks to CPUs > 0. 297 */ 298 clk = readl(&clkrst->crc_clk_cpu_cmplx); 299 clk |= 1 << CPU1_CLK_STP_SHIFT; 300 if (get_num_cpus() == 4) 301 clk |= (1 << CPU2_CLK_STP_SHIFT) + (1 << CPU3_CLK_STP_SHIFT); 302 303 /* Stop/Unstop the CPU clock */ 304 clk &= ~CPU0_CLK_STP_MASK; 305 clk |= !enable << CPU0_CLK_STP_SHIFT; 306 writel(clk, &clkrst->crc_clk_cpu_cmplx); 307 308 clock_enable(PERIPH_ID_CPU); 309 } 310 311 static int is_cpu_powered(void) 312 { 313 struct pmc_ctlr *pmc = (struct pmc_ctlr *)NV_PA_PMC_BASE; 314 315 return (readl(&pmc->pmc_pwrgate_status) & CPU_PWRED) ? 1 : 0; 316 } 317 318 static void remove_cpu_io_clamps(void) 319 { 320 struct pmc_ctlr *pmc = (struct pmc_ctlr *)NV_PA_PMC_BASE; 321 u32 reg; 322 debug("%s entry\n", __func__); 323 324 /* Remove the clamps on the CPU I/O signals */ 325 reg = readl(&pmc->pmc_remove_clamping); 326 reg |= CPU_CLMP; 327 writel(reg, &pmc->pmc_remove_clamping); 328 329 /* Give I/O signals time to stabilize */ 330 udelay(IO_STABILIZATION_DELAY); 331 } 332 333 void powerup_cpu(void) 334 { 335 struct pmc_ctlr *pmc = (struct pmc_ctlr *)NV_PA_PMC_BASE; 336 u32 reg; 337 int timeout = IO_STABILIZATION_DELAY; 338 debug("%s entry\n", __func__); 339 340 if (!is_cpu_powered()) { 341 /* Toggle the CPU power state (OFF -> ON) */ 342 reg = readl(&pmc->pmc_pwrgate_toggle); 343 reg &= PARTID_CP; 344 reg |= START_CP; 345 writel(reg, &pmc->pmc_pwrgate_toggle); 346 347 /* Wait for the power to come up */ 348 while (!is_cpu_powered()) { 349 if (timeout-- == 0) 350 printf("CPU failed to power up!\n"); 351 else 352 udelay(10); 353 } 354 355 /* 356 * Remove the I/O clamps from CPU power partition. 357 * Recommended only on a Warm boot, if the CPU partition gets 358 * power gated. Shouldn't cause any harm when called after a 359 * cold boot according to HW, probably just redundant. 360 */ 361 remove_cpu_io_clamps(); 362 } 363 } 364 365 void reset_A9_cpu(int reset) 366 { 367 /* 368 * NOTE: Regardless of whether the request is to hold the CPU in reset 369 * or take it out of reset, every processor in the CPU complex 370 * except the master (CPU 0) will be held in reset because the 371 * AVP only talks to the master. The AVP does not know that there 372 * are multiple processors in the CPU complex. 373 */ 374 int mask = crc_rst_cpu | crc_rst_de | crc_rst_debug; 375 int num_cpus = get_num_cpus(); 376 int cpu; 377 378 debug("%s entry\n", __func__); 379 /* Hold CPUs 1 onwards in reset, and CPU 0 if asked */ 380 for (cpu = 1; cpu < num_cpus; cpu++) 381 reset_cmplx_set_enable(cpu, mask, 1); 382 reset_cmplx_set_enable(0, mask, reset); 383 384 /* Enable/Disable master CPU reset */ 385 reset_set_enable(PERIPH_ID_CPU, reset); 386 } 387 388 void clock_enable_coresight(int enable) 389 { 390 u32 rst, src = 2; 391 392 debug("%s entry\n", __func__); 393 clock_set_enable(PERIPH_ID_CORESIGHT, enable); 394 reset_set_enable(PERIPH_ID_CORESIGHT, !enable); 395 396 if (enable) { 397 /* 398 * Put CoreSight on PLLP_OUT0 and divide it down as per 399 * PLLP base frequency based on SoC type (T20/T30+). 400 * Clock divider request would setup CSITE clock as 144MHz 401 * for PLLP base 216MHz and 204MHz for PLLP base 408MHz 402 */ 403 src = CLK_DIVIDER(NVBL_PLLP_KHZ, CSITE_KHZ); 404 clock_ll_set_source_divisor(PERIPH_ID_CSI, 0, src); 405 406 /* Unlock the CPU CoreSight interfaces */ 407 rst = CORESIGHT_UNLOCK; 408 writel(rst, CSITE_CPU_DBG0_LAR); 409 writel(rst, CSITE_CPU_DBG1_LAR); 410 if (get_num_cpus() == 4) { 411 writel(rst, CSITE_CPU_DBG2_LAR); 412 writel(rst, CSITE_CPU_DBG3_LAR); 413 } 414 } 415 } 416 417 void halt_avp(void) 418 { 419 debug("%s entry\n", __func__); 420 421 for (;;) { 422 writel(HALT_COP_EVENT_JTAG | (FLOW_MODE_STOP << 29), 423 FLOW_CTLR_HALT_COP_EVENTS); 424 } 425 } 426