1 /* 2 * Copyright (c) 2013-2014, NVIDIA CORPORATION. All rights reserved. 3 * 4 * This program is free software; you can redistribute it and/or modify it 5 * under the terms and conditions of the GNU General Public License, 6 * version 2, as published by the Free Software Foundation. 7 * 8 * This program is distributed in the hope it will be useful, but WITHOUT 9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 11 * more details. 12 * 13 * You should have received a copy of the GNU General Public License 14 * along with this program. If not, see <http://www.gnu.org/licenses/>. 15 */ 16 17 /* Tegra cache routines */ 18 19 #include <common.h> 20 #include <asm/io.h> 21 #include <asm/arch-tegra/ap.h> 22 #include <asm/arch/gp_padctrl.h> 23 24 void config_cache(void) 25 { 26 u32 reg = 0; 27 28 /* enable SMP mode and FW for CPU0, by writing to Auxiliary Ctl reg */ 29 asm volatile( 30 "mrc p15, 0, r0, c1, c0, 1\n" 31 "orr r0, r0, #0x41\n" 32 "mcr p15, 0, r0, c1, c0, 1\n"); 33 34 /* Currently, only Tegra114+ needs this L2 cache change to boot Linux */ 35 if (tegra_get_chip() < CHIPID_TEGRA114) 36 return; 37 38 /* 39 * Systems with an architectural L2 cache must not use the PL310. 40 * Config L2CTLR here for a data RAM latency of 3 cycles. 41 */ 42 asm("mrc p15, 1, %0, c9, c0, 2" : : "r" (reg)); 43 reg &= ~7; 44 reg |= 2; 45 asm("mcr p15, 1, %0, c9, c0, 2" : : "r" (reg)); 46 } 47