1 /* 2 * (C) Copyright 2010,2011 3 * NVIDIA Corporation <www.nvidia.com> 4 * 5 * SPDX-License-Identifier: GPL-2.0+ 6 */ 7 8 #include <common.h> 9 #include <dm.h> 10 #include <errno.h> 11 #include <ns16550.h> 12 #include <linux/compiler.h> 13 #include <linux/sizes.h> 14 #include <asm/io.h> 15 #include <asm/arch/clock.h> 16 #ifdef CONFIG_LCD 17 #include <asm/arch/display.h> 18 #endif 19 #include <asm/arch/funcmux.h> 20 #include <asm/arch/pinmux.h> 21 #include <asm/arch/pmu.h> 22 #ifdef CONFIG_PWM_TEGRA 23 #include <asm/arch/pwm.h> 24 #endif 25 #include <asm/arch/tegra.h> 26 #include <asm/arch-tegra/ap.h> 27 #include <asm/arch-tegra/board.h> 28 #include <asm/arch-tegra/clk_rst.h> 29 #include <asm/arch-tegra/pmc.h> 30 #include <asm/arch-tegra/sys_proto.h> 31 #include <asm/arch-tegra/uart.h> 32 #include <asm/arch-tegra/warmboot.h> 33 #include <asm/arch-tegra/gpu.h> 34 #ifdef CONFIG_TEGRA_CLOCK_SCALING 35 #include <asm/arch/emc.h> 36 #endif 37 #include <asm/arch-tegra/usb.h> 38 #ifdef CONFIG_USB_EHCI_TEGRA 39 #include <usb.h> 40 #endif 41 #ifdef CONFIG_TEGRA_MMC 42 #include <asm/arch-tegra/tegra_mmc.h> 43 #include <asm/arch-tegra/mmc.h> 44 #endif 45 #include <asm/arch-tegra/xusb-padctl.h> 46 #include <power/as3722.h> 47 #include <i2c.h> 48 #include <spi.h> 49 #include "emc.h" 50 51 DECLARE_GLOBAL_DATA_PTR; 52 53 #ifdef CONFIG_SPL_BUILD 54 /* TODO(sjg@chromium.org): Remove once SPL supports device tree */ 55 U_BOOT_DEVICE(tegra_gpios) = { 56 "gpio_tegra" 57 }; 58 #endif 59 60 __weak void pinmux_init(void) {} 61 __weak void pin_mux_usb(void) {} 62 __weak void pin_mux_spi(void) {} 63 __weak void gpio_early_init_uart(void) {} 64 __weak void pin_mux_display(void) {} 65 __weak void start_cpu_fan(void) {} 66 67 #if defined(CONFIG_TEGRA_NAND) 68 __weak void pin_mux_nand(void) 69 { 70 funcmux_select(PERIPH_ID_NDFLASH, FUNCMUX_DEFAULT); 71 } 72 #endif 73 74 /* 75 * Routine: power_det_init 76 * Description: turn off power detects 77 */ 78 static void power_det_init(void) 79 { 80 #if defined(CONFIG_TEGRA20) 81 struct pmc_ctlr *const pmc = (struct pmc_ctlr *)NV_PA_PMC_BASE; 82 83 /* turn off power detects */ 84 writel(0, &pmc->pmc_pwr_det_latch); 85 writel(0, &pmc->pmc_pwr_det); 86 #endif 87 } 88 89 __weak int tegra_board_id(void) 90 { 91 return -1; 92 } 93 94 #ifdef CONFIG_DISPLAY_BOARDINFO 95 int checkboard(void) 96 { 97 int board_id = tegra_board_id(); 98 99 printf("Board: %s", CONFIG_TEGRA_BOARD_STRING); 100 if (board_id != -1) 101 printf(", ID: %d\n", board_id); 102 printf("\n"); 103 104 return 0; 105 } 106 #endif /* CONFIG_DISPLAY_BOARDINFO */ 107 108 __weak int tegra_lcd_pmic_init(int board_it) 109 { 110 return 0; 111 } 112 113 __weak int nvidia_board_init(void) 114 { 115 return 0; 116 } 117 118 /* 119 * Routine: board_init 120 * Description: Early hardware init. 121 */ 122 int board_init(void) 123 { 124 __maybe_unused int err; 125 __maybe_unused int board_id; 126 127 /* Do clocks and UART first so that printf() works */ 128 clock_init(); 129 clock_verify(); 130 131 tegra_gpu_config(); 132 133 #ifdef CONFIG_TEGRA_SPI 134 pin_mux_spi(); 135 #endif 136 137 #ifdef CONFIG_PWM_TEGRA 138 if (pwm_init(gd->fdt_blob)) 139 debug("%s: Failed to init pwm\n", __func__); 140 #endif 141 #ifdef CONFIG_LCD 142 pin_mux_display(); 143 tegra_lcd_check_next_stage(gd->fdt_blob, 0); 144 #endif 145 /* boot param addr */ 146 gd->bd->bi_boot_params = (NV_PA_SDRAM_BASE + 0x100); 147 148 power_det_init(); 149 150 #ifdef CONFIG_SYS_I2C_TEGRA 151 # ifdef CONFIG_TEGRA_PMU 152 if (pmu_set_nominal()) 153 debug("Failed to select nominal voltages\n"); 154 # ifdef CONFIG_TEGRA_CLOCK_SCALING 155 err = board_emc_init(); 156 if (err) 157 debug("Memory controller init failed: %d\n", err); 158 # endif 159 # endif /* CONFIG_TEGRA_PMU */ 160 #ifdef CONFIG_AS3722_POWER 161 err = as3722_init(NULL); 162 if (err && err != -ENODEV) 163 return err; 164 #endif 165 #endif /* CONFIG_SYS_I2C_TEGRA */ 166 167 #ifdef CONFIG_USB_EHCI_TEGRA 168 pin_mux_usb(); 169 #endif 170 171 #ifdef CONFIG_LCD 172 board_id = tegra_board_id(); 173 err = tegra_lcd_pmic_init(board_id); 174 if (err) 175 return err; 176 tegra_lcd_check_next_stage(gd->fdt_blob, 0); 177 #endif 178 179 #ifdef CONFIG_TEGRA_NAND 180 pin_mux_nand(); 181 #endif 182 183 tegra_xusb_padctl_init(gd->fdt_blob); 184 185 #ifdef CONFIG_TEGRA_LP0 186 /* save Sdram params to PMC 2, 4, and 24 for WB0 */ 187 warmboot_save_sdram_params(); 188 189 /* prepare the WB code to LP0 location */ 190 warmboot_prepare_code(TEGRA_LP0_ADDR, TEGRA_LP0_SIZE); 191 #endif 192 return nvidia_board_init(); 193 } 194 195 #ifdef CONFIG_BOARD_EARLY_INIT_F 196 static void __gpio_early_init(void) 197 { 198 } 199 200 void gpio_early_init(void) __attribute__((weak, alias("__gpio_early_init"))); 201 202 int board_early_init_f(void) 203 { 204 #if defined(CONFIG_TEGRA_DISCONNECT_UDC_ON_BOOT) 205 #define USBCMD_FS2 (1 << 15) 206 { 207 struct usb_ctlr *usbctlr = (struct usb_ctlr *)0x7d000000; 208 writel(USBCMD_FS2, &usbctlr->usb_cmd); 209 } 210 #endif 211 212 /* Do any special system timer/TSC setup */ 213 #if defined(CONFIG_TEGRA_SUPPORT_NON_SECURE) 214 if (!tegra_cpu_is_non_secure()) 215 #endif 216 arch_timer_init(); 217 218 pinmux_init(); 219 board_init_uart_f(); 220 221 /* Initialize periph GPIOs */ 222 gpio_early_init(); 223 gpio_early_init_uart(); 224 #ifdef CONFIG_LCD 225 tegra_lcd_early_init(gd->fdt_blob); 226 #endif 227 228 return 0; 229 } 230 #endif /* EARLY_INIT */ 231 232 int board_late_init(void) 233 { 234 #ifdef CONFIG_LCD 235 /* Make sure we finish initing the LCD */ 236 tegra_lcd_check_next_stage(gd->fdt_blob, 1); 237 #endif 238 #if defined(CONFIG_TEGRA_SUPPORT_NON_SECURE) 239 if (tegra_cpu_is_non_secure()) { 240 printf("CPU is in NS mode\n"); 241 setenv("cpu_ns_mode", "1"); 242 } else { 243 setenv("cpu_ns_mode", ""); 244 } 245 #endif 246 start_cpu_fan(); 247 248 return 0; 249 } 250 251 #if defined(CONFIG_TEGRA_MMC) 252 __weak void pin_mux_mmc(void) 253 { 254 } 255 256 /* this is a weak define that we are overriding */ 257 int board_mmc_init(bd_t *bd) 258 { 259 debug("%s called\n", __func__); 260 261 /* Enable muxes, etc. for SDMMC controllers */ 262 pin_mux_mmc(); 263 264 debug("%s: init MMC\n", __func__); 265 tegra_mmc_init(); 266 267 return 0; 268 } 269 270 void pad_init_mmc(struct mmc_host *host) 271 { 272 #if defined(CONFIG_TEGRA30) 273 enum periph_id id = host->mmc_id; 274 u32 val; 275 276 debug("%s: sdmmc address = %08x, id = %d\n", __func__, 277 (unsigned int)host->reg, id); 278 279 /* Set the pad drive strength for SDMMC1 or 3 only */ 280 if (id != PERIPH_ID_SDMMC1 && id != PERIPH_ID_SDMMC3) { 281 debug("%s: settings are only valid for SDMMC1/SDMMC3!\n", 282 __func__); 283 return; 284 } 285 286 val = readl(&host->reg->sdmemcmppadctl); 287 val &= 0xFFFFFFF0; 288 val |= MEMCOMP_PADCTRL_VREF; 289 writel(val, &host->reg->sdmemcmppadctl); 290 291 val = readl(&host->reg->autocalcfg); 292 val &= 0xFFFF0000; 293 val |= AUTO_CAL_PU_OFFSET | AUTO_CAL_PD_OFFSET | AUTO_CAL_ENABLED; 294 writel(val, &host->reg->autocalcfg); 295 #endif /* T30 */ 296 } 297 #endif /* MMC */ 298 299 /* 300 * In some SW environments, a memory carve-out exists to house a secure 301 * monitor, a trusted OS, and/or various statically allocated media buffers. 302 * 303 * This carveout exists at the highest possible address that is within a 304 * 32-bit physical address space. 305 * 306 * This function returns the total size of this carve-out. At present, the 307 * returned value is hard-coded for simplicity. In the future, it may be 308 * possible to determine the carve-out size: 309 * - By querying some run-time information source, such as: 310 * - A structure passed to U-Boot by earlier boot software. 311 * - SoC registers. 312 * - A call into the secure monitor. 313 * - In the per-board U-Boot configuration header, based on knowledge of the 314 * SW environment that U-Boot is being built for. 315 * 316 * For now, we support two configurations in U-Boot: 317 * - 32-bit ports without any form of carve-out. 318 * - 64 bit ports which are assumed to use a carve-out of a conservatively 319 * hard-coded size. 320 */ 321 static ulong carveout_size(void) 322 { 323 #ifdef CONFIG_ARM64 324 return SZ_512M; 325 #else 326 return 0; 327 #endif 328 } 329 330 /* 331 * Determine the amount of usable RAM below 4GiB, taking into account any 332 * carve-out that may be assigned. 333 */ 334 static ulong usable_ram_size_below_4g(void) 335 { 336 ulong total_size_below_4g; 337 ulong usable_size_below_4g; 338 339 /* 340 * The total size of RAM below 4GiB is the lesser address of: 341 * (a) 2GiB itself (RAM starts at 2GiB, and 4GiB - 2GiB == 2GiB). 342 * (b) The size RAM physically present in the system. 343 */ 344 if (gd->ram_size < SZ_2G) 345 total_size_below_4g = gd->ram_size; 346 else 347 total_size_below_4g = SZ_2G; 348 349 /* Calculate usable RAM by subtracting out any carve-out size */ 350 usable_size_below_4g = total_size_below_4g - carveout_size(); 351 352 return usable_size_below_4g; 353 } 354 355 /* 356 * Represent all available RAM in either one or two banks. 357 * 358 * The first bank describes any usable RAM below 4GiB. 359 * The second bank describes any RAM above 4GiB. 360 * 361 * This split is driven by the following requirements: 362 * - The NVIDIA L4T kernel requires separate entries in the DT /memory/reg 363 * property for memory below and above the 4GiB boundary. The layout of that 364 * DT property is directly driven by the entries in the U-Boot bank array. 365 * - The potential existence of a carve-out at the end of RAM below 4GiB can 366 * only be represented using multiple banks. 367 * 368 * Explicitly removing the carve-out RAM from the bank entries makes the RAM 369 * layout a bit more obvious, e.g. when running "bdinfo" at the U-Boot 370 * command-line. 371 * 372 * This does mean that the DT U-Boot passes to the Linux kernel will not 373 * include this RAM in /memory/reg at all. An alternative would be to include 374 * all RAM in the U-Boot banks (and hence DT), and add a /memreserve/ node 375 * into DT to stop the kernel from using the RAM. IIUC, I don't /think/ the 376 * Linux kernel will ever need to access any RAM in* the carve-out via a CPU 377 * mapping, so either way is acceptable. 378 * 379 * On 32-bit systems, we never define a bank for RAM above 4GiB, since the 380 * start address of that bank cannot be represented in the 32-bit .size 381 * field. 382 */ 383 void dram_init_banksize(void) 384 { 385 gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE; 386 gd->bd->bi_dram[0].size = usable_ram_size_below_4g(); 387 388 #ifdef CONFIG_PCI 389 gd->pci_ram_top = gd->bd->bi_dram[0].start + gd->bd->bi_dram[0].size; 390 #endif 391 392 #ifdef CONFIG_PHYS_64BIT 393 if (gd->ram_size > SZ_2G) { 394 gd->bd->bi_dram[1].start = 0x100000000; 395 gd->bd->bi_dram[1].size = gd->ram_size - SZ_2G; 396 } else 397 #endif 398 { 399 gd->bd->bi_dram[1].start = 0; 400 gd->bd->bi_dram[1].size = 0; 401 } 402 } 403 404 /* 405 * Most hardware on 64-bit Tegra is still restricted to DMA to the lower 406 * 32-bits of the physical address space. Cap the maximum usable RAM area 407 * at 4 GiB to avoid DMA buffers from being allocated beyond the 32-bit 408 * boundary that most devices can address. Also, don't let U-Boot use any 409 * carve-out, as mentioned above. 410 * 411 * This function is called before dram_init_banksize(), so we can't simply 412 * return gd->bd->bi_dram[1].start + gd->bd->bi_dram[1].size. 413 */ 414 ulong board_get_usable_ram_top(ulong total_size) 415 { 416 return CONFIG_SYS_SDRAM_BASE + usable_ram_size_below_4g(); 417 } 418 419 /* 420 * This function is called right before the kernel is booted. "blob" is the 421 * device tree that will be passed to the kernel. 422 */ 423 int ft_system_setup(void *blob, bd_t *bd) 424 { 425 const char *gpu_path = 426 #if defined(CONFIG_TEGRA124) || defined(CONFIG_TEGRA210) 427 "/gpu@0,57000000"; 428 #else 429 NULL; 430 #endif 431 432 /* Enable GPU node if GPU setup has been performed */ 433 if (gpu_path != NULL) 434 return tegra_gpu_enable_node(blob, gpu_path); 435 436 return 0; 437 } 438