1 /* 2 * (C) Copyright 2010,2011 3 * NVIDIA Corporation <www.nvidia.com> 4 * 5 * SPDX-License-Identifier: GPL-2.0+ 6 */ 7 8 #include <common.h> 9 #include <dm.h> 10 #include <errno.h> 11 #include <ns16550.h> 12 #include <linux/compiler.h> 13 #include <linux/sizes.h> 14 #include <asm/io.h> 15 #include <asm/arch/clock.h> 16 #include <asm/arch/funcmux.h> 17 #include <asm/arch/pinmux.h> 18 #include <asm/arch/pmu.h> 19 #include <asm/arch/tegra.h> 20 #include <asm/arch-tegra/ap.h> 21 #include <asm/arch-tegra/board.h> 22 #include <asm/arch-tegra/clk_rst.h> 23 #include <asm/arch-tegra/pmc.h> 24 #include <asm/arch-tegra/sys_proto.h> 25 #include <asm/arch-tegra/uart.h> 26 #include <asm/arch-tegra/warmboot.h> 27 #include <asm/arch-tegra/gpu.h> 28 #ifdef CONFIG_TEGRA_CLOCK_SCALING 29 #include <asm/arch/emc.h> 30 #endif 31 #include <asm/arch-tegra/usb.h> 32 #ifdef CONFIG_USB_EHCI_TEGRA 33 #include <usb.h> 34 #endif 35 #include <asm/arch-tegra/xusb-padctl.h> 36 #include <power/as3722.h> 37 #include <i2c.h> 38 #include <spi.h> 39 #include "emc.h" 40 41 DECLARE_GLOBAL_DATA_PTR; 42 43 #ifdef CONFIG_SPL_BUILD 44 /* TODO(sjg@chromium.org): Remove once SPL supports device tree */ 45 U_BOOT_DEVICE(tegra_gpios) = { 46 "gpio_tegra" 47 }; 48 #endif 49 50 __weak void pinmux_init(void) {} 51 __weak void pin_mux_usb(void) {} 52 __weak void pin_mux_spi(void) {} 53 __weak void pin_mux_mmc(void) {} 54 __weak void gpio_early_init_uart(void) {} 55 __weak void pin_mux_display(void) {} 56 __weak void start_cpu_fan(void) {} 57 58 #if defined(CONFIG_TEGRA_NAND) 59 __weak void pin_mux_nand(void) 60 { 61 funcmux_select(PERIPH_ID_NDFLASH, FUNCMUX_DEFAULT); 62 } 63 #endif 64 65 /* 66 * Routine: power_det_init 67 * Description: turn off power detects 68 */ 69 static void power_det_init(void) 70 { 71 #if defined(CONFIG_TEGRA20) 72 struct pmc_ctlr *const pmc = (struct pmc_ctlr *)NV_PA_PMC_BASE; 73 74 /* turn off power detects */ 75 writel(0, &pmc->pmc_pwr_det_latch); 76 writel(0, &pmc->pmc_pwr_det); 77 #endif 78 } 79 80 __weak int tegra_board_id(void) 81 { 82 return -1; 83 } 84 85 #ifdef CONFIG_DISPLAY_BOARDINFO 86 int checkboard(void) 87 { 88 int board_id = tegra_board_id(); 89 90 printf("Board: %s", CONFIG_TEGRA_BOARD_STRING); 91 if (board_id != -1) 92 printf(", ID: %d\n", board_id); 93 printf("\n"); 94 95 return 0; 96 } 97 #endif /* CONFIG_DISPLAY_BOARDINFO */ 98 99 __weak int tegra_lcd_pmic_init(int board_it) 100 { 101 return 0; 102 } 103 104 __weak int nvidia_board_init(void) 105 { 106 return 0; 107 } 108 109 /* 110 * Routine: board_init 111 * Description: Early hardware init. 112 */ 113 int board_init(void) 114 { 115 __maybe_unused int err; 116 __maybe_unused int board_id; 117 118 /* Do clocks and UART first so that printf() works */ 119 clock_init(); 120 clock_verify(); 121 122 tegra_gpu_config(); 123 124 #ifdef CONFIG_TEGRA_SPI 125 pin_mux_spi(); 126 #endif 127 128 #ifdef CONFIG_MMC_SDHCI_TEGRA 129 pin_mux_mmc(); 130 #endif 131 132 /* Init is handled automatically in the driver-model case */ 133 #if defined(CONFIG_DM_VIDEO) 134 pin_mux_display(); 135 #endif 136 /* boot param addr */ 137 gd->bd->bi_boot_params = (NV_PA_SDRAM_BASE + 0x100); 138 139 power_det_init(); 140 141 #ifdef CONFIG_SYS_I2C_TEGRA 142 # ifdef CONFIG_TEGRA_PMU 143 if (pmu_set_nominal()) 144 debug("Failed to select nominal voltages\n"); 145 # ifdef CONFIG_TEGRA_CLOCK_SCALING 146 err = board_emc_init(); 147 if (err) 148 debug("Memory controller init failed: %d\n", err); 149 # endif 150 # endif /* CONFIG_TEGRA_PMU */ 151 #ifdef CONFIG_PMIC_AS3722 152 err = as3722_init(NULL); 153 if (err && err != -ENODEV) 154 return err; 155 #endif 156 #endif /* CONFIG_SYS_I2C_TEGRA */ 157 158 #ifdef CONFIG_USB_EHCI_TEGRA 159 pin_mux_usb(); 160 #endif 161 162 #if defined(CONFIG_DM_VIDEO) 163 board_id = tegra_board_id(); 164 err = tegra_lcd_pmic_init(board_id); 165 if (err) 166 return err; 167 #endif 168 169 #ifdef CONFIG_TEGRA_NAND 170 pin_mux_nand(); 171 #endif 172 173 tegra_xusb_padctl_init(gd->fdt_blob); 174 175 #ifdef CONFIG_TEGRA_LP0 176 /* save Sdram params to PMC 2, 4, and 24 for WB0 */ 177 warmboot_save_sdram_params(); 178 179 /* prepare the WB code to LP0 location */ 180 warmboot_prepare_code(TEGRA_LP0_ADDR, TEGRA_LP0_SIZE); 181 #endif 182 return nvidia_board_init(); 183 } 184 185 #ifdef CONFIG_BOARD_EARLY_INIT_F 186 static void __gpio_early_init(void) 187 { 188 } 189 190 void gpio_early_init(void) __attribute__((weak, alias("__gpio_early_init"))); 191 192 int board_early_init_f(void) 193 { 194 if (!clock_early_init_done()) 195 clock_early_init(); 196 197 #if defined(CONFIG_TEGRA_DISCONNECT_UDC_ON_BOOT) 198 #define USBCMD_FS2 (1 << 15) 199 { 200 struct usb_ctlr *usbctlr = (struct usb_ctlr *)0x7d000000; 201 writel(USBCMD_FS2, &usbctlr->usb_cmd); 202 } 203 #endif 204 205 /* Do any special system timer/TSC setup */ 206 #if defined(CONFIG_TEGRA_SUPPORT_NON_SECURE) 207 if (!tegra_cpu_is_non_secure()) 208 #endif 209 arch_timer_init(); 210 211 pinmux_init(); 212 board_init_uart_f(); 213 214 /* Initialize periph GPIOs */ 215 gpio_early_init(); 216 gpio_early_init_uart(); 217 218 return 0; 219 } 220 #endif /* EARLY_INIT */ 221 222 int board_late_init(void) 223 { 224 #if defined(CONFIG_TEGRA_SUPPORT_NON_SECURE) 225 if (tegra_cpu_is_non_secure()) { 226 printf("CPU is in NS mode\n"); 227 setenv("cpu_ns_mode", "1"); 228 } else { 229 setenv("cpu_ns_mode", ""); 230 } 231 #endif 232 start_cpu_fan(); 233 234 return 0; 235 } 236 237 /* 238 * In some SW environments, a memory carve-out exists to house a secure 239 * monitor, a trusted OS, and/or various statically allocated media buffers. 240 * 241 * This carveout exists at the highest possible address that is within a 242 * 32-bit physical address space. 243 * 244 * This function returns the total size of this carve-out. At present, the 245 * returned value is hard-coded for simplicity. In the future, it may be 246 * possible to determine the carve-out size: 247 * - By querying some run-time information source, such as: 248 * - A structure passed to U-Boot by earlier boot software. 249 * - SoC registers. 250 * - A call into the secure monitor. 251 * - In the per-board U-Boot configuration header, based on knowledge of the 252 * SW environment that U-Boot is being built for. 253 * 254 * For now, we support two configurations in U-Boot: 255 * - 32-bit ports without any form of carve-out. 256 * - 64 bit ports which are assumed to use a carve-out of a conservatively 257 * hard-coded size. 258 */ 259 static ulong carveout_size(void) 260 { 261 #ifdef CONFIG_ARM64 262 return SZ_512M; 263 #else 264 return 0; 265 #endif 266 } 267 268 /* 269 * Determine the amount of usable RAM below 4GiB, taking into account any 270 * carve-out that may be assigned. 271 */ 272 static ulong usable_ram_size_below_4g(void) 273 { 274 ulong total_size_below_4g; 275 ulong usable_size_below_4g; 276 277 /* 278 * The total size of RAM below 4GiB is the lesser address of: 279 * (a) 2GiB itself (RAM starts at 2GiB, and 4GiB - 2GiB == 2GiB). 280 * (b) The size RAM physically present in the system. 281 */ 282 if (gd->ram_size < SZ_2G) 283 total_size_below_4g = gd->ram_size; 284 else 285 total_size_below_4g = SZ_2G; 286 287 /* Calculate usable RAM by subtracting out any carve-out size */ 288 usable_size_below_4g = total_size_below_4g - carveout_size(); 289 290 return usable_size_below_4g; 291 } 292 293 /* 294 * Represent all available RAM in either one or two banks. 295 * 296 * The first bank describes any usable RAM below 4GiB. 297 * The second bank describes any RAM above 4GiB. 298 * 299 * This split is driven by the following requirements: 300 * - The NVIDIA L4T kernel requires separate entries in the DT /memory/reg 301 * property for memory below and above the 4GiB boundary. The layout of that 302 * DT property is directly driven by the entries in the U-Boot bank array. 303 * - The potential existence of a carve-out at the end of RAM below 4GiB can 304 * only be represented using multiple banks. 305 * 306 * Explicitly removing the carve-out RAM from the bank entries makes the RAM 307 * layout a bit more obvious, e.g. when running "bdinfo" at the U-Boot 308 * command-line. 309 * 310 * This does mean that the DT U-Boot passes to the Linux kernel will not 311 * include this RAM in /memory/reg at all. An alternative would be to include 312 * all RAM in the U-Boot banks (and hence DT), and add a /memreserve/ node 313 * into DT to stop the kernel from using the RAM. IIUC, I don't /think/ the 314 * Linux kernel will ever need to access any RAM in* the carve-out via a CPU 315 * mapping, so either way is acceptable. 316 * 317 * On 32-bit systems, we never define a bank for RAM above 4GiB, since the 318 * start address of that bank cannot be represented in the 32-bit .size 319 * field. 320 */ 321 int dram_init_banksize(void) 322 { 323 gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE; 324 gd->bd->bi_dram[0].size = usable_ram_size_below_4g(); 325 326 #ifdef CONFIG_PCI 327 gd->pci_ram_top = gd->bd->bi_dram[0].start + gd->bd->bi_dram[0].size; 328 #endif 329 330 #ifdef CONFIG_PHYS_64BIT 331 if (gd->ram_size > SZ_2G) { 332 gd->bd->bi_dram[1].start = 0x100000000; 333 gd->bd->bi_dram[1].size = gd->ram_size - SZ_2G; 334 } else 335 #endif 336 { 337 gd->bd->bi_dram[1].start = 0; 338 gd->bd->bi_dram[1].size = 0; 339 } 340 341 return 0; 342 } 343 344 /* 345 * Most hardware on 64-bit Tegra is still restricted to DMA to the lower 346 * 32-bits of the physical address space. Cap the maximum usable RAM area 347 * at 4 GiB to avoid DMA buffers from being allocated beyond the 32-bit 348 * boundary that most devices can address. Also, don't let U-Boot use any 349 * carve-out, as mentioned above. 350 * 351 * This function is called before dram_init_banksize(), so we can't simply 352 * return gd->bd->bi_dram[1].start + gd->bd->bi_dram[1].size. 353 */ 354 ulong board_get_usable_ram_top(ulong total_size) 355 { 356 return CONFIG_SYS_SDRAM_BASE + usable_ram_size_below_4g(); 357 } 358