1 /* 2 * (C) Copyright 2010,2011 3 * NVIDIA Corporation <www.nvidia.com> 4 * 5 * SPDX-License-Identifier: GPL-2.0+ 6 */ 7 8 #include <common.h> 9 #include <dm.h> 10 #include <errno.h> 11 #include <ns16550.h> 12 #include <linux/compiler.h> 13 #include <asm/io.h> 14 #include <asm/arch/clock.h> 15 #ifdef CONFIG_LCD 16 #include <asm/arch/display.h> 17 #endif 18 #include <asm/arch/funcmux.h> 19 #include <asm/arch/pinmux.h> 20 #include <asm/arch/pmu.h> 21 #ifdef CONFIG_PWM_TEGRA 22 #include <asm/arch/pwm.h> 23 #endif 24 #include <asm/arch/tegra.h> 25 #include <asm/arch-tegra/ap.h> 26 #include <asm/arch-tegra/board.h> 27 #include <asm/arch-tegra/clk_rst.h> 28 #include <asm/arch-tegra/pmc.h> 29 #include <asm/arch-tegra/sys_proto.h> 30 #include <asm/arch-tegra/uart.h> 31 #include <asm/arch-tegra/warmboot.h> 32 #ifdef CONFIG_TEGRA_CLOCK_SCALING 33 #include <asm/arch/emc.h> 34 #endif 35 #ifdef CONFIG_USB_EHCI_TEGRA 36 #include <asm/arch-tegra/usb.h> 37 #include <usb.h> 38 #endif 39 #ifdef CONFIG_TEGRA_MMC 40 #include <asm/arch-tegra/tegra_mmc.h> 41 #include <asm/arch-tegra/mmc.h> 42 #endif 43 #include <asm/arch-tegra/xusb-padctl.h> 44 #include <power/as3722.h> 45 #include <i2c.h> 46 #include <spi.h> 47 #include "emc.h" 48 49 DECLARE_GLOBAL_DATA_PTR; 50 51 #ifdef CONFIG_SPL_BUILD 52 /* TODO(sjg@chromium.org): Remove once SPL supports device tree */ 53 U_BOOT_DEVICE(tegra_gpios) = { 54 "gpio_tegra" 55 }; 56 #endif 57 58 __weak void pinmux_init(void) {} 59 __weak void pin_mux_usb(void) {} 60 __weak void pin_mux_spi(void) {} 61 __weak void gpio_early_init_uart(void) {} 62 __weak void pin_mux_display(void) {} 63 64 #if defined(CONFIG_TEGRA_NAND) 65 __weak void pin_mux_nand(void) 66 { 67 funcmux_select(PERIPH_ID_NDFLASH, FUNCMUX_DEFAULT); 68 } 69 #endif 70 71 /* 72 * Routine: power_det_init 73 * Description: turn off power detects 74 */ 75 static void power_det_init(void) 76 { 77 #if defined(CONFIG_TEGRA20) 78 struct pmc_ctlr *const pmc = (struct pmc_ctlr *)NV_PA_PMC_BASE; 79 80 /* turn off power detects */ 81 writel(0, &pmc->pmc_pwr_det_latch); 82 writel(0, &pmc->pmc_pwr_det); 83 #endif 84 } 85 86 __weak int tegra_board_id(void) 87 { 88 return -1; 89 } 90 91 #ifdef CONFIG_DISPLAY_BOARDINFO 92 int checkboard(void) 93 { 94 int board_id = tegra_board_id(); 95 96 printf("Board: %s", CONFIG_TEGRA_BOARD_STRING); 97 if (board_id != -1) 98 printf(", ID: %d\n", board_id); 99 printf("\n"); 100 101 return 0; 102 } 103 #endif /* CONFIG_DISPLAY_BOARDINFO */ 104 105 __weak int tegra_lcd_pmic_init(int board_it) 106 { 107 return 0; 108 } 109 110 __weak int nvidia_board_init(void) 111 { 112 return 0; 113 } 114 115 /* 116 * Routine: board_init 117 * Description: Early hardware init. 118 */ 119 int board_init(void) 120 { 121 __maybe_unused int err; 122 __maybe_unused int board_id; 123 124 /* Do clocks and UART first so that printf() works */ 125 clock_init(); 126 clock_verify(); 127 128 #ifdef CONFIG_TEGRA_SPI 129 pin_mux_spi(); 130 #endif 131 132 #ifdef CONFIG_PWM_TEGRA 133 if (pwm_init(gd->fdt_blob)) 134 debug("%s: Failed to init pwm\n", __func__); 135 #endif 136 #ifdef CONFIG_LCD 137 pin_mux_display(); 138 tegra_lcd_check_next_stage(gd->fdt_blob, 0); 139 #endif 140 /* boot param addr */ 141 gd->bd->bi_boot_params = (NV_PA_SDRAM_BASE + 0x100); 142 143 power_det_init(); 144 145 #ifdef CONFIG_SYS_I2C_TEGRA 146 # ifdef CONFIG_TEGRA_PMU 147 if (pmu_set_nominal()) 148 debug("Failed to select nominal voltages\n"); 149 # ifdef CONFIG_TEGRA_CLOCK_SCALING 150 err = board_emc_init(); 151 if (err) 152 debug("Memory controller init failed: %d\n", err); 153 # endif 154 # endif /* CONFIG_TEGRA_PMU */ 155 #ifdef CONFIG_AS3722_POWER 156 err = as3722_init(NULL); 157 if (err && err != -ENODEV) 158 return err; 159 #endif 160 #endif /* CONFIG_SYS_I2C_TEGRA */ 161 162 #ifdef CONFIG_USB_EHCI_TEGRA 163 pin_mux_usb(); 164 #endif 165 166 #ifdef CONFIG_LCD 167 board_id = tegra_board_id(); 168 err = tegra_lcd_pmic_init(board_id); 169 if (err) 170 return err; 171 tegra_lcd_check_next_stage(gd->fdt_blob, 0); 172 #endif 173 174 #ifdef CONFIG_TEGRA_NAND 175 pin_mux_nand(); 176 #endif 177 178 tegra_xusb_padctl_init(gd->fdt_blob); 179 180 #ifdef CONFIG_TEGRA_LP0 181 /* save Sdram params to PMC 2, 4, and 24 for WB0 */ 182 warmboot_save_sdram_params(); 183 184 /* prepare the WB code to LP0 location */ 185 warmboot_prepare_code(TEGRA_LP0_ADDR, TEGRA_LP0_SIZE); 186 #endif 187 return nvidia_board_init(); 188 } 189 190 #ifdef CONFIG_BOARD_EARLY_INIT_F 191 static void __gpio_early_init(void) 192 { 193 } 194 195 void gpio_early_init(void) __attribute__((weak, alias("__gpio_early_init"))); 196 197 int board_early_init_f(void) 198 { 199 /* Do any special system timer/TSC setup */ 200 #if defined(CONFIG_TEGRA_SUPPORT_NON_SECURE) 201 if (!tegra_cpu_is_non_secure()) 202 #endif 203 arch_timer_init(); 204 205 pinmux_init(); 206 board_init_uart_f(); 207 208 /* Initialize periph GPIOs */ 209 gpio_early_init(); 210 gpio_early_init_uart(); 211 #ifdef CONFIG_LCD 212 tegra_lcd_early_init(gd->fdt_blob); 213 #endif 214 215 return 0; 216 } 217 #endif /* EARLY_INIT */ 218 219 int board_late_init(void) 220 { 221 #ifdef CONFIG_LCD 222 /* Make sure we finish initing the LCD */ 223 tegra_lcd_check_next_stage(gd->fdt_blob, 1); 224 #endif 225 #if defined(CONFIG_TEGRA_SUPPORT_NON_SECURE) 226 if (tegra_cpu_is_non_secure()) { 227 printf("CPU is in NS mode\n"); 228 setenv("cpu_ns_mode", "1"); 229 } else { 230 setenv("cpu_ns_mode", ""); 231 } 232 #endif 233 return 0; 234 } 235 236 #if defined(CONFIG_TEGRA_MMC) 237 __weak void pin_mux_mmc(void) 238 { 239 } 240 241 /* this is a weak define that we are overriding */ 242 int board_mmc_init(bd_t *bd) 243 { 244 debug("%s called\n", __func__); 245 246 /* Enable muxes, etc. for SDMMC controllers */ 247 pin_mux_mmc(); 248 249 debug("%s: init MMC\n", __func__); 250 tegra_mmc_init(); 251 252 return 0; 253 } 254 255 void pad_init_mmc(struct mmc_host *host) 256 { 257 #if defined(CONFIG_TEGRA30) 258 enum periph_id id = host->mmc_id; 259 u32 val; 260 261 debug("%s: sdmmc address = %08x, id = %d\n", __func__, 262 (unsigned int)host->reg, id); 263 264 /* Set the pad drive strength for SDMMC1 or 3 only */ 265 if (id != PERIPH_ID_SDMMC1 && id != PERIPH_ID_SDMMC3) { 266 debug("%s: settings are only valid for SDMMC1/SDMMC3!\n", 267 __func__); 268 return; 269 } 270 271 val = readl(&host->reg->sdmemcmppadctl); 272 val &= 0xFFFFFFF0; 273 val |= MEMCOMP_PADCTRL_VREF; 274 writel(val, &host->reg->sdmemcmppadctl); 275 276 val = readl(&host->reg->autocalcfg); 277 val &= 0xFFFF0000; 278 val |= AUTO_CAL_PU_OFFSET | AUTO_CAL_PD_OFFSET | AUTO_CAL_ENABLED; 279 writel(val, &host->reg->autocalcfg); 280 #endif /* T30 */ 281 } 282 #endif /* MMC */ 283 284 #ifdef CONFIG_ARM64 285 /* 286 * Most hardware on 64-bit Tegra is still restricted to DMA to the lower 287 * 32-bits of the physical address space. Cap the maximum usable RAM area 288 * at 4 GiB to avoid DMA buffers from being allocated beyond the 32-bit 289 * boundary that most devices can address. 290 */ 291 ulong board_get_usable_ram_top(ulong total_size) 292 { 293 if (gd->ram_top > 0x100000000) 294 return 0x100000000; 295 296 return gd->ram_top; 297 } 298 #endif 299