1 /* 2 * (C) Copyright 2010,2011 3 * NVIDIA Corporation <www.nvidia.com> 4 * 5 * SPDX-License-Identifier: GPL-2.0+ 6 */ 7 8 #include <common.h> 9 #include <dm.h> 10 #include <errno.h> 11 #include <ns16550.h> 12 #include <linux/compiler.h> 13 #include <asm/io.h> 14 #include <asm/arch/clock.h> 15 #ifdef CONFIG_LCD 16 #include <asm/arch/display.h> 17 #endif 18 #include <asm/arch/funcmux.h> 19 #include <asm/arch/pinmux.h> 20 #include <asm/arch/pmu.h> 21 #ifdef CONFIG_PWM_TEGRA 22 #include <asm/arch/pwm.h> 23 #endif 24 #include <asm/arch/tegra.h> 25 #include <asm/arch-tegra/ap.h> 26 #include <asm/arch-tegra/board.h> 27 #include <asm/arch-tegra/clk_rst.h> 28 #include <asm/arch-tegra/pmc.h> 29 #include <asm/arch-tegra/sys_proto.h> 30 #include <asm/arch-tegra/uart.h> 31 #include <asm/arch-tegra/warmboot.h> 32 #ifdef CONFIG_TEGRA_CLOCK_SCALING 33 #include <asm/arch/emc.h> 34 #endif 35 #ifdef CONFIG_USB_EHCI_TEGRA 36 #include <asm/arch-tegra/usb.h> 37 #include <usb.h> 38 #endif 39 #ifdef CONFIG_TEGRA_MMC 40 #include <asm/arch-tegra/tegra_mmc.h> 41 #include <asm/arch-tegra/mmc.h> 42 #endif 43 #include <asm/arch-tegra/xusb-padctl.h> 44 #include <power/as3722.h> 45 #include <i2c.h> 46 #include <spi.h> 47 #include "emc.h" 48 49 DECLARE_GLOBAL_DATA_PTR; 50 51 #ifdef CONFIG_SPL_BUILD 52 /* TODO(sjg@chromium.org): Remove once SPL supports device tree */ 53 U_BOOT_DEVICE(tegra_gpios) = { 54 "gpio_tegra" 55 }; 56 #endif 57 58 __weak void pinmux_init(void) {} 59 __weak void pin_mux_usb(void) {} 60 __weak void pin_mux_spi(void) {} 61 __weak void gpio_early_init_uart(void) {} 62 __weak void pin_mux_display(void) {} 63 64 #if defined(CONFIG_TEGRA_NAND) 65 __weak void pin_mux_nand(void) 66 { 67 funcmux_select(PERIPH_ID_NDFLASH, FUNCMUX_DEFAULT); 68 } 69 #endif 70 71 /* 72 * Routine: power_det_init 73 * Description: turn off power detects 74 */ 75 static void power_det_init(void) 76 { 77 #if defined(CONFIG_TEGRA20) 78 struct pmc_ctlr *const pmc = (struct pmc_ctlr *)NV_PA_PMC_BASE; 79 80 /* turn off power detects */ 81 writel(0, &pmc->pmc_pwr_det_latch); 82 writel(0, &pmc->pmc_pwr_det); 83 #endif 84 } 85 86 __weak int tegra_board_id(void) 87 { 88 return -1; 89 } 90 91 #ifdef CONFIG_DISPLAY_BOARDINFO 92 int checkboard(void) 93 { 94 int board_id = tegra_board_id(); 95 96 printf("Board: %s", CONFIG_TEGRA_BOARD_STRING); 97 if (board_id != -1) 98 printf(", ID: %d\n", board_id); 99 printf("\n"); 100 101 return 0; 102 } 103 #endif /* CONFIG_DISPLAY_BOARDINFO */ 104 105 __weak int tegra_lcd_pmic_init(int board_it) 106 { 107 return 0; 108 } 109 110 /* 111 * Routine: board_init 112 * Description: Early hardware init. 113 */ 114 int board_init(void) 115 { 116 __maybe_unused int err; 117 __maybe_unused int board_id; 118 119 /* Do clocks and UART first so that printf() works */ 120 clock_init(); 121 clock_verify(); 122 123 #ifdef CONFIG_TEGRA_SPI 124 pin_mux_spi(); 125 #endif 126 127 #ifdef CONFIG_PWM_TEGRA 128 if (pwm_init(gd->fdt_blob)) 129 debug("%s: Failed to init pwm\n", __func__); 130 #endif 131 #ifdef CONFIG_LCD 132 pin_mux_display(); 133 tegra_lcd_check_next_stage(gd->fdt_blob, 0); 134 #endif 135 /* boot param addr */ 136 gd->bd->bi_boot_params = (NV_PA_SDRAM_BASE + 0x100); 137 138 power_det_init(); 139 140 #ifdef CONFIG_SYS_I2C_TEGRA 141 # ifdef CONFIG_TEGRA_PMU 142 if (pmu_set_nominal()) 143 debug("Failed to select nominal voltages\n"); 144 # ifdef CONFIG_TEGRA_CLOCK_SCALING 145 err = board_emc_init(); 146 if (err) 147 debug("Memory controller init failed: %d\n", err); 148 # endif 149 # endif /* CONFIG_TEGRA_PMU */ 150 #ifdef CONFIG_AS3722_POWER 151 err = as3722_init(NULL); 152 if (err && err != -ENODEV) 153 return err; 154 #endif 155 #endif /* CONFIG_SYS_I2C_TEGRA */ 156 157 #ifdef CONFIG_USB_EHCI_TEGRA 158 pin_mux_usb(); 159 usb_process_devicetree(gd->fdt_blob); 160 #endif 161 162 #ifdef CONFIG_LCD 163 board_id = tegra_board_id(); 164 err = tegra_lcd_pmic_init(board_id); 165 if (err) 166 return err; 167 tegra_lcd_check_next_stage(gd->fdt_blob, 0); 168 #endif 169 170 #ifdef CONFIG_TEGRA_NAND 171 pin_mux_nand(); 172 #endif 173 174 tegra_xusb_padctl_init(gd->fdt_blob); 175 176 #ifdef CONFIG_TEGRA_LP0 177 /* save Sdram params to PMC 2, 4, and 24 for WB0 */ 178 warmboot_save_sdram_params(); 179 180 /* prepare the WB code to LP0 location */ 181 warmboot_prepare_code(TEGRA_LP0_ADDR, TEGRA_LP0_SIZE); 182 #endif 183 184 return 0; 185 } 186 187 #ifdef CONFIG_BOARD_EARLY_INIT_F 188 static void __gpio_early_init(void) 189 { 190 } 191 192 void gpio_early_init(void) __attribute__((weak, alias("__gpio_early_init"))); 193 194 int board_early_init_f(void) 195 { 196 pinmux_init(); 197 board_init_uart_f(); 198 199 /* Initialize periph GPIOs */ 200 gpio_early_init(); 201 gpio_early_init_uart(); 202 #ifdef CONFIG_LCD 203 tegra_lcd_early_init(gd->fdt_blob); 204 #endif 205 206 return 0; 207 } 208 #endif /* EARLY_INIT */ 209 210 int board_late_init(void) 211 { 212 #ifdef CONFIG_LCD 213 /* Make sure we finish initing the LCD */ 214 tegra_lcd_check_next_stage(gd->fdt_blob, 1); 215 #endif 216 #if defined(CONFIG_TEGRA_SUPPORT_NON_SECURE) 217 if (tegra_cpu_is_non_secure()) { 218 printf("CPU is in NS mode\n"); 219 setenv("cpu_ns_mode", "1"); 220 } else { 221 setenv("cpu_ns_mode", ""); 222 } 223 #endif 224 return 0; 225 } 226 227 #if defined(CONFIG_TEGRA_MMC) 228 __weak void pin_mux_mmc(void) 229 { 230 } 231 232 /* this is a weak define that we are overriding */ 233 int board_mmc_init(bd_t *bd) 234 { 235 debug("%s called\n", __func__); 236 237 /* Enable muxes, etc. for SDMMC controllers */ 238 pin_mux_mmc(); 239 240 debug("%s: init MMC\n", __func__); 241 tegra_mmc_init(); 242 243 return 0; 244 } 245 246 void pad_init_mmc(struct mmc_host *host) 247 { 248 #if defined(CONFIG_TEGRA30) 249 enum periph_id id = host->mmc_id; 250 u32 val; 251 252 debug("%s: sdmmc address = %08x, id = %d\n", __func__, 253 (unsigned int)host->reg, id); 254 255 /* Set the pad drive strength for SDMMC1 or 3 only */ 256 if (id != PERIPH_ID_SDMMC1 && id != PERIPH_ID_SDMMC3) { 257 debug("%s: settings are only valid for SDMMC1/SDMMC3!\n", 258 __func__); 259 return; 260 } 261 262 val = readl(&host->reg->sdmemcmppadctl); 263 val &= 0xFFFFFFF0; 264 val |= MEMCOMP_PADCTRL_VREF; 265 writel(val, &host->reg->sdmemcmppadctl); 266 267 val = readl(&host->reg->autocalcfg); 268 val &= 0xFFFF0000; 269 val |= AUTO_CAL_PU_OFFSET | AUTO_CAL_PD_OFFSET | AUTO_CAL_ENABLED; 270 writel(val, &host->reg->autocalcfg); 271 #endif /* T30 */ 272 } 273 #endif /* MMC */ 274