1 /* 2 * (C) Copyright 2010,2011 3 * NVIDIA Corporation <www.nvidia.com> 4 * 5 * SPDX-License-Identifier: GPL-2.0+ 6 */ 7 8 #include <common.h> 9 #include <dm.h> 10 #include <errno.h> 11 #include <ns16550.h> 12 #include <linux/compiler.h> 13 #include <linux/sizes.h> 14 #include <asm/io.h> 15 #include <asm/arch/clock.h> 16 #ifdef CONFIG_LCD 17 #include <asm/arch/display.h> 18 #endif 19 #include <asm/arch/funcmux.h> 20 #include <asm/arch/pinmux.h> 21 #include <asm/arch/pmu.h> 22 #ifdef CONFIG_PWM_TEGRA 23 #include <asm/arch/pwm.h> 24 #endif 25 #include <asm/arch/tegra.h> 26 #include <asm/arch-tegra/ap.h> 27 #include <asm/arch-tegra/board.h> 28 #include <asm/arch-tegra/clk_rst.h> 29 #include <asm/arch-tegra/pmc.h> 30 #include <asm/arch-tegra/sys_proto.h> 31 #include <asm/arch-tegra/uart.h> 32 #include <asm/arch-tegra/warmboot.h> 33 #include <asm/arch-tegra/gpu.h> 34 #ifdef CONFIG_TEGRA_CLOCK_SCALING 35 #include <asm/arch/emc.h> 36 #endif 37 #ifdef CONFIG_USB_EHCI_TEGRA 38 #include <asm/arch-tegra/usb.h> 39 #include <usb.h> 40 #endif 41 #ifdef CONFIG_TEGRA_MMC 42 #include <asm/arch-tegra/tegra_mmc.h> 43 #include <asm/arch-tegra/mmc.h> 44 #endif 45 #include <asm/arch-tegra/xusb-padctl.h> 46 #include <power/as3722.h> 47 #include <i2c.h> 48 #include <spi.h> 49 #include "emc.h" 50 51 DECLARE_GLOBAL_DATA_PTR; 52 53 #ifdef CONFIG_SPL_BUILD 54 /* TODO(sjg@chromium.org): Remove once SPL supports device tree */ 55 U_BOOT_DEVICE(tegra_gpios) = { 56 "gpio_tegra" 57 }; 58 #endif 59 60 __weak void pinmux_init(void) {} 61 __weak void pin_mux_usb(void) {} 62 __weak void pin_mux_spi(void) {} 63 __weak void gpio_early_init_uart(void) {} 64 __weak void pin_mux_display(void) {} 65 __weak void start_cpu_fan(void) {} 66 67 #if defined(CONFIG_TEGRA_NAND) 68 __weak void pin_mux_nand(void) 69 { 70 funcmux_select(PERIPH_ID_NDFLASH, FUNCMUX_DEFAULT); 71 } 72 #endif 73 74 /* 75 * Routine: power_det_init 76 * Description: turn off power detects 77 */ 78 static void power_det_init(void) 79 { 80 #if defined(CONFIG_TEGRA20) 81 struct pmc_ctlr *const pmc = (struct pmc_ctlr *)NV_PA_PMC_BASE; 82 83 /* turn off power detects */ 84 writel(0, &pmc->pmc_pwr_det_latch); 85 writel(0, &pmc->pmc_pwr_det); 86 #endif 87 } 88 89 __weak int tegra_board_id(void) 90 { 91 return -1; 92 } 93 94 #ifdef CONFIG_DISPLAY_BOARDINFO 95 int checkboard(void) 96 { 97 int board_id = tegra_board_id(); 98 99 printf("Board: %s", CONFIG_TEGRA_BOARD_STRING); 100 if (board_id != -1) 101 printf(", ID: %d\n", board_id); 102 printf("\n"); 103 104 return 0; 105 } 106 #endif /* CONFIG_DISPLAY_BOARDINFO */ 107 108 __weak int tegra_lcd_pmic_init(int board_it) 109 { 110 return 0; 111 } 112 113 __weak int nvidia_board_init(void) 114 { 115 return 0; 116 } 117 118 /* 119 * Routine: board_init 120 * Description: Early hardware init. 121 */ 122 int board_init(void) 123 { 124 __maybe_unused int err; 125 __maybe_unused int board_id; 126 127 /* Do clocks and UART first so that printf() works */ 128 clock_init(); 129 clock_verify(); 130 131 tegra_gpu_config(); 132 133 #ifdef CONFIG_TEGRA_SPI 134 pin_mux_spi(); 135 #endif 136 137 #ifdef CONFIG_PWM_TEGRA 138 if (pwm_init(gd->fdt_blob)) 139 debug("%s: Failed to init pwm\n", __func__); 140 #endif 141 #ifdef CONFIG_LCD 142 pin_mux_display(); 143 tegra_lcd_check_next_stage(gd->fdt_blob, 0); 144 #endif 145 /* boot param addr */ 146 gd->bd->bi_boot_params = (NV_PA_SDRAM_BASE + 0x100); 147 148 power_det_init(); 149 150 #ifdef CONFIG_SYS_I2C_TEGRA 151 # ifdef CONFIG_TEGRA_PMU 152 if (pmu_set_nominal()) 153 debug("Failed to select nominal voltages\n"); 154 # ifdef CONFIG_TEGRA_CLOCK_SCALING 155 err = board_emc_init(); 156 if (err) 157 debug("Memory controller init failed: %d\n", err); 158 # endif 159 # endif /* CONFIG_TEGRA_PMU */ 160 #ifdef CONFIG_AS3722_POWER 161 err = as3722_init(NULL); 162 if (err && err != -ENODEV) 163 return err; 164 #endif 165 #endif /* CONFIG_SYS_I2C_TEGRA */ 166 167 #ifdef CONFIG_USB_EHCI_TEGRA 168 pin_mux_usb(); 169 #endif 170 171 #ifdef CONFIG_LCD 172 board_id = tegra_board_id(); 173 err = tegra_lcd_pmic_init(board_id); 174 if (err) 175 return err; 176 tegra_lcd_check_next_stage(gd->fdt_blob, 0); 177 #endif 178 179 #ifdef CONFIG_TEGRA_NAND 180 pin_mux_nand(); 181 #endif 182 183 tegra_xusb_padctl_init(gd->fdt_blob); 184 185 #ifdef CONFIG_TEGRA_LP0 186 /* save Sdram params to PMC 2, 4, and 24 for WB0 */ 187 warmboot_save_sdram_params(); 188 189 /* prepare the WB code to LP0 location */ 190 warmboot_prepare_code(TEGRA_LP0_ADDR, TEGRA_LP0_SIZE); 191 #endif 192 return nvidia_board_init(); 193 } 194 195 #ifdef CONFIG_BOARD_EARLY_INIT_F 196 static void __gpio_early_init(void) 197 { 198 } 199 200 void gpio_early_init(void) __attribute__((weak, alias("__gpio_early_init"))); 201 202 int board_early_init_f(void) 203 { 204 /* Do any special system timer/TSC setup */ 205 #if defined(CONFIG_TEGRA_SUPPORT_NON_SECURE) 206 if (!tegra_cpu_is_non_secure()) 207 #endif 208 arch_timer_init(); 209 210 pinmux_init(); 211 board_init_uart_f(); 212 213 /* Initialize periph GPIOs */ 214 gpio_early_init(); 215 gpio_early_init_uart(); 216 #ifdef CONFIG_LCD 217 tegra_lcd_early_init(gd->fdt_blob); 218 #endif 219 220 return 0; 221 } 222 #endif /* EARLY_INIT */ 223 224 int board_late_init(void) 225 { 226 #ifdef CONFIG_LCD 227 /* Make sure we finish initing the LCD */ 228 tegra_lcd_check_next_stage(gd->fdt_blob, 1); 229 #endif 230 #if defined(CONFIG_TEGRA_SUPPORT_NON_SECURE) 231 if (tegra_cpu_is_non_secure()) { 232 printf("CPU is in NS mode\n"); 233 setenv("cpu_ns_mode", "1"); 234 } else { 235 setenv("cpu_ns_mode", ""); 236 } 237 #endif 238 start_cpu_fan(); 239 240 return 0; 241 } 242 243 #if defined(CONFIG_TEGRA_MMC) 244 __weak void pin_mux_mmc(void) 245 { 246 } 247 248 /* this is a weak define that we are overriding */ 249 int board_mmc_init(bd_t *bd) 250 { 251 debug("%s called\n", __func__); 252 253 /* Enable muxes, etc. for SDMMC controllers */ 254 pin_mux_mmc(); 255 256 debug("%s: init MMC\n", __func__); 257 tegra_mmc_init(); 258 259 return 0; 260 } 261 262 void pad_init_mmc(struct mmc_host *host) 263 { 264 #if defined(CONFIG_TEGRA30) 265 enum periph_id id = host->mmc_id; 266 u32 val; 267 268 debug("%s: sdmmc address = %08x, id = %d\n", __func__, 269 (unsigned int)host->reg, id); 270 271 /* Set the pad drive strength for SDMMC1 or 3 only */ 272 if (id != PERIPH_ID_SDMMC1 && id != PERIPH_ID_SDMMC3) { 273 debug("%s: settings are only valid for SDMMC1/SDMMC3!\n", 274 __func__); 275 return; 276 } 277 278 val = readl(&host->reg->sdmemcmppadctl); 279 val &= 0xFFFFFFF0; 280 val |= MEMCOMP_PADCTRL_VREF; 281 writel(val, &host->reg->sdmemcmppadctl); 282 283 val = readl(&host->reg->autocalcfg); 284 val &= 0xFFFF0000; 285 val |= AUTO_CAL_PU_OFFSET | AUTO_CAL_PD_OFFSET | AUTO_CAL_ENABLED; 286 writel(val, &host->reg->autocalcfg); 287 #endif /* T30 */ 288 } 289 #endif /* MMC */ 290 291 /* 292 * In some SW environments, a memory carve-out exists to house a secure 293 * monitor, a trusted OS, and/or various statically allocated media buffers. 294 * 295 * This carveout exists at the highest possible address that is within a 296 * 32-bit physical address space. 297 * 298 * This function returns the total size of this carve-out. At present, the 299 * returned value is hard-coded for simplicity. In the future, it may be 300 * possible to determine the carve-out size: 301 * - By querying some run-time information source, such as: 302 * - A structure passed to U-Boot by earlier boot software. 303 * - SoC registers. 304 * - A call into the secure monitor. 305 * - In the per-board U-Boot configuration header, based on knowledge of the 306 * SW environment that U-Boot is being built for. 307 * 308 * For now, we support two configurations in U-Boot: 309 * - 32-bit ports without any form of carve-out. 310 * - 64 bit ports which are assumed to use a carve-out of a conservatively 311 * hard-coded size. 312 */ 313 static ulong carveout_size(void) 314 { 315 #ifdef CONFIG_ARM64 316 return SZ_512M; 317 #else 318 return 0; 319 #endif 320 } 321 322 /* 323 * Determine the amount of usable RAM below 4GiB, taking into account any 324 * carve-out that may be assigned. 325 */ 326 static ulong usable_ram_size_below_4g(void) 327 { 328 ulong total_size_below_4g; 329 ulong usable_size_below_4g; 330 331 /* 332 * The total size of RAM below 4GiB is the lesser address of: 333 * (a) 2GiB itself (RAM starts at 2GiB, and 4GiB - 2GiB == 2GiB). 334 * (b) The size RAM physically present in the system. 335 */ 336 if (gd->ram_size < SZ_2G) 337 total_size_below_4g = gd->ram_size; 338 else 339 total_size_below_4g = SZ_2G; 340 341 /* Calculate usable RAM by subtracting out any carve-out size */ 342 usable_size_below_4g = total_size_below_4g - carveout_size(); 343 344 return usable_size_below_4g; 345 } 346 347 /* 348 * Represent all available RAM in either one or two banks. 349 * 350 * The first bank describes any usable RAM below 4GiB. 351 * The second bank describes any RAM above 4GiB. 352 * 353 * This split is driven by the following requirements: 354 * - The NVIDIA L4T kernel requires separate entries in the DT /memory/reg 355 * property for memory below and above the 4GiB boundary. The layout of that 356 * DT property is directly driven by the entries in the U-Boot bank array. 357 * - The potential existence of a carve-out at the end of RAM below 4GiB can 358 * only be represented using multiple banks. 359 * 360 * Explicitly removing the carve-out RAM from the bank entries makes the RAM 361 * layout a bit more obvious, e.g. when running "bdinfo" at the U-Boot 362 * command-line. 363 * 364 * This does mean that the DT U-Boot passes to the Linux kernel will not 365 * include this RAM in /memory/reg at all. An alternative would be to include 366 * all RAM in the U-Boot banks (and hence DT), and add a /memreserve/ node 367 * into DT to stop the kernel from using the RAM. IIUC, I don't /think/ the 368 * Linux kernel will ever need to access any RAM in* the carve-out via a CPU 369 * mapping, so either way is acceptable. 370 * 371 * On 32-bit systems, we never define a bank for RAM above 4GiB, since the 372 * start address of that bank cannot be represented in the 32-bit .size 373 * field. 374 */ 375 void dram_init_banksize(void) 376 { 377 gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE; 378 gd->bd->bi_dram[0].size = usable_ram_size_below_4g(); 379 380 #ifdef CONFIG_PCI 381 gd->pci_ram_top = gd->bd->bi_dram[0].start + gd->bd->bi_dram[0].size; 382 #endif 383 384 #ifdef CONFIG_PHYS_64BIT 385 if (gd->ram_size > SZ_2G) { 386 gd->bd->bi_dram[1].start = 0x100000000; 387 gd->bd->bi_dram[1].size = gd->ram_size - SZ_2G; 388 } else 389 #endif 390 { 391 gd->bd->bi_dram[1].start = 0; 392 gd->bd->bi_dram[1].size = 0; 393 } 394 } 395 396 /* 397 * Most hardware on 64-bit Tegra is still restricted to DMA to the lower 398 * 32-bits of the physical address space. Cap the maximum usable RAM area 399 * at 4 GiB to avoid DMA buffers from being allocated beyond the 32-bit 400 * boundary that most devices can address. Also, don't let U-Boot use any 401 * carve-out, as mentioned above. 402 * 403 * This function is called before dram_init_banksize(), so we can't simply 404 * return gd->bd->bi_dram[1].start + gd->bd->bi_dram[1].size. 405 */ 406 ulong board_get_usable_ram_top(ulong total_size) 407 { 408 return CONFIG_SYS_SDRAM_BASE + usable_ram_size_below_4g(); 409 } 410 411 /* 412 * This function is called right before the kernel is booted. "blob" is the 413 * device tree that will be passed to the kernel. 414 */ 415 int ft_system_setup(void *blob, bd_t *bd) 416 { 417 const char *gpu_path = 418 #if defined(CONFIG_TEGRA124) || defined(CONFIG_TEGRA210) 419 "/gpu@0,57000000"; 420 #else 421 NULL; 422 #endif 423 424 /* Enable GPU node if GPU setup has been performed */ 425 if (gpu_path != NULL) 426 return tegra_gpu_enable_node(blob, gpu_path); 427 428 return 0; 429 } 430