1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * (C) Copyright 2010,2011 4 * NVIDIA Corporation <www.nvidia.com> 5 */ 6 7 #include <common.h> 8 #include <dm.h> 9 #include <efi_loader.h> 10 #include <errno.h> 11 #include <ns16550.h> 12 #include <usb.h> 13 #include <asm/io.h> 14 #include <asm/arch-tegra/ap.h> 15 #include <asm/arch-tegra/board.h> 16 #include <asm/arch-tegra/clk_rst.h> 17 #include <asm/arch-tegra/pmc.h> 18 #include <asm/arch-tegra/sys_proto.h> 19 #include <asm/arch-tegra/uart.h> 20 #include <asm/arch-tegra/warmboot.h> 21 #include <asm/arch-tegra/gpu.h> 22 #include <asm/arch-tegra/usb.h> 23 #include <asm/arch-tegra/xusb-padctl.h> 24 #include <asm/arch/clock.h> 25 #include <asm/arch/funcmux.h> 26 #include <asm/arch/pinmux.h> 27 #include <asm/arch/pmu.h> 28 #include <asm/arch/tegra.h> 29 #ifdef CONFIG_TEGRA_CLOCK_SCALING 30 #include <asm/arch/emc.h> 31 #endif 32 #include "emc.h" 33 34 DECLARE_GLOBAL_DATA_PTR; 35 36 #ifdef CONFIG_SPL_BUILD 37 /* TODO(sjg@chromium.org): Remove once SPL supports device tree */ 38 U_BOOT_DEVICE(tegra_gpios) = { 39 "gpio_tegra" 40 }; 41 #endif 42 43 __weak void pinmux_init(void) {} 44 __weak void pin_mux_usb(void) {} 45 __weak void pin_mux_spi(void) {} 46 __weak void pin_mux_mmc(void) {} 47 __weak void gpio_early_init_uart(void) {} 48 __weak void pin_mux_display(void) {} 49 __weak void start_cpu_fan(void) {} 50 51 #if defined(CONFIG_TEGRA_NAND) 52 __weak void pin_mux_nand(void) 53 { 54 funcmux_select(PERIPH_ID_NDFLASH, FUNCMUX_DEFAULT); 55 } 56 #endif 57 58 /* 59 * Routine: power_det_init 60 * Description: turn off power detects 61 */ 62 static void power_det_init(void) 63 { 64 #if defined(CONFIG_TEGRA20) 65 struct pmc_ctlr *const pmc = (struct pmc_ctlr *)NV_PA_PMC_BASE; 66 67 /* turn off power detects */ 68 writel(0, &pmc->pmc_pwr_det_latch); 69 writel(0, &pmc->pmc_pwr_det); 70 #endif 71 } 72 73 __weak int tegra_board_id(void) 74 { 75 return -1; 76 } 77 78 #ifdef CONFIG_DISPLAY_BOARDINFO 79 int checkboard(void) 80 { 81 int board_id = tegra_board_id(); 82 83 printf("Board: %s", CONFIG_TEGRA_BOARD_STRING); 84 if (board_id != -1) 85 printf(", ID: %d\n", board_id); 86 printf("\n"); 87 88 return 0; 89 } 90 #endif /* CONFIG_DISPLAY_BOARDINFO */ 91 92 __weak int tegra_lcd_pmic_init(int board_it) 93 { 94 return 0; 95 } 96 97 __weak int nvidia_board_init(void) 98 { 99 return 0; 100 } 101 102 /* 103 * Routine: board_init 104 * Description: Early hardware init. 105 */ 106 int board_init(void) 107 { 108 __maybe_unused int err; 109 __maybe_unused int board_id; 110 111 /* Do clocks and UART first so that printf() works */ 112 clock_init(); 113 clock_verify(); 114 115 tegra_gpu_config(); 116 117 #ifdef CONFIG_TEGRA_SPI 118 pin_mux_spi(); 119 #endif 120 121 #ifdef CONFIG_MMC_SDHCI_TEGRA 122 pin_mux_mmc(); 123 #endif 124 125 /* Init is handled automatically in the driver-model case */ 126 #if defined(CONFIG_DM_VIDEO) 127 pin_mux_display(); 128 #endif 129 /* boot param addr */ 130 gd->bd->bi_boot_params = (NV_PA_SDRAM_BASE + 0x100); 131 132 power_det_init(); 133 134 #ifdef CONFIG_SYS_I2C_TEGRA 135 # ifdef CONFIG_TEGRA_PMU 136 if (pmu_set_nominal()) 137 debug("Failed to select nominal voltages\n"); 138 # ifdef CONFIG_TEGRA_CLOCK_SCALING 139 err = board_emc_init(); 140 if (err) 141 debug("Memory controller init failed: %d\n", err); 142 # endif 143 # endif /* CONFIG_TEGRA_PMU */ 144 #endif /* CONFIG_SYS_I2C_TEGRA */ 145 146 #ifdef CONFIG_USB_EHCI_TEGRA 147 pin_mux_usb(); 148 #endif 149 150 #if defined(CONFIG_DM_VIDEO) 151 board_id = tegra_board_id(); 152 err = tegra_lcd_pmic_init(board_id); 153 if (err) { 154 debug("Failed to set up LCD PMIC\n"); 155 return err; 156 } 157 #endif 158 159 #ifdef CONFIG_TEGRA_NAND 160 pin_mux_nand(); 161 #endif 162 163 tegra_xusb_padctl_init(); 164 165 #ifdef CONFIG_TEGRA_LP0 166 /* save Sdram params to PMC 2, 4, and 24 for WB0 */ 167 warmboot_save_sdram_params(); 168 169 /* prepare the WB code to LP0 location */ 170 warmboot_prepare_code(TEGRA_LP0_ADDR, TEGRA_LP0_SIZE); 171 #endif 172 return nvidia_board_init(); 173 } 174 175 #ifdef CONFIG_BOARD_EARLY_INIT_F 176 static void __gpio_early_init(void) 177 { 178 } 179 180 void gpio_early_init(void) __attribute__((weak, alias("__gpio_early_init"))); 181 182 int board_early_init_f(void) 183 { 184 if (!clock_early_init_done()) 185 clock_early_init(); 186 187 #if defined(CONFIG_TEGRA_DISCONNECT_UDC_ON_BOOT) 188 #define USBCMD_FS2 (1 << 15) 189 { 190 struct usb_ctlr *usbctlr = (struct usb_ctlr *)0x7d000000; 191 writel(USBCMD_FS2, &usbctlr->usb_cmd); 192 } 193 #endif 194 195 /* Do any special system timer/TSC setup */ 196 #if defined(CONFIG_TEGRA_SUPPORT_NON_SECURE) 197 if (!tegra_cpu_is_non_secure()) 198 #endif 199 arch_timer_init(); 200 201 pinmux_init(); 202 board_init_uart_f(); 203 204 /* Initialize periph GPIOs */ 205 gpio_early_init(); 206 gpio_early_init_uart(); 207 208 return 0; 209 } 210 #endif /* EARLY_INIT */ 211 212 int board_late_init(void) 213 { 214 #if CONFIG_IS_ENABLED(EFI_LOADER) 215 if (gd->bd->bi_dram[1].start) { 216 /* 217 * Only bank 0 is below board_get_usable_ram_top(), so all of 218 * bank 1 is not mapped by the U-Boot MMU configuration, and so 219 * we must prevent EFI from using it. 220 */ 221 efi_add_memory_map(gd->bd->bi_dram[1].start, 222 gd->bd->bi_dram[1].size >> EFI_PAGE_SHIFT, 223 EFI_BOOT_SERVICES_DATA, false); 224 } 225 #endif 226 227 #if defined(CONFIG_TEGRA_SUPPORT_NON_SECURE) 228 if (tegra_cpu_is_non_secure()) { 229 printf("CPU is in NS mode\n"); 230 env_set("cpu_ns_mode", "1"); 231 } else { 232 env_set("cpu_ns_mode", ""); 233 } 234 #endif 235 start_cpu_fan(); 236 237 return 0; 238 } 239 240 /* 241 * In some SW environments, a memory carve-out exists to house a secure 242 * monitor, a trusted OS, and/or various statically allocated media buffers. 243 * 244 * This carveout exists at the highest possible address that is within a 245 * 32-bit physical address space. 246 * 247 * This function returns the total size of this carve-out. At present, the 248 * returned value is hard-coded for simplicity. In the future, it may be 249 * possible to determine the carve-out size: 250 * - By querying some run-time information source, such as: 251 * - A structure passed to U-Boot by earlier boot software. 252 * - SoC registers. 253 * - A call into the secure monitor. 254 * - In the per-board U-Boot configuration header, based on knowledge of the 255 * SW environment that U-Boot is being built for. 256 * 257 * For now, we support two configurations in U-Boot: 258 * - 32-bit ports without any form of carve-out. 259 * - 64 bit ports which are assumed to use a carve-out of a conservatively 260 * hard-coded size. 261 */ 262 static ulong carveout_size(void) 263 { 264 #ifdef CONFIG_ARM64 265 return SZ_512M; 266 #elif defined(CONFIG_ARMV7_SECURE_RESERVE_SIZE) 267 // BASE+SIZE might not == 4GB. If so, we want the carveout to cover 268 // from BASE to 4GB, not BASE to BASE+SIZE. 269 return (0 - CONFIG_ARMV7_SECURE_BASE) & ~(SZ_2M - 1); 270 #else 271 return 0; 272 #endif 273 } 274 275 /* 276 * Determine the amount of usable RAM below 4GiB, taking into account any 277 * carve-out that may be assigned. 278 */ 279 static ulong usable_ram_size_below_4g(void) 280 { 281 ulong total_size_below_4g; 282 ulong usable_size_below_4g; 283 284 /* 285 * The total size of RAM below 4GiB is the lesser address of: 286 * (a) 2GiB itself (RAM starts at 2GiB, and 4GiB - 2GiB == 2GiB). 287 * (b) The size RAM physically present in the system. 288 */ 289 if (gd->ram_size < SZ_2G) 290 total_size_below_4g = gd->ram_size; 291 else 292 total_size_below_4g = SZ_2G; 293 294 /* Calculate usable RAM by subtracting out any carve-out size */ 295 usable_size_below_4g = total_size_below_4g - carveout_size(); 296 297 return usable_size_below_4g; 298 } 299 300 /* 301 * Represent all available RAM in either one or two banks. 302 * 303 * The first bank describes any usable RAM below 4GiB. 304 * The second bank describes any RAM above 4GiB. 305 * 306 * This split is driven by the following requirements: 307 * - The NVIDIA L4T kernel requires separate entries in the DT /memory/reg 308 * property for memory below and above the 4GiB boundary. The layout of that 309 * DT property is directly driven by the entries in the U-Boot bank array. 310 * - The potential existence of a carve-out at the end of RAM below 4GiB can 311 * only be represented using multiple banks. 312 * 313 * Explicitly removing the carve-out RAM from the bank entries makes the RAM 314 * layout a bit more obvious, e.g. when running "bdinfo" at the U-Boot 315 * command-line. 316 * 317 * This does mean that the DT U-Boot passes to the Linux kernel will not 318 * include this RAM in /memory/reg at all. An alternative would be to include 319 * all RAM in the U-Boot banks (and hence DT), and add a /memreserve/ node 320 * into DT to stop the kernel from using the RAM. IIUC, I don't /think/ the 321 * Linux kernel will ever need to access any RAM in* the carve-out via a CPU 322 * mapping, so either way is acceptable. 323 * 324 * On 32-bit systems, we never define a bank for RAM above 4GiB, since the 325 * start address of that bank cannot be represented in the 32-bit .size 326 * field. 327 */ 328 int dram_init_banksize(void) 329 { 330 gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE; 331 gd->bd->bi_dram[0].size = usable_ram_size_below_4g(); 332 333 #ifdef CONFIG_PCI 334 gd->pci_ram_top = gd->bd->bi_dram[0].start + gd->bd->bi_dram[0].size; 335 #endif 336 337 #ifdef CONFIG_PHYS_64BIT 338 if (gd->ram_size > SZ_2G) { 339 gd->bd->bi_dram[1].start = 0x100000000; 340 gd->bd->bi_dram[1].size = gd->ram_size - SZ_2G; 341 } else 342 #endif 343 { 344 gd->bd->bi_dram[1].start = 0; 345 gd->bd->bi_dram[1].size = 0; 346 } 347 348 return 0; 349 } 350 351 /* 352 * Most hardware on 64-bit Tegra is still restricted to DMA to the lower 353 * 32-bits of the physical address space. Cap the maximum usable RAM area 354 * at 4 GiB to avoid DMA buffers from being allocated beyond the 32-bit 355 * boundary that most devices can address. Also, don't let U-Boot use any 356 * carve-out, as mentioned above. 357 * 358 * This function is called before dram_init_banksize(), so we can't simply 359 * return gd->bd->bi_dram[1].start + gd->bd->bi_dram[1].size. 360 */ 361 ulong board_get_usable_ram_top(ulong total_size) 362 { 363 return CONFIG_SYS_SDRAM_BASE + usable_ram_size_below_4g(); 364 } 365