1 /* 2 * (C) Copyright 2010,2011 3 * NVIDIA Corporation <www.nvidia.com> 4 * 5 * SPDX-License-Identifier: GPL-2.0+ 6 */ 7 8 #include <common.h> 9 #include <dm.h> 10 #include <errno.h> 11 #include <ns16550.h> 12 #include <usb.h> 13 #include <asm/io.h> 14 #include <asm/arch-tegra/ap.h> 15 #include <asm/arch-tegra/board.h> 16 #include <asm/arch-tegra/clk_rst.h> 17 #include <asm/arch-tegra/pmc.h> 18 #include <asm/arch-tegra/sys_proto.h> 19 #include <asm/arch-tegra/uart.h> 20 #include <asm/arch-tegra/warmboot.h> 21 #include <asm/arch-tegra/gpu.h> 22 #include <asm/arch-tegra/usb.h> 23 #include <asm/arch-tegra/xusb-padctl.h> 24 #include <asm/arch/clock.h> 25 #include <asm/arch/funcmux.h> 26 #include <asm/arch/pinmux.h> 27 #include <asm/arch/pmu.h> 28 #include <asm/arch/tegra.h> 29 #ifdef CONFIG_TEGRA_CLOCK_SCALING 30 #include <asm/arch/emc.h> 31 #endif 32 #include <power/as3722.h> 33 #include "emc.h" 34 35 DECLARE_GLOBAL_DATA_PTR; 36 37 #ifdef CONFIG_SPL_BUILD 38 /* TODO(sjg@chromium.org): Remove once SPL supports device tree */ 39 U_BOOT_DEVICE(tegra_gpios) = { 40 "gpio_tegra" 41 }; 42 #endif 43 44 __weak void pinmux_init(void) {} 45 __weak void pin_mux_usb(void) {} 46 __weak void pin_mux_spi(void) {} 47 __weak void pin_mux_mmc(void) {} 48 __weak void gpio_early_init_uart(void) {} 49 __weak void pin_mux_display(void) {} 50 __weak void start_cpu_fan(void) {} 51 52 #if defined(CONFIG_TEGRA_NAND) 53 __weak void pin_mux_nand(void) 54 { 55 funcmux_select(PERIPH_ID_NDFLASH, FUNCMUX_DEFAULT); 56 } 57 #endif 58 59 /* 60 * Routine: power_det_init 61 * Description: turn off power detects 62 */ 63 static void power_det_init(void) 64 { 65 #if defined(CONFIG_TEGRA20) 66 struct pmc_ctlr *const pmc = (struct pmc_ctlr *)NV_PA_PMC_BASE; 67 68 /* turn off power detects */ 69 writel(0, &pmc->pmc_pwr_det_latch); 70 writel(0, &pmc->pmc_pwr_det); 71 #endif 72 } 73 74 __weak int tegra_board_id(void) 75 { 76 return -1; 77 } 78 79 #ifdef CONFIG_DISPLAY_BOARDINFO 80 int checkboard(void) 81 { 82 int board_id = tegra_board_id(); 83 84 printf("Board: %s", CONFIG_TEGRA_BOARD_STRING); 85 if (board_id != -1) 86 printf(", ID: %d\n", board_id); 87 printf("\n"); 88 89 return 0; 90 } 91 #endif /* CONFIG_DISPLAY_BOARDINFO */ 92 93 __weak int tegra_lcd_pmic_init(int board_it) 94 { 95 return 0; 96 } 97 98 __weak int nvidia_board_init(void) 99 { 100 return 0; 101 } 102 103 /* 104 * Routine: board_init 105 * Description: Early hardware init. 106 */ 107 int board_init(void) 108 { 109 __maybe_unused int err; 110 __maybe_unused int board_id; 111 112 /* Do clocks and UART first so that printf() works */ 113 clock_init(); 114 clock_verify(); 115 116 tegra_gpu_config(); 117 118 #ifdef CONFIG_TEGRA_SPI 119 pin_mux_spi(); 120 #endif 121 122 #ifdef CONFIG_MMC_SDHCI_TEGRA 123 pin_mux_mmc(); 124 #endif 125 126 /* Init is handled automatically in the driver-model case */ 127 #if defined(CONFIG_DM_VIDEO) 128 pin_mux_display(); 129 #endif 130 /* boot param addr */ 131 gd->bd->bi_boot_params = (NV_PA_SDRAM_BASE + 0x100); 132 133 power_det_init(); 134 135 #ifdef CONFIG_SYS_I2C_TEGRA 136 # ifdef CONFIG_TEGRA_PMU 137 if (pmu_set_nominal()) 138 debug("Failed to select nominal voltages\n"); 139 # ifdef CONFIG_TEGRA_CLOCK_SCALING 140 err = board_emc_init(); 141 if (err) 142 debug("Memory controller init failed: %d\n", err); 143 # endif 144 # endif /* CONFIG_TEGRA_PMU */ 145 #ifdef CONFIG_PMIC_AS3722 146 err = as3722_init(NULL); 147 if (err && err != -ENODEV) 148 return err; 149 #endif 150 #endif /* CONFIG_SYS_I2C_TEGRA */ 151 152 #ifdef CONFIG_USB_EHCI_TEGRA 153 pin_mux_usb(); 154 #endif 155 156 #if defined(CONFIG_DM_VIDEO) 157 board_id = tegra_board_id(); 158 err = tegra_lcd_pmic_init(board_id); 159 if (err) { 160 debug("Failed to set up LCD PMIC\n"); 161 return err; 162 } 163 #endif 164 165 #ifdef CONFIG_TEGRA_NAND 166 pin_mux_nand(); 167 #endif 168 169 tegra_xusb_padctl_init(gd->fdt_blob); 170 171 #ifdef CONFIG_TEGRA_LP0 172 /* save Sdram params to PMC 2, 4, and 24 for WB0 */ 173 warmboot_save_sdram_params(); 174 175 /* prepare the WB code to LP0 location */ 176 warmboot_prepare_code(TEGRA_LP0_ADDR, TEGRA_LP0_SIZE); 177 #endif 178 return nvidia_board_init(); 179 } 180 181 #ifdef CONFIG_BOARD_EARLY_INIT_F 182 static void __gpio_early_init(void) 183 { 184 } 185 186 void gpio_early_init(void) __attribute__((weak, alias("__gpio_early_init"))); 187 188 int board_early_init_f(void) 189 { 190 if (!clock_early_init_done()) 191 clock_early_init(); 192 193 #if defined(CONFIG_TEGRA_DISCONNECT_UDC_ON_BOOT) 194 #define USBCMD_FS2 (1 << 15) 195 { 196 struct usb_ctlr *usbctlr = (struct usb_ctlr *)0x7d000000; 197 writel(USBCMD_FS2, &usbctlr->usb_cmd); 198 } 199 #endif 200 201 /* Do any special system timer/TSC setup */ 202 #if defined(CONFIG_TEGRA_SUPPORT_NON_SECURE) 203 if (!tegra_cpu_is_non_secure()) 204 #endif 205 arch_timer_init(); 206 207 pinmux_init(); 208 board_init_uart_f(); 209 210 /* Initialize periph GPIOs */ 211 gpio_early_init(); 212 gpio_early_init_uart(); 213 214 return 0; 215 } 216 #endif /* EARLY_INIT */ 217 218 int board_late_init(void) 219 { 220 #if defined(CONFIG_TEGRA_SUPPORT_NON_SECURE) 221 if (tegra_cpu_is_non_secure()) { 222 printf("CPU is in NS mode\n"); 223 setenv("cpu_ns_mode", "1"); 224 } else { 225 setenv("cpu_ns_mode", ""); 226 } 227 #endif 228 start_cpu_fan(); 229 230 return 0; 231 } 232 233 /* 234 * In some SW environments, a memory carve-out exists to house a secure 235 * monitor, a trusted OS, and/or various statically allocated media buffers. 236 * 237 * This carveout exists at the highest possible address that is within a 238 * 32-bit physical address space. 239 * 240 * This function returns the total size of this carve-out. At present, the 241 * returned value is hard-coded for simplicity. In the future, it may be 242 * possible to determine the carve-out size: 243 * - By querying some run-time information source, such as: 244 * - A structure passed to U-Boot by earlier boot software. 245 * - SoC registers. 246 * - A call into the secure monitor. 247 * - In the per-board U-Boot configuration header, based on knowledge of the 248 * SW environment that U-Boot is being built for. 249 * 250 * For now, we support two configurations in U-Boot: 251 * - 32-bit ports without any form of carve-out. 252 * - 64 bit ports which are assumed to use a carve-out of a conservatively 253 * hard-coded size. 254 */ 255 static ulong carveout_size(void) 256 { 257 #ifdef CONFIG_ARM64 258 return SZ_512M; 259 #else 260 return 0; 261 #endif 262 } 263 264 /* 265 * Determine the amount of usable RAM below 4GiB, taking into account any 266 * carve-out that may be assigned. 267 */ 268 static ulong usable_ram_size_below_4g(void) 269 { 270 ulong total_size_below_4g; 271 ulong usable_size_below_4g; 272 273 /* 274 * The total size of RAM below 4GiB is the lesser address of: 275 * (a) 2GiB itself (RAM starts at 2GiB, and 4GiB - 2GiB == 2GiB). 276 * (b) The size RAM physically present in the system. 277 */ 278 if (gd->ram_size < SZ_2G) 279 total_size_below_4g = gd->ram_size; 280 else 281 total_size_below_4g = SZ_2G; 282 283 /* Calculate usable RAM by subtracting out any carve-out size */ 284 usable_size_below_4g = total_size_below_4g - carveout_size(); 285 286 return usable_size_below_4g; 287 } 288 289 /* 290 * Represent all available RAM in either one or two banks. 291 * 292 * The first bank describes any usable RAM below 4GiB. 293 * The second bank describes any RAM above 4GiB. 294 * 295 * This split is driven by the following requirements: 296 * - The NVIDIA L4T kernel requires separate entries in the DT /memory/reg 297 * property for memory below and above the 4GiB boundary. The layout of that 298 * DT property is directly driven by the entries in the U-Boot bank array. 299 * - The potential existence of a carve-out at the end of RAM below 4GiB can 300 * only be represented using multiple banks. 301 * 302 * Explicitly removing the carve-out RAM from the bank entries makes the RAM 303 * layout a bit more obvious, e.g. when running "bdinfo" at the U-Boot 304 * command-line. 305 * 306 * This does mean that the DT U-Boot passes to the Linux kernel will not 307 * include this RAM in /memory/reg at all. An alternative would be to include 308 * all RAM in the U-Boot banks (and hence DT), and add a /memreserve/ node 309 * into DT to stop the kernel from using the RAM. IIUC, I don't /think/ the 310 * Linux kernel will ever need to access any RAM in* the carve-out via a CPU 311 * mapping, so either way is acceptable. 312 * 313 * On 32-bit systems, we never define a bank for RAM above 4GiB, since the 314 * start address of that bank cannot be represented in the 32-bit .size 315 * field. 316 */ 317 int dram_init_banksize(void) 318 { 319 gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE; 320 gd->bd->bi_dram[0].size = usable_ram_size_below_4g(); 321 322 #ifdef CONFIG_PCI 323 gd->pci_ram_top = gd->bd->bi_dram[0].start + gd->bd->bi_dram[0].size; 324 #endif 325 326 #ifdef CONFIG_PHYS_64BIT 327 if (gd->ram_size > SZ_2G) { 328 gd->bd->bi_dram[1].start = 0x100000000; 329 gd->bd->bi_dram[1].size = gd->ram_size - SZ_2G; 330 } else 331 #endif 332 { 333 gd->bd->bi_dram[1].start = 0; 334 gd->bd->bi_dram[1].size = 0; 335 } 336 337 return 0; 338 } 339 340 /* 341 * Most hardware on 64-bit Tegra is still restricted to DMA to the lower 342 * 32-bits of the physical address space. Cap the maximum usable RAM area 343 * at 4 GiB to avoid DMA buffers from being allocated beyond the 32-bit 344 * boundary that most devices can address. Also, don't let U-Boot use any 345 * carve-out, as mentioned above. 346 * 347 * This function is called before dram_init_banksize(), so we can't simply 348 * return gd->bd->bi_dram[1].start + gd->bd->bi_dram[1].size. 349 */ 350 ulong board_get_usable_ram_top(ulong total_size) 351 { 352 return CONFIG_SYS_SDRAM_BASE + usable_ram_size_below_4g(); 353 } 354