1 /* 2 * (C) Copyright 2010,2011 3 * NVIDIA Corporation <www.nvidia.com> 4 * 5 * SPDX-License-Identifier: GPL-2.0+ 6 */ 7 8 #include <common.h> 9 #include <dm.h> 10 #include <errno.h> 11 #include <ns16550.h> 12 #include <linux/compiler.h> 13 #include <linux/sizes.h> 14 #include <asm/io.h> 15 #include <asm/arch/clock.h> 16 #include <asm/arch/funcmux.h> 17 #include <asm/arch/pinmux.h> 18 #include <asm/arch/pmu.h> 19 #include <asm/arch/tegra.h> 20 #include <asm/arch-tegra/ap.h> 21 #include <asm/arch-tegra/board.h> 22 #include <asm/arch-tegra/clk_rst.h> 23 #include <asm/arch-tegra/pmc.h> 24 #include <asm/arch-tegra/sys_proto.h> 25 #include <asm/arch-tegra/uart.h> 26 #include <asm/arch-tegra/warmboot.h> 27 #include <asm/arch-tegra/gpu.h> 28 #ifdef CONFIG_TEGRA_CLOCK_SCALING 29 #include <asm/arch/emc.h> 30 #endif 31 #include <asm/arch-tegra/usb.h> 32 #ifdef CONFIG_USB_EHCI_TEGRA 33 #include <usb.h> 34 #endif 35 #ifdef CONFIG_TEGRA_MMC 36 #include <asm/arch-tegra/tegra_mmc.h> 37 #include <asm/arch-tegra/mmc.h> 38 #endif 39 #include <asm/arch-tegra/xusb-padctl.h> 40 #include <power/as3722.h> 41 #include <i2c.h> 42 #include <spi.h> 43 #include "emc.h" 44 45 DECLARE_GLOBAL_DATA_PTR; 46 47 #ifdef CONFIG_SPL_BUILD 48 /* TODO(sjg@chromium.org): Remove once SPL supports device tree */ 49 U_BOOT_DEVICE(tegra_gpios) = { 50 "gpio_tegra" 51 }; 52 #endif 53 54 __weak void pinmux_init(void) {} 55 __weak void pin_mux_usb(void) {} 56 __weak void pin_mux_spi(void) {} 57 __weak void gpio_early_init_uart(void) {} 58 __weak void pin_mux_display(void) {} 59 __weak void start_cpu_fan(void) {} 60 61 #if defined(CONFIG_TEGRA_NAND) 62 __weak void pin_mux_nand(void) 63 { 64 funcmux_select(PERIPH_ID_NDFLASH, FUNCMUX_DEFAULT); 65 } 66 #endif 67 68 /* 69 * Routine: power_det_init 70 * Description: turn off power detects 71 */ 72 static void power_det_init(void) 73 { 74 #if defined(CONFIG_TEGRA20) 75 struct pmc_ctlr *const pmc = (struct pmc_ctlr *)NV_PA_PMC_BASE; 76 77 /* turn off power detects */ 78 writel(0, &pmc->pmc_pwr_det_latch); 79 writel(0, &pmc->pmc_pwr_det); 80 #endif 81 } 82 83 __weak int tegra_board_id(void) 84 { 85 return -1; 86 } 87 88 #ifdef CONFIG_DISPLAY_BOARDINFO 89 int checkboard(void) 90 { 91 int board_id = tegra_board_id(); 92 93 printf("Board: %s", CONFIG_TEGRA_BOARD_STRING); 94 if (board_id != -1) 95 printf(", ID: %d\n", board_id); 96 printf("\n"); 97 98 return 0; 99 } 100 #endif /* CONFIG_DISPLAY_BOARDINFO */ 101 102 __weak int tegra_lcd_pmic_init(int board_it) 103 { 104 return 0; 105 } 106 107 __weak int nvidia_board_init(void) 108 { 109 return 0; 110 } 111 112 /* 113 * Routine: board_init 114 * Description: Early hardware init. 115 */ 116 int board_init(void) 117 { 118 __maybe_unused int err; 119 __maybe_unused int board_id; 120 121 /* Do clocks and UART first so that printf() works */ 122 clock_init(); 123 clock_verify(); 124 125 tegra_gpu_config(); 126 127 #ifdef CONFIG_TEGRA_SPI 128 pin_mux_spi(); 129 #endif 130 131 /* Init is handled automatically in the driver-model case */ 132 #if defined(CONFIG_DM_VIDEO) 133 pin_mux_display(); 134 #endif 135 /* boot param addr */ 136 gd->bd->bi_boot_params = (NV_PA_SDRAM_BASE + 0x100); 137 138 power_det_init(); 139 140 #ifdef CONFIG_SYS_I2C_TEGRA 141 # ifdef CONFIG_TEGRA_PMU 142 if (pmu_set_nominal()) 143 debug("Failed to select nominal voltages\n"); 144 # ifdef CONFIG_TEGRA_CLOCK_SCALING 145 err = board_emc_init(); 146 if (err) 147 debug("Memory controller init failed: %d\n", err); 148 # endif 149 # endif /* CONFIG_TEGRA_PMU */ 150 #ifdef CONFIG_AS3722_POWER 151 err = as3722_init(NULL); 152 if (err && err != -ENODEV) 153 return err; 154 #endif 155 #endif /* CONFIG_SYS_I2C_TEGRA */ 156 157 #ifdef CONFIG_USB_EHCI_TEGRA 158 pin_mux_usb(); 159 #endif 160 161 #if defined(CONFIG_DM_VIDEO) 162 board_id = tegra_board_id(); 163 err = tegra_lcd_pmic_init(board_id); 164 if (err) 165 return err; 166 #endif 167 168 #ifdef CONFIG_TEGRA_NAND 169 pin_mux_nand(); 170 #endif 171 172 tegra_xusb_padctl_init(gd->fdt_blob); 173 174 #ifdef CONFIG_TEGRA_LP0 175 /* save Sdram params to PMC 2, 4, and 24 for WB0 */ 176 warmboot_save_sdram_params(); 177 178 /* prepare the WB code to LP0 location */ 179 warmboot_prepare_code(TEGRA_LP0_ADDR, TEGRA_LP0_SIZE); 180 #endif 181 return nvidia_board_init(); 182 } 183 184 #ifdef CONFIG_BOARD_EARLY_INIT_F 185 static void __gpio_early_init(void) 186 { 187 } 188 189 void gpio_early_init(void) __attribute__((weak, alias("__gpio_early_init"))); 190 191 int board_early_init_f(void) 192 { 193 #if defined(CONFIG_TEGRA_DISCONNECT_UDC_ON_BOOT) 194 #define USBCMD_FS2 (1 << 15) 195 { 196 struct usb_ctlr *usbctlr = (struct usb_ctlr *)0x7d000000; 197 writel(USBCMD_FS2, &usbctlr->usb_cmd); 198 } 199 #endif 200 201 /* Do any special system timer/TSC setup */ 202 #if defined(CONFIG_TEGRA_SUPPORT_NON_SECURE) 203 if (!tegra_cpu_is_non_secure()) 204 #endif 205 arch_timer_init(); 206 207 pinmux_init(); 208 board_init_uart_f(); 209 210 /* Initialize periph GPIOs */ 211 gpio_early_init(); 212 gpio_early_init_uart(); 213 214 return 0; 215 } 216 #endif /* EARLY_INIT */ 217 218 int board_late_init(void) 219 { 220 #if defined(CONFIG_TEGRA_SUPPORT_NON_SECURE) 221 if (tegra_cpu_is_non_secure()) { 222 printf("CPU is in NS mode\n"); 223 setenv("cpu_ns_mode", "1"); 224 } else { 225 setenv("cpu_ns_mode", ""); 226 } 227 #endif 228 start_cpu_fan(); 229 230 return 0; 231 } 232 233 #if defined(CONFIG_TEGRA_MMC) 234 __weak void pin_mux_mmc(void) 235 { 236 } 237 238 /* this is a weak define that we are overriding */ 239 int board_mmc_init(bd_t *bd) 240 { 241 debug("%s called\n", __func__); 242 243 /* Enable muxes, etc. for SDMMC controllers */ 244 pin_mux_mmc(); 245 246 debug("%s: init MMC\n", __func__); 247 tegra_mmc_init(); 248 249 return 0; 250 } 251 252 void pad_init_mmc(struct mmc_host *host) 253 { 254 #if defined(CONFIG_TEGRA30) 255 enum periph_id id = host->mmc_id; 256 u32 val; 257 258 debug("%s: sdmmc address = %08x, id = %d\n", __func__, 259 (unsigned int)host->reg, id); 260 261 /* Set the pad drive strength for SDMMC1 or 3 only */ 262 if (id != PERIPH_ID_SDMMC1 && id != PERIPH_ID_SDMMC3) { 263 debug("%s: settings are only valid for SDMMC1/SDMMC3!\n", 264 __func__); 265 return; 266 } 267 268 val = readl(&host->reg->sdmemcmppadctl); 269 val &= 0xFFFFFFF0; 270 val |= MEMCOMP_PADCTRL_VREF; 271 writel(val, &host->reg->sdmemcmppadctl); 272 273 val = readl(&host->reg->autocalcfg); 274 val &= 0xFFFF0000; 275 val |= AUTO_CAL_PU_OFFSET | AUTO_CAL_PD_OFFSET | AUTO_CAL_ENABLED; 276 writel(val, &host->reg->autocalcfg); 277 #endif /* T30 */ 278 } 279 #endif /* MMC */ 280 281 /* 282 * In some SW environments, a memory carve-out exists to house a secure 283 * monitor, a trusted OS, and/or various statically allocated media buffers. 284 * 285 * This carveout exists at the highest possible address that is within a 286 * 32-bit physical address space. 287 * 288 * This function returns the total size of this carve-out. At present, the 289 * returned value is hard-coded for simplicity. In the future, it may be 290 * possible to determine the carve-out size: 291 * - By querying some run-time information source, such as: 292 * - A structure passed to U-Boot by earlier boot software. 293 * - SoC registers. 294 * - A call into the secure monitor. 295 * - In the per-board U-Boot configuration header, based on knowledge of the 296 * SW environment that U-Boot is being built for. 297 * 298 * For now, we support two configurations in U-Boot: 299 * - 32-bit ports without any form of carve-out. 300 * - 64 bit ports which are assumed to use a carve-out of a conservatively 301 * hard-coded size. 302 */ 303 static ulong carveout_size(void) 304 { 305 #ifdef CONFIG_ARM64 306 return SZ_512M; 307 #else 308 return 0; 309 #endif 310 } 311 312 /* 313 * Determine the amount of usable RAM below 4GiB, taking into account any 314 * carve-out that may be assigned. 315 */ 316 static ulong usable_ram_size_below_4g(void) 317 { 318 ulong total_size_below_4g; 319 ulong usable_size_below_4g; 320 321 /* 322 * The total size of RAM below 4GiB is the lesser address of: 323 * (a) 2GiB itself (RAM starts at 2GiB, and 4GiB - 2GiB == 2GiB). 324 * (b) The size RAM physically present in the system. 325 */ 326 if (gd->ram_size < SZ_2G) 327 total_size_below_4g = gd->ram_size; 328 else 329 total_size_below_4g = SZ_2G; 330 331 /* Calculate usable RAM by subtracting out any carve-out size */ 332 usable_size_below_4g = total_size_below_4g - carveout_size(); 333 334 return usable_size_below_4g; 335 } 336 337 /* 338 * Represent all available RAM in either one or two banks. 339 * 340 * The first bank describes any usable RAM below 4GiB. 341 * The second bank describes any RAM above 4GiB. 342 * 343 * This split is driven by the following requirements: 344 * - The NVIDIA L4T kernel requires separate entries in the DT /memory/reg 345 * property for memory below and above the 4GiB boundary. The layout of that 346 * DT property is directly driven by the entries in the U-Boot bank array. 347 * - The potential existence of a carve-out at the end of RAM below 4GiB can 348 * only be represented using multiple banks. 349 * 350 * Explicitly removing the carve-out RAM from the bank entries makes the RAM 351 * layout a bit more obvious, e.g. when running "bdinfo" at the U-Boot 352 * command-line. 353 * 354 * This does mean that the DT U-Boot passes to the Linux kernel will not 355 * include this RAM in /memory/reg at all. An alternative would be to include 356 * all RAM in the U-Boot banks (and hence DT), and add a /memreserve/ node 357 * into DT to stop the kernel from using the RAM. IIUC, I don't /think/ the 358 * Linux kernel will ever need to access any RAM in* the carve-out via a CPU 359 * mapping, so either way is acceptable. 360 * 361 * On 32-bit systems, we never define a bank for RAM above 4GiB, since the 362 * start address of that bank cannot be represented in the 32-bit .size 363 * field. 364 */ 365 void dram_init_banksize(void) 366 { 367 gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE; 368 gd->bd->bi_dram[0].size = usable_ram_size_below_4g(); 369 370 #ifdef CONFIG_PCI 371 gd->pci_ram_top = gd->bd->bi_dram[0].start + gd->bd->bi_dram[0].size; 372 #endif 373 374 #ifdef CONFIG_PHYS_64BIT 375 if (gd->ram_size > SZ_2G) { 376 gd->bd->bi_dram[1].start = 0x100000000; 377 gd->bd->bi_dram[1].size = gd->ram_size - SZ_2G; 378 } else 379 #endif 380 { 381 gd->bd->bi_dram[1].start = 0; 382 gd->bd->bi_dram[1].size = 0; 383 } 384 } 385 386 /* 387 * Most hardware on 64-bit Tegra is still restricted to DMA to the lower 388 * 32-bits of the physical address space. Cap the maximum usable RAM area 389 * at 4 GiB to avoid DMA buffers from being allocated beyond the 32-bit 390 * boundary that most devices can address. Also, don't let U-Boot use any 391 * carve-out, as mentioned above. 392 * 393 * This function is called before dram_init_banksize(), so we can't simply 394 * return gd->bd->bi_dram[1].start + gd->bd->bi_dram[1].size. 395 */ 396 ulong board_get_usable_ram_top(ulong total_size) 397 { 398 return CONFIG_SYS_SDRAM_BASE + usable_ram_size_below_4g(); 399 } 400 401 /* 402 * This function is called right before the kernel is booted. "blob" is the 403 * device tree that will be passed to the kernel. 404 */ 405 int ft_system_setup(void *blob, bd_t *bd) 406 { 407 const char *gpu_compats[] = { 408 #if defined(CONFIG_TEGRA124) 409 "nvidia,gk20a", 410 #endif 411 #if defined(CONFIG_TEGRA210) 412 "nvidia,gm20b", 413 #endif 414 }; 415 int i, ret; 416 417 /* Enable GPU node if GPU setup has been performed */ 418 for (i = 0; i < ARRAY_SIZE(gpu_compats); i++) { 419 ret = tegra_gpu_enable_node(blob, gpu_compats[i]); 420 if (ret) 421 return ret; 422 } 423 424 return 0; 425 } 426