1 /* 2 * (C) Copyright 2010-2015 3 * NVIDIA Corporation <www.nvidia.com> 4 * 5 * SPDX-License-Identifier: GPL-2.0+ 6 */ 7 8 #include <common.h> 9 #include <dm.h> 10 #include <ns16550.h> 11 #include <spl.h> 12 #include <asm/io.h> 13 #include <asm/arch/clock.h> 14 #include <asm/arch/funcmux.h> 15 #include <asm/arch/mc.h> 16 #include <asm/arch/tegra.h> 17 #include <asm/arch-tegra/ap.h> 18 #include <asm/arch-tegra/board.h> 19 #include <asm/arch-tegra/pmc.h> 20 #include <asm/arch-tegra/sys_proto.h> 21 #include <asm/arch-tegra/warmboot.h> 22 23 void save_boot_params_ret(void); 24 25 DECLARE_GLOBAL_DATA_PTR; 26 27 enum { 28 /* UARTs which we can enable */ 29 UARTA = 1 << 0, 30 UARTB = 1 << 1, 31 UARTC = 1 << 2, 32 UARTD = 1 << 3, 33 UARTE = 1 << 4, 34 UART_COUNT = 5, 35 }; 36 37 static bool from_spl __attribute__ ((section(".data"))); 38 39 #ifndef CONFIG_SPL_BUILD 40 void save_boot_params(u32 r0, u32 r1, u32 r2, u32 r3) 41 { 42 from_spl = r0 != UBOOT_NOT_LOADED_FROM_SPL; 43 save_boot_params_ret(); 44 } 45 #endif 46 47 bool spl_was_boot_source(void) 48 { 49 return from_spl; 50 } 51 52 #if defined(CONFIG_TEGRA_SUPPORT_NON_SECURE) 53 #if !defined(CONFIG_TEGRA124) 54 #error tegra_cpu_is_non_secure has only been validated on Tegra124 55 #endif 56 bool tegra_cpu_is_non_secure(void) 57 { 58 /* 59 * This register reads 0xffffffff in non-secure mode. This register 60 * only implements bits 31:20, so the lower bits will always read 0 in 61 * secure mode. Thus, the lower bits are an indicator for secure vs. 62 * non-secure mode. 63 */ 64 struct mc_ctlr *mc = (struct mc_ctlr *)NV_PA_MC_BASE; 65 uint32_t mc_s_cfg0 = readl(&mc->mc_security_cfg0); 66 return (mc_s_cfg0 & 1) == 1; 67 } 68 #endif 69 70 /* Read the RAM size directly from the memory controller */ 71 static phys_size_t query_sdram_size(void) 72 { 73 struct mc_ctlr *const mc = (struct mc_ctlr *)NV_PA_MC_BASE; 74 u32 emem_cfg; 75 phys_size_t size_bytes; 76 77 emem_cfg = readl(&mc->mc_emem_cfg); 78 #if defined(CONFIG_TEGRA20) 79 debug("mc->mc_emem_cfg (MEM_SIZE_KB) = 0x%08x\n", emem_cfg); 80 size_bytes = get_ram_size((void *)PHYS_SDRAM_1, emem_cfg * 1024); 81 #else 82 debug("mc->mc_emem_cfg (MEM_SIZE_MB) = 0x%08x\n", emem_cfg); 83 #ifndef CONFIG_PHYS_64BIT 84 /* 85 * If >=4GB RAM is present, the byte RAM size won't fit into 32-bits 86 * and will wrap. Clip the reported size to the maximum that a 32-bit 87 * variable can represent (rounded to a page). 88 */ 89 if (emem_cfg >= 4096) { 90 size_bytes = U32_MAX & ~(0x1000 - 1); 91 } else 92 #endif 93 { 94 /* RAM size EMC is programmed to. */ 95 size_bytes = (phys_size_t)emem_cfg * 1024 * 1024; 96 #ifndef CONFIG_ARM64 97 /* 98 * If all RAM fits within 32-bits, it can be accessed without 99 * LPAE, so go test the RAM size. Otherwise, we can't access 100 * all the RAM, and get_ram_size() would get confused, so 101 * avoid using it. There's no reason we should need this 102 * validation step anyway. 103 */ 104 if (emem_cfg <= (0 - PHYS_SDRAM_1) / (1024 * 1024)) 105 size_bytes = get_ram_size((void *)PHYS_SDRAM_1, 106 size_bytes); 107 #endif 108 } 109 #endif 110 111 #if defined(CONFIG_TEGRA30) || defined(CONFIG_TEGRA114) 112 /* External memory limited to 2047 MB due to IROM/HI-VEC */ 113 if (size_bytes == SZ_2G) 114 size_bytes -= SZ_1M; 115 #endif 116 117 return size_bytes; 118 } 119 120 int dram_init(void) 121 { 122 /* We do not initialise DRAM here. We just query the size */ 123 gd->ram_size = query_sdram_size(); 124 return 0; 125 } 126 127 static int uart_configs[] = { 128 #if defined(CONFIG_TEGRA20) 129 #if defined(CONFIG_TEGRA_UARTA_UAA_UAB) 130 FUNCMUX_UART1_UAA_UAB, 131 #elif defined(CONFIG_TEGRA_UARTA_GPU) 132 FUNCMUX_UART1_GPU, 133 #elif defined(CONFIG_TEGRA_UARTA_SDIO1) 134 FUNCMUX_UART1_SDIO1, 135 #else 136 FUNCMUX_UART1_IRRX_IRTX, 137 #endif 138 FUNCMUX_UART2_UAD, 139 -1, 140 FUNCMUX_UART4_GMC, 141 -1, 142 #elif defined(CONFIG_TEGRA30) 143 FUNCMUX_UART1_ULPI, /* UARTA */ 144 -1, 145 -1, 146 -1, 147 -1, 148 #elif defined(CONFIG_TEGRA114) 149 -1, 150 -1, 151 -1, 152 FUNCMUX_UART4_GMI, /* UARTD */ 153 -1, 154 #elif defined(CONFIG_TEGRA124) 155 FUNCMUX_UART1_KBC, /* UARTA */ 156 -1, 157 -1, 158 FUNCMUX_UART4_GPIO, /* UARTD */ 159 -1, 160 #else /* Tegra210 */ 161 FUNCMUX_UART1_UART1, /* UARTA */ 162 -1, 163 -1, 164 FUNCMUX_UART4_UART4, /* UARTD */ 165 -1, 166 #endif 167 }; 168 169 /** 170 * Set up the specified uarts 171 * 172 * @param uarts_ids Mask containing UARTs to init (UARTx) 173 */ 174 static void setup_uarts(int uart_ids) 175 { 176 static enum periph_id id_for_uart[] = { 177 PERIPH_ID_UART1, 178 PERIPH_ID_UART2, 179 PERIPH_ID_UART3, 180 PERIPH_ID_UART4, 181 PERIPH_ID_UART5, 182 }; 183 size_t i; 184 185 for (i = 0; i < UART_COUNT; i++) { 186 if (uart_ids & (1 << i)) { 187 enum periph_id id = id_for_uart[i]; 188 189 funcmux_select(id, uart_configs[i]); 190 clock_ll_start_uart(id); 191 } 192 } 193 } 194 195 void board_init_uart_f(void) 196 { 197 int uart_ids = 0; /* bit mask of which UART ids to enable */ 198 199 #ifdef CONFIG_TEGRA_ENABLE_UARTA 200 uart_ids |= UARTA; 201 #endif 202 #ifdef CONFIG_TEGRA_ENABLE_UARTB 203 uart_ids |= UARTB; 204 #endif 205 #ifdef CONFIG_TEGRA_ENABLE_UARTC 206 uart_ids |= UARTC; 207 #endif 208 #ifdef CONFIG_TEGRA_ENABLE_UARTD 209 uart_ids |= UARTD; 210 #endif 211 #ifdef CONFIG_TEGRA_ENABLE_UARTE 212 uart_ids |= UARTE; 213 #endif 214 setup_uarts(uart_ids); 215 } 216 217 #if !CONFIG_IS_ENABLED(OF_CONTROL) 218 static struct ns16550_platdata ns16550_com1_pdata = { 219 .base = CONFIG_SYS_NS16550_COM1, 220 .reg_shift = 2, 221 .clock = CONFIG_SYS_NS16550_CLK, 222 .fcr = UART_FCR_DEFVAL, 223 }; 224 225 U_BOOT_DEVICE(ns16550_com1) = { 226 "ns16550_serial", &ns16550_com1_pdata 227 }; 228 #endif 229 230 #if !defined(CONFIG_SYS_DCACHE_OFF) && !defined(CONFIG_ARM64) 231 void enable_caches(void) 232 { 233 /* Enable D-cache. I-cache is already enabled in start.S */ 234 dcache_enable(); 235 } 236 #endif 237