1 /* 2 * (C) Copyright 2010-2014 3 * NVIDIA Corporation <www.nvidia.com> 4 * 5 * SPDX-License-Identifier: GPL-2.0+ 6 */ 7 8 #include <common.h> 9 #include <asm/io.h> 10 #include <asm/arch/clock.h> 11 #include <asm/arch/funcmux.h> 12 #include <asm/arch/mc.h> 13 #include <asm/arch/tegra.h> 14 #include <asm/arch-tegra/board.h> 15 #include <asm/arch-tegra/pmc.h> 16 #include <asm/arch-tegra/sys_proto.h> 17 #include <asm/arch-tegra/warmboot.h> 18 19 DECLARE_GLOBAL_DATA_PTR; 20 21 enum { 22 /* UARTs which we can enable */ 23 UARTA = 1 << 0, 24 UARTB = 1 << 1, 25 UARTC = 1 << 2, 26 UARTD = 1 << 3, 27 UARTE = 1 << 4, 28 UART_COUNT = 5, 29 }; 30 31 /* Read the RAM size directly from the memory controller */ 32 unsigned int query_sdram_size(void) 33 { 34 struct mc_ctlr *const mc = (struct mc_ctlr *)NV_PA_MC_BASE; 35 u32 size_mb; 36 37 size_mb = readl(&mc->mc_emem_cfg); 38 #if defined(CONFIG_TEGRA20) 39 debug("mc->mc_emem_cfg (MEM_SIZE_KB) = 0x%08x\n", size_mb); 40 size_mb = get_ram_size((void *)PHYS_SDRAM_1, size_mb * 1024); 41 #else 42 debug("mc->mc_emem_cfg (MEM_SIZE_MB) = 0x%08x\n", size_mb); 43 size_mb = get_ram_size((void *)PHYS_SDRAM_1, size_mb * 1024 * 1024); 44 #endif 45 46 #if defined(CONFIG_TEGRA30) || defined(CONFIG_TEGRA114) 47 /* External memory limited to 2047 MB due to IROM/HI-VEC */ 48 if (size_mb == SZ_2G) size_mb -= SZ_1M; 49 #endif 50 51 return size_mb; 52 } 53 54 int dram_init(void) 55 { 56 /* We do not initialise DRAM here. We just query the size */ 57 gd->ram_size = query_sdram_size(); 58 return 0; 59 } 60 61 #ifdef CONFIG_DISPLAY_BOARDINFO 62 int checkboard(void) 63 { 64 printf("Board: %s\n", sysinfo.board_string); 65 return 0; 66 } 67 #endif /* CONFIG_DISPLAY_BOARDINFO */ 68 69 static int uart_configs[] = { 70 #if defined(CONFIG_TEGRA20) 71 #if defined(CONFIG_TEGRA_UARTA_UAA_UAB) 72 FUNCMUX_UART1_UAA_UAB, 73 #elif defined(CONFIG_TEGRA_UARTA_GPU) 74 FUNCMUX_UART1_GPU, 75 #elif defined(CONFIG_TEGRA_UARTA_SDIO1) 76 FUNCMUX_UART1_SDIO1, 77 #else 78 FUNCMUX_UART1_IRRX_IRTX, 79 #endif 80 FUNCMUX_UART2_UAD, 81 -1, 82 FUNCMUX_UART4_GMC, 83 -1, 84 #elif defined(CONFIG_TEGRA30) 85 FUNCMUX_UART1_ULPI, /* UARTA */ 86 -1, 87 -1, 88 -1, 89 -1, 90 #elif defined(CONFIG_TEGRA114) 91 -1, 92 -1, 93 -1, 94 FUNCMUX_UART4_GMI, /* UARTD */ 95 -1, 96 #else /* Tegra124 */ 97 FUNCMUX_UART1_KBC, /* UARTA */ 98 -1, 99 -1, 100 FUNCMUX_UART4_GPIO, /* UARTD */ 101 -1, 102 #endif 103 }; 104 105 /** 106 * Set up the specified uarts 107 * 108 * @param uarts_ids Mask containing UARTs to init (UARTx) 109 */ 110 static void setup_uarts(int uart_ids) 111 { 112 static enum periph_id id_for_uart[] = { 113 PERIPH_ID_UART1, 114 PERIPH_ID_UART2, 115 PERIPH_ID_UART3, 116 PERIPH_ID_UART4, 117 PERIPH_ID_UART5, 118 }; 119 size_t i; 120 121 for (i = 0; i < UART_COUNT; i++) { 122 if (uart_ids & (1 << i)) { 123 enum periph_id id = id_for_uart[i]; 124 125 funcmux_select(id, uart_configs[i]); 126 clock_ll_start_uart(id); 127 } 128 } 129 } 130 131 void board_init_uart_f(void) 132 { 133 int uart_ids = 0; /* bit mask of which UART ids to enable */ 134 135 #ifdef CONFIG_TEGRA_ENABLE_UARTA 136 uart_ids |= UARTA; 137 #endif 138 #ifdef CONFIG_TEGRA_ENABLE_UARTB 139 uart_ids |= UARTB; 140 #endif 141 #ifdef CONFIG_TEGRA_ENABLE_UARTC 142 uart_ids |= UARTC; 143 #endif 144 #ifdef CONFIG_TEGRA_ENABLE_UARTD 145 uart_ids |= UARTD; 146 #endif 147 #ifdef CONFIG_TEGRA_ENABLE_UARTE 148 uart_ids |= UARTE; 149 #endif 150 setup_uarts(uart_ids); 151 } 152 153 #ifndef CONFIG_SYS_DCACHE_OFF 154 void enable_caches(void) 155 { 156 /* Enable D-cache. I-cache is already enabled in start.S */ 157 dcache_enable(); 158 } 159 #endif 160