1 /* 2 * (C) Copyright 2010-2014 3 * NVIDIA Corporation <www.nvidia.com> 4 * 5 * SPDX-License-Identifier: GPL-2.0+ 6 */ 7 8 #include <common.h> 9 #include <asm/io.h> 10 #include <asm/arch/clock.h> 11 #include <asm/arch/funcmux.h> 12 #include <asm/arch/mc.h> 13 #include <asm/arch/tegra.h> 14 #include <asm/arch-tegra/ap.h> 15 #include <asm/arch-tegra/board.h> 16 #include <asm/arch-tegra/pmc.h> 17 #include <asm/arch-tegra/sys_proto.h> 18 #include <asm/arch-tegra/warmboot.h> 19 20 DECLARE_GLOBAL_DATA_PTR; 21 22 enum { 23 /* UARTs which we can enable */ 24 UARTA = 1 << 0, 25 UARTB = 1 << 1, 26 UARTC = 1 << 2, 27 UARTD = 1 << 3, 28 UARTE = 1 << 4, 29 UART_COUNT = 5, 30 }; 31 32 #if defined(CONFIG_TEGRA_SUPPORT_NON_SECURE) 33 #if !defined(CONFIG_TEGRA124) 34 #error tegra_cpu_is_non_secure has only been validated on Tegra124 35 #endif 36 bool tegra_cpu_is_non_secure(void) 37 { 38 /* 39 * This register reads 0xffffffff in non-secure mode. This register 40 * only implements bits 31:20, so the lower bits will always read 0 in 41 * secure mode. Thus, the lower bits are an indicator for secure vs. 42 * non-secure mode. 43 */ 44 struct mc_ctlr *mc = (struct mc_ctlr *)NV_PA_MC_BASE; 45 uint32_t mc_s_cfg0 = readl(&mc->mc_security_cfg0); 46 return (mc_s_cfg0 & 1) == 1; 47 } 48 #endif 49 50 /* Read the RAM size directly from the memory controller */ 51 unsigned int query_sdram_size(void) 52 { 53 struct mc_ctlr *const mc = (struct mc_ctlr *)NV_PA_MC_BASE; 54 u32 emem_cfg, size_bytes; 55 56 emem_cfg = readl(&mc->mc_emem_cfg); 57 #if defined(CONFIG_TEGRA20) 58 debug("mc->mc_emem_cfg (MEM_SIZE_KB) = 0x%08x\n", emem_cfg); 59 size_bytes = get_ram_size((void *)PHYS_SDRAM_1, emem_cfg * 1024); 60 #else 61 debug("mc->mc_emem_cfg (MEM_SIZE_MB) = 0x%08x\n", emem_cfg); 62 /* 63 * If >=4GB RAM is present, the byte RAM size won't fit into 32-bits 64 * and will wrap. Clip the reported size to the maximum that a 32-bit 65 * variable can represent (rounded to a page). 66 */ 67 if (emem_cfg >= 4096) { 68 size_bytes = U32_MAX & ~(0x1000 - 1); 69 } else { 70 /* RAM size EMC is programmed to. */ 71 size_bytes = emem_cfg * 1024 * 1024; 72 /* 73 * If all RAM fits within 32-bits, it can be accessed without 74 * LPAE, so go test the RAM size. Otherwise, we can't access 75 * all the RAM, and get_ram_size() would get confused, so 76 * avoid using it. There's no reason we should need this 77 * validation step anyway. 78 */ 79 if (emem_cfg <= (0 - PHYS_SDRAM_1) / (1024 * 1024)) 80 size_bytes = get_ram_size((void *)PHYS_SDRAM_1, 81 size_bytes); 82 } 83 #endif 84 85 #if defined(CONFIG_TEGRA30) || defined(CONFIG_TEGRA114) 86 /* External memory limited to 2047 MB due to IROM/HI-VEC */ 87 if (size_bytes == SZ_2G) 88 size_bytes -= SZ_1M; 89 #endif 90 91 return size_bytes; 92 } 93 94 int dram_init(void) 95 { 96 /* We do not initialise DRAM here. We just query the size */ 97 gd->ram_size = query_sdram_size(); 98 return 0; 99 } 100 101 #ifdef CONFIG_DISPLAY_BOARDINFO 102 int checkboard(void) 103 { 104 printf("Board: %s\n", sysinfo.board_string); 105 return 0; 106 } 107 #endif /* CONFIG_DISPLAY_BOARDINFO */ 108 109 static int uart_configs[] = { 110 #if defined(CONFIG_TEGRA20) 111 #if defined(CONFIG_TEGRA_UARTA_UAA_UAB) 112 FUNCMUX_UART1_UAA_UAB, 113 #elif defined(CONFIG_TEGRA_UARTA_GPU) 114 FUNCMUX_UART1_GPU, 115 #elif defined(CONFIG_TEGRA_UARTA_SDIO1) 116 FUNCMUX_UART1_SDIO1, 117 #else 118 FUNCMUX_UART1_IRRX_IRTX, 119 #endif 120 FUNCMUX_UART2_UAD, 121 -1, 122 FUNCMUX_UART4_GMC, 123 -1, 124 #elif defined(CONFIG_TEGRA30) 125 FUNCMUX_UART1_ULPI, /* UARTA */ 126 -1, 127 -1, 128 -1, 129 -1, 130 #elif defined(CONFIG_TEGRA114) 131 -1, 132 -1, 133 -1, 134 FUNCMUX_UART4_GMI, /* UARTD */ 135 -1, 136 #else /* Tegra124 */ 137 FUNCMUX_UART1_KBC, /* UARTA */ 138 -1, 139 -1, 140 FUNCMUX_UART4_GPIO, /* UARTD */ 141 -1, 142 #endif 143 }; 144 145 /** 146 * Set up the specified uarts 147 * 148 * @param uarts_ids Mask containing UARTs to init (UARTx) 149 */ 150 static void setup_uarts(int uart_ids) 151 { 152 static enum periph_id id_for_uart[] = { 153 PERIPH_ID_UART1, 154 PERIPH_ID_UART2, 155 PERIPH_ID_UART3, 156 PERIPH_ID_UART4, 157 PERIPH_ID_UART5, 158 }; 159 size_t i; 160 161 for (i = 0; i < UART_COUNT; i++) { 162 if (uart_ids & (1 << i)) { 163 enum periph_id id = id_for_uart[i]; 164 165 funcmux_select(id, uart_configs[i]); 166 clock_ll_start_uart(id); 167 } 168 } 169 } 170 171 void board_init_uart_f(void) 172 { 173 int uart_ids = 0; /* bit mask of which UART ids to enable */ 174 175 #ifdef CONFIG_TEGRA_ENABLE_UARTA 176 uart_ids |= UARTA; 177 #endif 178 #ifdef CONFIG_TEGRA_ENABLE_UARTB 179 uart_ids |= UARTB; 180 #endif 181 #ifdef CONFIG_TEGRA_ENABLE_UARTC 182 uart_ids |= UARTC; 183 #endif 184 #ifdef CONFIG_TEGRA_ENABLE_UARTD 185 uart_ids |= UARTD; 186 #endif 187 #ifdef CONFIG_TEGRA_ENABLE_UARTE 188 uart_ids |= UARTE; 189 #endif 190 setup_uarts(uart_ids); 191 } 192 193 #ifndef CONFIG_SYS_DCACHE_OFF 194 void enable_caches(void) 195 { 196 /* Enable D-cache. I-cache is already enabled in start.S */ 197 dcache_enable(); 198 } 199 #endif 200