1 /* 2 * (C) Copyright 2010-2014 3 * NVIDIA Corporation <www.nvidia.com> 4 * 5 * SPDX-License-Identifier: GPL-2.0+ 6 */ 7 8 /* Tegra AP (Application Processor) code */ 9 10 #include <common.h> 11 #include <asm/io.h> 12 #include <asm/arch/gp_padctrl.h> 13 #include <asm/arch-tegra/ap.h> 14 #include <asm/arch-tegra/clock.h> 15 #include <asm/arch-tegra/fuse.h> 16 #include <asm/arch-tegra/pmc.h> 17 #include <asm/arch-tegra/scu.h> 18 #include <asm/arch-tegra/tegra.h> 19 #include <asm/arch-tegra/warmboot.h> 20 21 int tegra_get_chip(void) 22 { 23 int rev; 24 struct apb_misc_gp_ctlr *gp = 25 (struct apb_misc_gp_ctlr *)NV_PA_APB_MISC_GP_BASE; 26 27 /* 28 * This is undocumented, Chip ID is bits 15:8 of the register 29 * APB_MISC + 0x804, and has value 0x20 for Tegra20, 0x30 for 30 * Tegra30, 0x35 for T114, and 0x40 for Tegra124. 31 */ 32 rev = (readl(&gp->hidrev) & HIDREV_CHIPID_MASK) >> HIDREV_CHIPID_SHIFT; 33 debug("%s: CHIPID is 0x%02X\n", __func__, rev); 34 35 return rev; 36 } 37 38 int tegra_get_sku_info(void) 39 { 40 int sku_id; 41 struct fuse_regs *fuse = (struct fuse_regs *)NV_PA_FUSE_BASE; 42 43 sku_id = readl(&fuse->sku_info) & 0xff; 44 debug("%s: SKU info byte is 0x%02X\n", __func__, sku_id); 45 46 return sku_id; 47 } 48 49 int tegra_get_chip_sku(void) 50 { 51 uint sku_id, chip_id; 52 53 chip_id = tegra_get_chip(); 54 sku_id = tegra_get_sku_info(); 55 56 switch (chip_id) { 57 case CHIPID_TEGRA20: 58 switch (sku_id) { 59 case SKU_ID_T20_7: 60 case SKU_ID_T20: 61 return TEGRA_SOC_T20; 62 case SKU_ID_T25SE: 63 case SKU_ID_AP25: 64 case SKU_ID_T25: 65 case SKU_ID_AP25E: 66 case SKU_ID_T25E: 67 return TEGRA_SOC_T25; 68 } 69 break; 70 case CHIPID_TEGRA30: 71 switch (sku_id) { 72 case SKU_ID_T33: 73 case SKU_ID_T30: 74 case SKU_ID_TM30MQS_P_A3: 75 default: 76 return TEGRA_SOC_T30; 77 } 78 break; 79 case CHIPID_TEGRA114: 80 switch (sku_id) { 81 case SKU_ID_T114_ENG: 82 case SKU_ID_T114_1: 83 default: 84 return TEGRA_SOC_T114; 85 } 86 break; 87 case CHIPID_TEGRA124: 88 switch (sku_id) { 89 case SKU_ID_T124_ENG: 90 default: 91 return TEGRA_SOC_T124; 92 } 93 break; 94 } 95 96 /* unknown chip/sku id */ 97 printf("%s: ERROR: UNKNOWN CHIP/SKU ID COMBO (0x%02X/0x%02X)\n", 98 __func__, chip_id, sku_id); 99 return TEGRA_SOC_UNKNOWN; 100 } 101 102 static void enable_scu(void) 103 { 104 struct scu_ctlr *scu = (struct scu_ctlr *)NV_PA_ARM_PERIPHBASE; 105 u32 reg; 106 107 /* Only enable the SCU on T20/T25 */ 108 if (tegra_get_chip() != CHIPID_TEGRA20) 109 return; 110 111 /* If SCU already setup/enabled, return */ 112 if (readl(&scu->scu_ctrl) & SCU_CTRL_ENABLE) 113 return; 114 115 /* Invalidate all ways for all processors */ 116 writel(0xFFFF, &scu->scu_inv_all); 117 118 /* Enable SCU - bit 0 */ 119 reg = readl(&scu->scu_ctrl); 120 reg |= SCU_CTRL_ENABLE; 121 writel(reg, &scu->scu_ctrl); 122 } 123 124 static u32 get_odmdata(void) 125 { 126 /* 127 * ODMDATA is stored in the BCT in IRAM by the BootROM. 128 * The BCT start and size are stored in the BIT in IRAM. 129 * Read the data @ bct_start + (bct_size - 12). This works 130 * on BCTs for currently supported SoCs, which are locked down. 131 * If this changes in new chips, we can revisit this algorithm. 132 */ 133 134 u32 bct_start, odmdata; 135 136 bct_start = readl(NV_PA_BASE_SRAM + NVBOOTINFOTABLE_BCTPTR); 137 odmdata = readl(bct_start + BCT_ODMDATA_OFFSET); 138 139 return odmdata; 140 } 141 142 static void init_pmc_scratch(void) 143 { 144 struct pmc_ctlr *const pmc = (struct pmc_ctlr *)NV_PA_PMC_BASE; 145 u32 odmdata; 146 int i; 147 148 /* SCRATCH0 is initialized by the boot ROM and shouldn't be cleared */ 149 for (i = 0; i < 23; i++) 150 writel(0, &pmc->pmc_scratch1+i); 151 152 /* ODMDATA is for kernel use to determine RAM size, LP config, etc. */ 153 odmdata = get_odmdata(); 154 writel(odmdata, &pmc->pmc_scratch20); 155 } 156 157 void s_init(void) 158 { 159 /* Init PMC scratch memory */ 160 init_pmc_scratch(); 161 162 enable_scu(); 163 164 /* init the cache */ 165 config_cache(); 166 167 /* init vpr */ 168 config_vpr(); 169 } 170