1 /* 2 * (C) Copyright 2010-2014 3 * NVIDIA Corporation <www.nvidia.com> 4 * 5 * SPDX-License-Identifier: GPL-2.0+ 6 */ 7 8 /* Tegra AP (Application Processor) code */ 9 10 #include <common.h> 11 #include <asm/io.h> 12 #include <asm/arch/gp_padctrl.h> 13 #include <asm/arch/mc.h> 14 #include <asm/arch-tegra/ap.h> 15 #include <asm/arch-tegra/clock.h> 16 #include <asm/arch-tegra/fuse.h> 17 #include <asm/arch-tegra/pmc.h> 18 #include <asm/arch-tegra/scu.h> 19 #include <asm/arch-tegra/tegra.h> 20 #include <asm/arch-tegra/warmboot.h> 21 22 int tegra_get_chip(void) 23 { 24 int rev; 25 struct apb_misc_gp_ctlr *gp = 26 (struct apb_misc_gp_ctlr *)NV_PA_APB_MISC_GP_BASE; 27 28 /* 29 * This is undocumented, Chip ID is bits 15:8 of the register 30 * APB_MISC + 0x804, and has value 0x20 for Tegra20, 0x30 for 31 * Tegra30, 0x35 for T114, and 0x40 for Tegra124. 32 */ 33 rev = (readl(&gp->hidrev) & HIDREV_CHIPID_MASK) >> HIDREV_CHIPID_SHIFT; 34 debug("%s: CHIPID is 0x%02X\n", __func__, rev); 35 36 return rev; 37 } 38 39 int tegra_get_sku_info(void) 40 { 41 int sku_id; 42 struct fuse_regs *fuse = (struct fuse_regs *)NV_PA_FUSE_BASE; 43 44 sku_id = readl(&fuse->sku_info) & 0xff; 45 debug("%s: SKU info byte is 0x%02X\n", __func__, sku_id); 46 47 return sku_id; 48 } 49 50 int tegra_get_chip_sku(void) 51 { 52 uint sku_id, chip_id; 53 54 chip_id = tegra_get_chip(); 55 sku_id = tegra_get_sku_info(); 56 57 switch (chip_id) { 58 case CHIPID_TEGRA20: 59 switch (sku_id) { 60 case SKU_ID_T20_7: 61 case SKU_ID_T20: 62 return TEGRA_SOC_T20; 63 case SKU_ID_T25SE: 64 case SKU_ID_AP25: 65 case SKU_ID_T25: 66 case SKU_ID_AP25E: 67 case SKU_ID_T25E: 68 return TEGRA_SOC_T25; 69 } 70 break; 71 case CHIPID_TEGRA30: 72 switch (sku_id) { 73 case SKU_ID_T33: 74 case SKU_ID_T30: 75 case SKU_ID_TM30MQS_P_A3: 76 default: 77 return TEGRA_SOC_T30; 78 } 79 break; 80 case CHIPID_TEGRA114: 81 switch (sku_id) { 82 case SKU_ID_T114_ENG: 83 case SKU_ID_T114_1: 84 default: 85 return TEGRA_SOC_T114; 86 } 87 break; 88 case CHIPID_TEGRA124: 89 switch (sku_id) { 90 case SKU_ID_T124_ENG: 91 default: 92 return TEGRA_SOC_T124; 93 } 94 break; 95 } 96 97 /* unknown chip/sku id */ 98 printf("%s: ERROR: UNKNOWN CHIP/SKU ID COMBO (0x%02X/0x%02X)\n", 99 __func__, chip_id, sku_id); 100 return TEGRA_SOC_UNKNOWN; 101 } 102 103 static void enable_scu(void) 104 { 105 struct scu_ctlr *scu = (struct scu_ctlr *)NV_PA_ARM_PERIPHBASE; 106 u32 reg; 107 108 /* Only enable the SCU on T20/T25 */ 109 if (tegra_get_chip() != CHIPID_TEGRA20) 110 return; 111 112 /* If SCU already setup/enabled, return */ 113 if (readl(&scu->scu_ctrl) & SCU_CTRL_ENABLE) 114 return; 115 116 /* Invalidate all ways for all processors */ 117 writel(0xFFFF, &scu->scu_inv_all); 118 119 /* Enable SCU - bit 0 */ 120 reg = readl(&scu->scu_ctrl); 121 reg |= SCU_CTRL_ENABLE; 122 writel(reg, &scu->scu_ctrl); 123 } 124 125 static u32 get_odmdata(void) 126 { 127 /* 128 * ODMDATA is stored in the BCT in IRAM by the BootROM. 129 * The BCT start and size are stored in the BIT in IRAM. 130 * Read the data @ bct_start + (bct_size - 12). This works 131 * on BCTs for currently supported SoCs, which are locked down. 132 * If this changes in new chips, we can revisit this algorithm. 133 */ 134 135 u32 bct_start, odmdata; 136 137 bct_start = readl(NV_PA_BASE_SRAM + NVBOOTINFOTABLE_BCTPTR); 138 odmdata = readl(bct_start + BCT_ODMDATA_OFFSET); 139 140 return odmdata; 141 } 142 143 static void init_pmc_scratch(void) 144 { 145 struct pmc_ctlr *const pmc = (struct pmc_ctlr *)NV_PA_PMC_BASE; 146 u32 odmdata; 147 int i; 148 149 /* SCRATCH0 is initialized by the boot ROM and shouldn't be cleared */ 150 for (i = 0; i < 23; i++) 151 writel(0, &pmc->pmc_scratch1+i); 152 153 /* ODMDATA is for kernel use to determine RAM size, LP config, etc. */ 154 odmdata = get_odmdata(); 155 writel(odmdata, &pmc->pmc_scratch20); 156 } 157 158 #ifdef CONFIG_ARMV7_SECURE_RESERVE_SIZE 159 void protect_secure_section(void) 160 { 161 struct mc_ctlr *mc = (struct mc_ctlr *)NV_PA_MC_BASE; 162 163 /* Must be MB aligned */ 164 BUILD_BUG_ON(CONFIG_ARMV7_SECURE_BASE & 0xFFFFF); 165 BUILD_BUG_ON(CONFIG_ARMV7_SECURE_RESERVE_SIZE & 0xFFFFF); 166 167 writel(CONFIG_ARMV7_SECURE_BASE, &mc->mc_security_cfg0); 168 writel(CONFIG_ARMV7_SECURE_RESERVE_SIZE >> 20, &mc->mc_security_cfg1); 169 } 170 #endif 171 172 #if defined(CONFIG_ARMV7_NONSEC) 173 static void smmu_flush(struct mc_ctlr *mc) 174 { 175 (void)readl(&mc->mc_smmu_config); 176 } 177 178 static void smmu_enable(void) 179 { 180 struct mc_ctlr *mc = (struct mc_ctlr *)NV_PA_MC_BASE; 181 u32 value; 182 183 /* 184 * Enable translation for all clients since access to this register 185 * is restricted to TrustZone-secured requestors. The kernel will use 186 * the per-SWGROUP enable bits to enable or disable translations. 187 */ 188 writel(0xffffffff, &mc->mc_smmu_translation_enable_0); 189 writel(0xffffffff, &mc->mc_smmu_translation_enable_1); 190 writel(0xffffffff, &mc->mc_smmu_translation_enable_2); 191 writel(0xffffffff, &mc->mc_smmu_translation_enable_3); 192 193 /* 194 * Enable SMMU globally since access to this register is restricted 195 * to TrustZone-secured requestors. 196 */ 197 value = readl(&mc->mc_smmu_config); 198 value |= TEGRA_MC_SMMU_CONFIG_ENABLE; 199 writel(value, &mc->mc_smmu_config); 200 201 smmu_flush(mc); 202 } 203 #else 204 static void smmu_enable(void) 205 { 206 } 207 #endif 208 209 void s_init(void) 210 { 211 /* Init PMC scratch memory */ 212 init_pmc_scratch(); 213 214 enable_scu(); 215 216 /* init the cache */ 217 config_cache(); 218 219 /* enable SMMU */ 220 smmu_enable(); 221 222 /* init vpr */ 223 config_vpr(); 224 } 225