1*83d290c5STom Rini // SPDX-License-Identifier: GPL-2.0+
2c2a7a7efSJagan Teki /*
3c2a7a7efSJagan Teki * Copyright (C) 2016 Siarhei Siamashka <siarhei.siamashka@gmail.com>
4c2a7a7efSJagan Teki */
5c2a7a7efSJagan Teki
6c2a7a7efSJagan Teki #include <common.h>
7c2a7a7efSJagan Teki #include <spl.h>
8c2a7a7efSJagan Teki #include <asm/gpio.h>
9c2a7a7efSJagan Teki #include <asm/io.h>
10c2a7a7efSJagan Teki #include <linux/libfdt.h>
11c2a7a7efSJagan Teki
12c2a7a7efSJagan Teki #ifdef CONFIG_SPL_OS_BOOT
13c2a7a7efSJagan Teki #error CONFIG_SPL_OS_BOOT is not supported yet
14c2a7a7efSJagan Teki #endif
15c2a7a7efSJagan Teki
16c2a7a7efSJagan Teki /*
17c2a7a7efSJagan Teki * This is a very simple U-Boot image loading implementation, trying to
18c2a7a7efSJagan Teki * replicate what the boot ROM is doing when loading the SPL. Because we
19c2a7a7efSJagan Teki * know the exact pins where the SPI Flash is connected and also know
20c2a7a7efSJagan Teki * that the Read Data Bytes (03h) command is supported, the hardware
21c2a7a7efSJagan Teki * configuration is very simple and we don't need the extra flexibility
22c2a7a7efSJagan Teki * of the SPI framework. Moreover, we rely on the default settings of
23c2a7a7efSJagan Teki * the SPI controler hardware registers and only adjust what needs to
24c2a7a7efSJagan Teki * be changed. This is good for the code size and this implementation
25c2a7a7efSJagan Teki * adds less than 400 bytes to the SPL.
26c2a7a7efSJagan Teki *
27c2a7a7efSJagan Teki * There are two variants of the SPI controller in Allwinner SoCs:
28c2a7a7efSJagan Teki * A10/A13/A20 (sun4i variant) and everything else (sun6i variant).
29c2a7a7efSJagan Teki * Both of them are supported.
30c2a7a7efSJagan Teki *
31c2a7a7efSJagan Teki * The pin mixing part is SoC specific and only A10/A13/A20/H3/A64 are
32c2a7a7efSJagan Teki * supported at the moment.
33c2a7a7efSJagan Teki */
34c2a7a7efSJagan Teki
35c2a7a7efSJagan Teki /*****************************************************************************/
36c2a7a7efSJagan Teki /* SUN4I variant of the SPI controller */
37c2a7a7efSJagan Teki /*****************************************************************************/
38c2a7a7efSJagan Teki
39c2a7a7efSJagan Teki #define SUN4I_SPI0_CCTL (0x01C05000 + 0x1C)
40c2a7a7efSJagan Teki #define SUN4I_SPI0_CTL (0x01C05000 + 0x08)
41c2a7a7efSJagan Teki #define SUN4I_SPI0_RX (0x01C05000 + 0x00)
42c2a7a7efSJagan Teki #define SUN4I_SPI0_TX (0x01C05000 + 0x04)
43c2a7a7efSJagan Teki #define SUN4I_SPI0_FIFO_STA (0x01C05000 + 0x28)
44c2a7a7efSJagan Teki #define SUN4I_SPI0_BC (0x01C05000 + 0x20)
45c2a7a7efSJagan Teki #define SUN4I_SPI0_TC (0x01C05000 + 0x24)
46c2a7a7efSJagan Teki
47c2a7a7efSJagan Teki #define SUN4I_CTL_ENABLE BIT(0)
48c2a7a7efSJagan Teki #define SUN4I_CTL_MASTER BIT(1)
49c2a7a7efSJagan Teki #define SUN4I_CTL_TF_RST BIT(8)
50c2a7a7efSJagan Teki #define SUN4I_CTL_RF_RST BIT(9)
51c2a7a7efSJagan Teki #define SUN4I_CTL_XCH BIT(10)
52c2a7a7efSJagan Teki
53c2a7a7efSJagan Teki /*****************************************************************************/
54c2a7a7efSJagan Teki /* SUN6I variant of the SPI controller */
55c2a7a7efSJagan Teki /*****************************************************************************/
56c2a7a7efSJagan Teki
57c2a7a7efSJagan Teki #define SUN6I_SPI0_CCTL (0x01C68000 + 0x24)
58c2a7a7efSJagan Teki #define SUN6I_SPI0_GCR (0x01C68000 + 0x04)
59c2a7a7efSJagan Teki #define SUN6I_SPI0_TCR (0x01C68000 + 0x08)
60c2a7a7efSJagan Teki #define SUN6I_SPI0_FIFO_STA (0x01C68000 + 0x1C)
61c2a7a7efSJagan Teki #define SUN6I_SPI0_MBC (0x01C68000 + 0x30)
62c2a7a7efSJagan Teki #define SUN6I_SPI0_MTC (0x01C68000 + 0x34)
63c2a7a7efSJagan Teki #define SUN6I_SPI0_BCC (0x01C68000 + 0x38)
64c2a7a7efSJagan Teki #define SUN6I_SPI0_TXD (0x01C68000 + 0x200)
65c2a7a7efSJagan Teki #define SUN6I_SPI0_RXD (0x01C68000 + 0x300)
66c2a7a7efSJagan Teki
67c2a7a7efSJagan Teki #define SUN6I_CTL_ENABLE BIT(0)
68c2a7a7efSJagan Teki #define SUN6I_CTL_MASTER BIT(1)
69c2a7a7efSJagan Teki #define SUN6I_CTL_SRST BIT(31)
70c2a7a7efSJagan Teki #define SUN6I_TCR_XCH BIT(31)
71c2a7a7efSJagan Teki
72c2a7a7efSJagan Teki /*****************************************************************************/
73c2a7a7efSJagan Teki
74c2a7a7efSJagan Teki #define CCM_AHB_GATING0 (0x01C20000 + 0x60)
75c2a7a7efSJagan Teki #define CCM_SPI0_CLK (0x01C20000 + 0xA0)
76c2a7a7efSJagan Teki #define SUN6I_BUS_SOFT_RST_REG0 (0x01C20000 + 0x2C0)
77c2a7a7efSJagan Teki
78c2a7a7efSJagan Teki #define AHB_RESET_SPI0_SHIFT 20
79c2a7a7efSJagan Teki #define AHB_GATE_OFFSET_SPI0 20
80c2a7a7efSJagan Teki
81c2a7a7efSJagan Teki #define SPI0_CLK_DIV_BY_2 0x1000
82c2a7a7efSJagan Teki #define SPI0_CLK_DIV_BY_4 0x1001
83c2a7a7efSJagan Teki
84c2a7a7efSJagan Teki /*****************************************************************************/
85c2a7a7efSJagan Teki
86c2a7a7efSJagan Teki /*
87c2a7a7efSJagan Teki * Allwinner A10/A20 SoCs were using pins PC0,PC1,PC2,PC23 for booting
88c2a7a7efSJagan Teki * from SPI Flash, everything else is using pins PC0,PC1,PC2,PC3.
89c2a7a7efSJagan Teki */
spi0_pinmux_setup(unsigned int pin_function)90c2a7a7efSJagan Teki static void spi0_pinmux_setup(unsigned int pin_function)
91c2a7a7efSJagan Teki {
92c2a7a7efSJagan Teki unsigned int pin;
93c2a7a7efSJagan Teki
94c2a7a7efSJagan Teki for (pin = SUNXI_GPC(0); pin <= SUNXI_GPC(2); pin++)
95c2a7a7efSJagan Teki sunxi_gpio_set_cfgpin(pin, pin_function);
96c2a7a7efSJagan Teki
97c2a7a7efSJagan Teki if (IS_ENABLED(CONFIG_MACH_SUN4I) || IS_ENABLED(CONFIG_MACH_SUN7I))
98c2a7a7efSJagan Teki sunxi_gpio_set_cfgpin(SUNXI_GPC(23), pin_function);
99c2a7a7efSJagan Teki else
100c2a7a7efSJagan Teki sunxi_gpio_set_cfgpin(SUNXI_GPC(3), pin_function);
101c2a7a7efSJagan Teki }
102c2a7a7efSJagan Teki
103c2a7a7efSJagan Teki /*
104c2a7a7efSJagan Teki * Setup 6 MHz from OSC24M (because the BROM is doing the same).
105c2a7a7efSJagan Teki */
spi0_enable_clock(void)106c2a7a7efSJagan Teki static void spi0_enable_clock(void)
107c2a7a7efSJagan Teki {
108c2a7a7efSJagan Teki /* Deassert SPI0 reset on SUN6I */
109c2a7a7efSJagan Teki if (IS_ENABLED(CONFIG_SUNXI_GEN_SUN6I))
110c2a7a7efSJagan Teki setbits_le32(SUN6I_BUS_SOFT_RST_REG0,
111c2a7a7efSJagan Teki (1 << AHB_RESET_SPI0_SHIFT));
112c2a7a7efSJagan Teki
113c2a7a7efSJagan Teki /* Open the SPI0 gate */
114c2a7a7efSJagan Teki setbits_le32(CCM_AHB_GATING0, (1 << AHB_GATE_OFFSET_SPI0));
115c2a7a7efSJagan Teki
116c2a7a7efSJagan Teki /* Divide by 4 */
117c2a7a7efSJagan Teki writel(SPI0_CLK_DIV_BY_4, IS_ENABLED(CONFIG_SUNXI_GEN_SUN6I) ?
118c2a7a7efSJagan Teki SUN6I_SPI0_CCTL : SUN4I_SPI0_CCTL);
119c2a7a7efSJagan Teki /* 24MHz from OSC24M */
120c2a7a7efSJagan Teki writel((1 << 31), CCM_SPI0_CLK);
121c2a7a7efSJagan Teki
122c2a7a7efSJagan Teki if (IS_ENABLED(CONFIG_SUNXI_GEN_SUN6I)) {
123c2a7a7efSJagan Teki /* Enable SPI in the master mode and do a soft reset */
124c2a7a7efSJagan Teki setbits_le32(SUN6I_SPI0_GCR, SUN6I_CTL_MASTER |
125c2a7a7efSJagan Teki SUN6I_CTL_ENABLE |
126c2a7a7efSJagan Teki SUN6I_CTL_SRST);
127c2a7a7efSJagan Teki /* Wait for completion */
128c2a7a7efSJagan Teki while (readl(SUN6I_SPI0_GCR) & SUN6I_CTL_SRST)
129c2a7a7efSJagan Teki ;
130c2a7a7efSJagan Teki } else {
131c2a7a7efSJagan Teki /* Enable SPI in the master mode and reset FIFO */
132c2a7a7efSJagan Teki setbits_le32(SUN4I_SPI0_CTL, SUN4I_CTL_MASTER |
133c2a7a7efSJagan Teki SUN4I_CTL_ENABLE |
134c2a7a7efSJagan Teki SUN4I_CTL_TF_RST |
135c2a7a7efSJagan Teki SUN4I_CTL_RF_RST);
136c2a7a7efSJagan Teki }
137c2a7a7efSJagan Teki }
138c2a7a7efSJagan Teki
spi0_disable_clock(void)139c2a7a7efSJagan Teki static void spi0_disable_clock(void)
140c2a7a7efSJagan Teki {
141c2a7a7efSJagan Teki /* Disable the SPI0 controller */
142c2a7a7efSJagan Teki if (IS_ENABLED(CONFIG_SUNXI_GEN_SUN6I))
143c2a7a7efSJagan Teki clrbits_le32(SUN6I_SPI0_GCR, SUN6I_CTL_MASTER |
144c2a7a7efSJagan Teki SUN6I_CTL_ENABLE);
145c2a7a7efSJagan Teki else
146c2a7a7efSJagan Teki clrbits_le32(SUN4I_SPI0_CTL, SUN4I_CTL_MASTER |
147c2a7a7efSJagan Teki SUN4I_CTL_ENABLE);
148c2a7a7efSJagan Teki
149c2a7a7efSJagan Teki /* Disable the SPI0 clock */
150c2a7a7efSJagan Teki writel(0, CCM_SPI0_CLK);
151c2a7a7efSJagan Teki
152c2a7a7efSJagan Teki /* Close the SPI0 gate */
153c2a7a7efSJagan Teki clrbits_le32(CCM_AHB_GATING0, (1 << AHB_GATE_OFFSET_SPI0));
154c2a7a7efSJagan Teki
155c2a7a7efSJagan Teki /* Assert SPI0 reset on SUN6I */
156c2a7a7efSJagan Teki if (IS_ENABLED(CONFIG_SUNXI_GEN_SUN6I))
157c2a7a7efSJagan Teki clrbits_le32(SUN6I_BUS_SOFT_RST_REG0,
158c2a7a7efSJagan Teki (1 << AHB_RESET_SPI0_SHIFT));
159c2a7a7efSJagan Teki }
160c2a7a7efSJagan Teki
spi0_init(void)161c2a7a7efSJagan Teki static void spi0_init(void)
162c2a7a7efSJagan Teki {
163c2a7a7efSJagan Teki unsigned int pin_function = SUNXI_GPC_SPI0;
164c2a7a7efSJagan Teki
165c2a7a7efSJagan Teki if (IS_ENABLED(CONFIG_MACH_SUN50I))
166c2a7a7efSJagan Teki pin_function = SUN50I_GPC_SPI0;
167c2a7a7efSJagan Teki
168c2a7a7efSJagan Teki spi0_pinmux_setup(pin_function);
169c2a7a7efSJagan Teki spi0_enable_clock();
170c2a7a7efSJagan Teki }
171c2a7a7efSJagan Teki
spi0_deinit(void)172c2a7a7efSJagan Teki static void spi0_deinit(void)
173c2a7a7efSJagan Teki {
174c2a7a7efSJagan Teki /* New SoCs can disable pins, older could only set them as input */
175c2a7a7efSJagan Teki unsigned int pin_function = SUNXI_GPIO_INPUT;
176c2a7a7efSJagan Teki if (IS_ENABLED(CONFIG_SUNXI_GEN_SUN6I))
177c2a7a7efSJagan Teki pin_function = SUNXI_GPIO_DISABLE;
178c2a7a7efSJagan Teki
179c2a7a7efSJagan Teki spi0_disable_clock();
180c2a7a7efSJagan Teki spi0_pinmux_setup(pin_function);
181c2a7a7efSJagan Teki }
182c2a7a7efSJagan Teki
183c2a7a7efSJagan Teki /*****************************************************************************/
184c2a7a7efSJagan Teki
185c2a7a7efSJagan Teki #define SPI_READ_MAX_SIZE 60 /* FIFO size, minus 4 bytes of the header */
186c2a7a7efSJagan Teki
sunxi_spi0_read_data(u8 * buf,u32 addr,u32 bufsize,ulong spi_ctl_reg,ulong spi_ctl_xch_bitmask,ulong spi_fifo_reg,ulong spi_tx_reg,ulong spi_rx_reg,ulong spi_bc_reg,ulong spi_tc_reg,ulong spi_bcc_reg)187c2a7a7efSJagan Teki static void sunxi_spi0_read_data(u8 *buf, u32 addr, u32 bufsize,
188c2a7a7efSJagan Teki ulong spi_ctl_reg,
189c2a7a7efSJagan Teki ulong spi_ctl_xch_bitmask,
190c2a7a7efSJagan Teki ulong spi_fifo_reg,
191c2a7a7efSJagan Teki ulong spi_tx_reg,
192c2a7a7efSJagan Teki ulong spi_rx_reg,
193c2a7a7efSJagan Teki ulong spi_bc_reg,
194c2a7a7efSJagan Teki ulong spi_tc_reg,
195c2a7a7efSJagan Teki ulong spi_bcc_reg)
196c2a7a7efSJagan Teki {
197c2a7a7efSJagan Teki writel(4 + bufsize, spi_bc_reg); /* Burst counter (total bytes) */
198c2a7a7efSJagan Teki writel(4, spi_tc_reg); /* Transfer counter (bytes to send) */
199c2a7a7efSJagan Teki if (spi_bcc_reg)
200c2a7a7efSJagan Teki writel(4, spi_bcc_reg); /* SUN6I also needs this */
201c2a7a7efSJagan Teki
202c2a7a7efSJagan Teki /* Send the Read Data Bytes (03h) command header */
203c2a7a7efSJagan Teki writeb(0x03, spi_tx_reg);
204c2a7a7efSJagan Teki writeb((u8)(addr >> 16), spi_tx_reg);
205c2a7a7efSJagan Teki writeb((u8)(addr >> 8), spi_tx_reg);
206c2a7a7efSJagan Teki writeb((u8)(addr), spi_tx_reg);
207c2a7a7efSJagan Teki
208c2a7a7efSJagan Teki /* Start the data transfer */
209c2a7a7efSJagan Teki setbits_le32(spi_ctl_reg, spi_ctl_xch_bitmask);
210c2a7a7efSJagan Teki
211c2a7a7efSJagan Teki /* Wait until everything is received in the RX FIFO */
212c2a7a7efSJagan Teki while ((readl(spi_fifo_reg) & 0x7F) < 4 + bufsize)
213c2a7a7efSJagan Teki ;
214c2a7a7efSJagan Teki
215c2a7a7efSJagan Teki /* Skip 4 bytes */
216c2a7a7efSJagan Teki readl(spi_rx_reg);
217c2a7a7efSJagan Teki
218c2a7a7efSJagan Teki /* Read the data */
219c2a7a7efSJagan Teki while (bufsize-- > 0)
220c2a7a7efSJagan Teki *buf++ = readb(spi_rx_reg);
221c2a7a7efSJagan Teki
222c2a7a7efSJagan Teki /* tSHSL time is up to 100 ns in various SPI flash datasheets */
223c2a7a7efSJagan Teki udelay(1);
224c2a7a7efSJagan Teki }
225c2a7a7efSJagan Teki
spi0_read_data(void * buf,u32 addr,u32 len)226c2a7a7efSJagan Teki static void spi0_read_data(void *buf, u32 addr, u32 len)
227c2a7a7efSJagan Teki {
228c2a7a7efSJagan Teki u8 *buf8 = buf;
229c2a7a7efSJagan Teki u32 chunk_len;
230c2a7a7efSJagan Teki
231c2a7a7efSJagan Teki while (len > 0) {
232c2a7a7efSJagan Teki chunk_len = len;
233c2a7a7efSJagan Teki if (chunk_len > SPI_READ_MAX_SIZE)
234c2a7a7efSJagan Teki chunk_len = SPI_READ_MAX_SIZE;
235c2a7a7efSJagan Teki
236c2a7a7efSJagan Teki if (IS_ENABLED(CONFIG_SUNXI_GEN_SUN6I)) {
237c2a7a7efSJagan Teki sunxi_spi0_read_data(buf8, addr, chunk_len,
238c2a7a7efSJagan Teki SUN6I_SPI0_TCR,
239c2a7a7efSJagan Teki SUN6I_TCR_XCH,
240c2a7a7efSJagan Teki SUN6I_SPI0_FIFO_STA,
241c2a7a7efSJagan Teki SUN6I_SPI0_TXD,
242c2a7a7efSJagan Teki SUN6I_SPI0_RXD,
243c2a7a7efSJagan Teki SUN6I_SPI0_MBC,
244c2a7a7efSJagan Teki SUN6I_SPI0_MTC,
245c2a7a7efSJagan Teki SUN6I_SPI0_BCC);
246c2a7a7efSJagan Teki } else {
247c2a7a7efSJagan Teki sunxi_spi0_read_data(buf8, addr, chunk_len,
248c2a7a7efSJagan Teki SUN4I_SPI0_CTL,
249c2a7a7efSJagan Teki SUN4I_CTL_XCH,
250c2a7a7efSJagan Teki SUN4I_SPI0_FIFO_STA,
251c2a7a7efSJagan Teki SUN4I_SPI0_TX,
252c2a7a7efSJagan Teki SUN4I_SPI0_RX,
253c2a7a7efSJagan Teki SUN4I_SPI0_BC,
254c2a7a7efSJagan Teki SUN4I_SPI0_TC,
255c2a7a7efSJagan Teki 0);
256c2a7a7efSJagan Teki }
257c2a7a7efSJagan Teki
258c2a7a7efSJagan Teki len -= chunk_len;
259c2a7a7efSJagan Teki buf8 += chunk_len;
260c2a7a7efSJagan Teki addr += chunk_len;
261c2a7a7efSJagan Teki }
262c2a7a7efSJagan Teki }
263c2a7a7efSJagan Teki
spi_load_read(struct spl_load_info * load,ulong sector,ulong count,void * buf)264c2a7a7efSJagan Teki static ulong spi_load_read(struct spl_load_info *load, ulong sector,
265c2a7a7efSJagan Teki ulong count, void *buf)
266c2a7a7efSJagan Teki {
267c2a7a7efSJagan Teki spi0_read_data(buf, sector, count);
268c2a7a7efSJagan Teki
269c2a7a7efSJagan Teki return count;
270c2a7a7efSJagan Teki }
271c2a7a7efSJagan Teki
272c2a7a7efSJagan Teki /*****************************************************************************/
273c2a7a7efSJagan Teki
spl_spi_load_image(struct spl_image_info * spl_image,struct spl_boot_device * bootdev)274c2a7a7efSJagan Teki static int spl_spi_load_image(struct spl_image_info *spl_image,
275c2a7a7efSJagan Teki struct spl_boot_device *bootdev)
276c2a7a7efSJagan Teki {
277c2a7a7efSJagan Teki int ret = 0;
278c2a7a7efSJagan Teki struct image_header *header;
279c2a7a7efSJagan Teki header = (struct image_header *)(CONFIG_SYS_TEXT_BASE);
280c2a7a7efSJagan Teki
281c2a7a7efSJagan Teki spi0_init();
282c2a7a7efSJagan Teki
283c2a7a7efSJagan Teki spi0_read_data((void *)header, CONFIG_SYS_SPI_U_BOOT_OFFS, 0x40);
284c2a7a7efSJagan Teki
285c2a7a7efSJagan Teki if (IS_ENABLED(CONFIG_SPL_LOAD_FIT) &&
286c2a7a7efSJagan Teki image_get_magic(header) == FDT_MAGIC) {
287c2a7a7efSJagan Teki struct spl_load_info load;
288c2a7a7efSJagan Teki
289c2a7a7efSJagan Teki debug("Found FIT image\n");
290c2a7a7efSJagan Teki load.dev = NULL;
291c2a7a7efSJagan Teki load.priv = NULL;
292c2a7a7efSJagan Teki load.filename = NULL;
293c2a7a7efSJagan Teki load.bl_len = 1;
294c2a7a7efSJagan Teki load.read = spi_load_read;
295c2a7a7efSJagan Teki ret = spl_load_simple_fit(spl_image, &load,
296c2a7a7efSJagan Teki CONFIG_SYS_SPI_U_BOOT_OFFS, header);
297c2a7a7efSJagan Teki } else {
298c2a7a7efSJagan Teki ret = spl_parse_image_header(spl_image, header);
299c2a7a7efSJagan Teki if (ret)
300c2a7a7efSJagan Teki return ret;
301c2a7a7efSJagan Teki
302c2a7a7efSJagan Teki spi0_read_data((void *)spl_image->load_addr,
303c2a7a7efSJagan Teki CONFIG_SYS_SPI_U_BOOT_OFFS, spl_image->size);
304c2a7a7efSJagan Teki }
305c2a7a7efSJagan Teki
306c2a7a7efSJagan Teki spi0_deinit();
307c2a7a7efSJagan Teki
308c2a7a7efSJagan Teki return ret;
309c2a7a7efSJagan Teki }
310c2a7a7efSJagan Teki /* Use priorty 0 to override the default if it happens to be linked in */
311c2a7a7efSJagan Teki SPL_LOAD_IMAGE_METHOD("sunxi SPI", 0, BOOT_DEVICE_SPI, spl_spi_load_image);
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