1 #include <common.h> 2 #include <asm/arch/dram.h> 3 #include <asm/arch/cpu.h> 4 5 void mctl_set_timing_params(uint16_t socid, struct dram_para *para) 6 { 7 struct sunxi_mctl_ctl_reg * const mctl_ctl = 8 (struct sunxi_mctl_ctl_reg *)SUNXI_DRAM_CTL0_BASE; 9 10 u8 tccd = 1; 11 u8 tfaw = ns_to_t(50); 12 u8 trrd = max(ns_to_t(10), 2); 13 u8 trcd = ns_to_t(20); 14 u8 trc = ns_to_t(65); 15 u8 txp = 2; 16 u8 twtr = max(ns_to_t(8), 2); 17 u8 trtp = max(ns_to_t(8), 2); 18 u8 twr = max(ns_to_t(15), 3); 19 u8 trp = ns_to_t(15); 20 u8 tras = ns_to_t(45); 21 u16 trefi = ns_to_t(7800) / 32; 22 u16 trfc = ns_to_t(328); 23 24 u8 tmrw = 0; 25 u8 tmrd = 2; 26 u8 tmod = 12; 27 u8 tcke = 3; 28 u8 tcksrx = 5; 29 u8 tcksre = 5; 30 u8 tckesr = 4; 31 u8 trasmax = 27; 32 33 u8 tcl = 3; /* CL 6 */ 34 u8 tcwl = 3; /* CWL 6 */ 35 u8 t_rdata_en = 1; 36 u8 wr_latency = 1; 37 38 u32 tdinit0 = (400 * CONFIG_DRAM_CLK) + 1; /* 400us */ 39 u32 tdinit1 = (500 * CONFIG_DRAM_CLK) / 1000 + 1; /* 500ns */ 40 u32 tdinit2 = (200 * CONFIG_DRAM_CLK) + 1; /* 200us */ 41 u32 tdinit3 = (1 * CONFIG_DRAM_CLK) + 1; /* 1us */ 42 43 u8 twtp = tcwl + 2 + twr; /* WL + BL / 2 + tWR */ 44 u8 twr2rd = tcwl + 2 + twtr; /* WL + BL / 2 + tWTR */ 45 u8 trd2wr = tcl + 2 + 1 - tcwl; /* RL + BL / 2 + 2 - WL */ 46 47 /* set mode register */ 48 writel(0x263, &mctl_ctl->mr[0]); 49 writel(0x4, &mctl_ctl->mr[1]); 50 writel(0x0, &mctl_ctl->mr[2]); 51 writel(0x0, &mctl_ctl->mr[3]); 52 53 /* set DRAM timing */ 54 writel(DRAMTMG0_TWTP(twtp) | DRAMTMG0_TFAW(tfaw) | 55 DRAMTMG0_TRAS_MAX(trasmax) | DRAMTMG0_TRAS(tras), 56 &mctl_ctl->dramtmg[0]); 57 writel(DRAMTMG1_TXP(txp) | DRAMTMG1_TRTP(trtp) | DRAMTMG1_TRC(trc), 58 &mctl_ctl->dramtmg[1]); 59 writel(DRAMTMG2_TCWL(tcwl) | DRAMTMG2_TCL(tcl) | 60 DRAMTMG2_TRD2WR(trd2wr) | DRAMTMG2_TWR2RD(twr2rd), 61 &mctl_ctl->dramtmg[2]); 62 writel(DRAMTMG3_TMRW(tmrw) | DRAMTMG3_TMRD(tmrd) | DRAMTMG3_TMOD(tmod), 63 &mctl_ctl->dramtmg[3]); 64 writel(DRAMTMG4_TRCD(trcd) | DRAMTMG4_TCCD(tccd) | DRAMTMG4_TRRD(trrd) | 65 DRAMTMG4_TRP(trp), &mctl_ctl->dramtmg[4]); 66 writel(DRAMTMG5_TCKSRX(tcksrx) | DRAMTMG5_TCKSRE(tcksre) | 67 DRAMTMG5_TCKESR(tckesr) | DRAMTMG5_TCKE(tcke), 68 &mctl_ctl->dramtmg[5]); 69 70 /* set two rank timing */ 71 clrsetbits_le32(&mctl_ctl->dramtmg[8], (0xff << 8) | (0xff << 0), 72 (0x66 << 8) | (0x10 << 0)); 73 74 /* set PHY interface timing, write latency and read latency configure */ 75 writel((0x2 << 24) | (t_rdata_en << 16) | (0x1 << 8) | 76 (wr_latency << 0), &mctl_ctl->pitmg[0]); 77 78 /* set PHY timing, PTR0-2 use default */ 79 writel(PTR3_TDINIT0(tdinit0) | PTR3_TDINIT1(tdinit1), &mctl_ctl->ptr[3]); 80 writel(PTR4_TDINIT2(tdinit2) | PTR4_TDINIT3(tdinit3), &mctl_ctl->ptr[4]); 81 82 /* set refresh timing */ 83 writel(RFSHTMG_TREFI(trefi) | RFSHTMG_TRFC(trfc), &mctl_ctl->rfshtmg); 84 } 85