1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3  * sun9i dram controller initialisation
4  *
5  * (C) Copyright 2007-2015
6  * Allwinner Technology Co., Ltd. <www.allwinnertech.com>
7  * Jerry Wang <wangflord@allwinnertech.com>
8  *
9  * (C) Copyright 2016 Theobroma Systems Design und Consulting GmbH
10  *                    Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
11  */
12 
13 #include <common.h>
14 #include <dm.h>
15 #include <errno.h>
16 #include <ram.h>
17 #include <asm/io.h>
18 #include <asm/arch/clock.h>
19 #include <asm/arch/dram.h>
20 #include <asm/arch/sys_proto.h>
21 
22 #define DRAM_CLK (CONFIG_DRAM_CLK * 1000000)
23 
24 /*
25  * The following amounts to an extensive rewrite of the code received from
26  * Allwinner as part of the open-source bootloader release (refer to
27  * https://github.com/allwinner-zh/bootloader.git) and augments the upstream
28  * sources (which act as the primary reference point for the inner workings
29  * of the 'underdocumented' DRAM controller in the A80) using the following
30  * documentation for other memory controllers based on the (Synopsys)
31  * Designware IP (DDR memory protocol controller and DDR PHY)
32  *   * TI Keystone II Architecture: DDR3 Memory Controller, User's Guide
33  *     Document 'SPRUHN7C', Oct 2013 (revised March 2015)
34  *   * Xilinx Zynq UltraScale+ MPSoC Register Reference
35  *     document ug1087 (v1.0)
36  * Note that the Zynq-documentation provides a very close match for the DDR
37  * memory protocol controller (and provides a very good guide to the rounding
38  * rules for various timings), whereas the TI Keystone II document should be
39  * referred to for DDR PHY specifics only.
40  *
41  * The DRAM controller in the A80 runs at half the frequency of the DDR PHY
42  * (i.e. the rules for MEMC_FREQ_RATIO=2 from the Zynq-documentation apply).
43  *
44  * Known limitations
45  * =================
46  * In the current state, the following features are not fully supported and
47  * a number of simplifying assumptions have been made:
48  *   1) Only DDR3 support is implemented, as our test platform (the A80-Q7
49  *      module) is designed to accomodate DDR3/DDR3L.
50  *   2) Only 2T-mode has been implemented and tested.
51  *   3) The controller supports two different clocking strategies (PLL6 can
52  *      either be 2*CK or CK/2)... we only support the 2*CK clock at this
53  *      time and haven't verified whether the alternative clocking strategy
54  *      works.  If you are interested in porting this over/testing this,
55  *      please refer to cases where bit 0 of 'dram_tpr8' is tested in the
56  *      original code from Allwinner.
57  *   4) Support for 2 ranks per controller is not implemented (as we don't
58  *      the hardware to test it).
59  *
60  * Future directions
61  * =================
62  * The driver should be driven from a device-tree based configuration that
63  * can dynamically provide the necessary timing parameters (i.e. target
64  * frequency and speed-bin information)---the data structures used in the
65  * calculation of the timing parameters are already designed to capture
66  * similar information as the device tree would provide.
67  *
68  * To enable a device-tree based configuration of the sun9i platform, we
69  * will need to enable CONFIG_TPL and bootstrap in 3 stages: initially
70  * into SRAM A1 (40KB) and next into SRAM A2 (160KB)---which would be the
71  * stage to initialise the platform via the device-tree---before having
72  * the full U-Boot run from DDR.
73  */
74 
75 /*
76  * A number of DDR3 timings are given as "the greater of a fixed number of
77  * clock cycles (CK) or nanoseconds.  We express these using a structure
78  * that holds a cycle count and a duration in picoseconds (so we can model
79  * sub-ns timings, such as 7.5ns without losing precision or resorting to
80  * rounding up early.
81  */
82 struct dram_sun9i_timing {
83 	u32 ck;
84 	u32 ps;
85 };
86 
87 /* */
88 struct dram_sun9i_cl_cwl_timing {
89 	u32 CL;
90 	u32 CWL;
91 	u32 tCKmin;  /* in ps */
92 	u32 tCKmax;  /* in ps */
93 };
94 
95 struct dram_sun9i_para {
96 	u32 dram_type;
97 
98 	u8 bus_width;
99 	u8 chan;
100 	u8 rank;
101 	u8 rows;
102 	u16 page_size;
103 
104 	/* Timing information for each speed-bin */
105 	struct dram_sun9i_cl_cwl_timing *cl_cwl_table;
106 	u32 cl_cwl_numentries;
107 
108 	/*
109 	 * For the timings, we try to keep the order and grouping used in
110 	 * JEDEC Standard No. 79-3F
111 	 */
112 
113 	/* timings */
114 	u32 tREFI; /* in ns */
115 	u32 tRFC;  /* in ns */
116 
117 	u32 tRAS;  /* in ps */
118 
119 	/* command and address timing */
120 	u32 tDLLK; /* in nCK */
121 	struct dram_sun9i_timing tRTP;
122 	struct dram_sun9i_timing tWTR;
123 	u32 tWR;   /* in nCK */
124 	u32 tMRD;  /* in nCK */
125 	struct dram_sun9i_timing tMOD;
126 	u32 tRCD;  /* in ps */
127 	u32 tRP;   /* in ps */
128 	u32 tRC;   /* in ps */
129 	u32 tCCD;  /* in nCK */
130 	struct dram_sun9i_timing tRRD;
131 	u32 tFAW;  /* in ps */
132 
133 	/* calibration timing */
134 	/* struct dram_sun9i_timing tZQinit; */
135 	struct dram_sun9i_timing tZQoper;
136 	struct dram_sun9i_timing tZQCS;
137 
138 	/* reset timing */
139 	/* struct dram_sun9i_timing tXPR; */
140 
141 	/* self-refresh timings */
142 	struct dram_sun9i_timing tXS;
143 	u32 tXSDLL; /* in nCK */
144 	/* struct dram_sun9i_timing tCKESR; */
145 	struct dram_sun9i_timing tCKSRE;
146 	struct dram_sun9i_timing tCKSRX;
147 
148 	/* power-down timings */
149 	struct dram_sun9i_timing tXP;
150 	struct dram_sun9i_timing tXPDLL;
151 	struct dram_sun9i_timing tCKE;
152 
153 	/* write leveling timings */
154 	u32 tWLMRD;    /* min, in nCK */
155 	/* u32 tWLDQSEN;  min, in nCK */
156 	u32 tWLO;      /* max, in ns */
157 	/* u32 tWLOE;     max, in ns */
158 
159 	/* u32 tCKDPX;    in nCK */
160 	/* u32 tCKCSX;    in nCK */
161 };
162 
163 static void mctl_sys_init(void);
164 
165 #define SCHED_RDWR_IDLE_GAP(n)            ((n & 0xff) << 24)
166 #define SCHED_GO2CRITICAL_HYSTERESIS(n)   ((n & 0xff) << 16)
167 #define SCHED_LPR_NUM_ENTRIES(n)          ((n & 0xff) <<  8)
168 #define SCHED_PAGECLOSE                   (1 << 2)
169 #define SCHED_PREFER_WRITE                (1 << 1)
170 #define SCHED_FORCE_LOW_PRI_N             (1 << 0)
171 
172 #define SCHED_CONFIG		(SCHED_RDWR_IDLE_GAP(0xf) | \
173 				 SCHED_GO2CRITICAL_HYSTERESIS(0x80) | \
174 				 SCHED_LPR_NUM_ENTRIES(0x20) | \
175 				 SCHED_FORCE_LOW_PRI_N)
176 #define PERFHPR0_CONFIG                   0x0000001f
177 #define PERFHPR1_CONFIG                   0x1f00001f
178 #define PERFLPR0_CONFIG                   0x000000ff
179 #define PERFLPR1_CONFIG                   0x0f0000ff
180 #define PERFWR0_CONFIG                    0x000000ff
181 #define PERFWR1_CONFIG                    0x0f0001ff
182 
183 static void mctl_ctl_sched_init(unsigned long  base)
184 {
185 	struct sunxi_mctl_ctl_reg *mctl_ctl =
186 		(struct sunxi_mctl_ctl_reg *)base;
187 
188 	/* Needs to be done before the global clk enable... */
189 	writel(SCHED_CONFIG, &mctl_ctl->sched);
190 	writel(PERFHPR0_CONFIG, &mctl_ctl->perfhpr0);
191 	writel(PERFHPR1_CONFIG, &mctl_ctl->perfhpr1);
192 	writel(PERFLPR0_CONFIG, &mctl_ctl->perflpr0);
193 	writel(PERFLPR1_CONFIG, &mctl_ctl->perflpr1);
194 	writel(PERFWR0_CONFIG, &mctl_ctl->perfwr0);
195 	writel(PERFWR1_CONFIG, &mctl_ctl->perfwr1);
196 }
197 
198 static void mctl_sys_init(void)
199 {
200 	struct sunxi_ccm_reg * const ccm =
201 		(struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
202 	struct sunxi_mctl_com_reg * const mctl_com =
203 		(struct sunxi_mctl_com_reg *)SUNXI_DRAM_COM_BASE;
204 
205 	debug("Setting PLL6 to %d\n", DRAM_CLK * 2);
206 	clock_set_pll6(DRAM_CLK * 2);
207 
208 	/* Original dram init code which may come in handy later
209 	********************************************************
210 	clock_set_pll6(use_2channelPLL ? (DRAM_CLK * 2) :
211 					 (DRAM_CLK / 2), false);
212 
213 	if ((para->dram_clk <= 400)|((para->dram_tpr8 & 0x1)==0)) {
214 		 * PLL6 should be 2*CK *
215 		 * ccm_setup_pll6_ddr_clk(PLL6_DDR_CLK); *
216 		ccm_setup_pll6_ddr_clk((1000000 * (para->dram_clk) * 2), 0);
217 	} else {
218 		 * PLL6 should be CK/2 *
219 		ccm_setup_pll6_ddr_clk((1000000 * (para->dram_clk) / 2), 1);
220 	}
221 
222 	if (para->dram_tpr13 & (0xf<<18)) {
223 		 *
224 		 * bit21:bit18=0001:pll swing 0.4
225 		 * bit21:bit18=0010:pll swing 0.3
226 		 * bit21:bit18=0100:pll swing 0.2
227 		 * bit21:bit18=1000:pll swing 0.1
228 		 *
229 		dram_dbg("DRAM fre extend open !\n");
230 		reg_val=mctl_read_w(CCM_PLL6_DDR_REG);
231 		reg_val&=(0x1<<16);
232 		reg_val=reg_val>>16;
233 
234 		if(para->dram_tpr13 & (0x1<<18))
235 		{
236 			mctl_write_w(CCM_PLL_BASE + 0x114,
237 				(0x3333U|(0x3<<17)|(reg_val<<19)|(0x120U<<20)|
238 				(0x2U<<29)|(0x1U<<31)));
239 		}
240 		else if(para->dram_tpr13 & (0x1<<19))
241 		{
242 			mctl_write_w(CCM_PLL_BASE + 0x114,
243 				(0x6666U|(0x3U<<17)|(reg_val<<19)|(0xD8U<<20)|
244 				(0x2U<<29)|(0x1U<<31)));
245 		}
246 		else if(para->dram_tpr13 & (0x1<<20))
247 		{
248 			mctl_write_w(CCM_PLL_BASE + 0x114,
249 				(0x9999U|(0x3U<<17)|(reg_val<<19)|(0x90U<<20)|
250 				(0x2U<<29)|(0x1U<<31)));
251 		}
252 		else if(para->dram_tpr13 & (0x1<<21))
253 		{
254 			mctl_write_w(CCM_PLL_BASE + 0x114,
255 				(0xccccU|(0x3U<<17)|(reg_val<<19)|(0x48U<<20)|
256 				(0x2U<<29)|(0x1U<<31)));
257 		}
258 
259 		//frequency extend open
260 		reg_val = mctl_read_w(CCM_PLL6_DDR_REG);
261 		reg_val |= ((0x1<<24)|(0x1<<30));
262 		mctl_write_w(CCM_PLL6_DDR_REG, reg_val);
263 
264 
265 		while(mctl_read_w(CCM_PLL6_DDR_REG) & (0x1<<30));
266 	}
267 
268 	aw_delay(0x20000);	//make some delay
269 	********************************************************
270 	*/
271 
272 	/* assert mctl reset */
273 	clrbits_le32(&ccm->ahb_reset0_cfg, 1 << AHB_RESET_OFFSET_MCTL);
274 	/* stop mctl clock */
275 	clrbits_le32(&ccm->ahb_gate0, 1 << AHB_GATE_OFFSET_MCTL);
276 
277 	sdelay(2000);
278 
279 	/* deassert mctl reset */
280 	setbits_le32(&ccm->ahb_reset0_cfg, 1 << AHB_RESET_OFFSET_MCTL);
281 	/* enable mctl clock */
282 	setbits_le32(&ccm->ahb_gate0, 1 << AHB_GATE_OFFSET_MCTL);
283 
284 	/* set up the transactions scheduling before enabling the global clk */
285 	mctl_ctl_sched_init(SUNXI_DRAM_CTL0_BASE);
286 	mctl_ctl_sched_init(SUNXI_DRAM_CTL1_BASE);
287 	sdelay(1000);
288 
289 	debug("2\n");
290 
291 	/* (3 << 12): PLL_DDR */
292 	writel((3 << 12) | (1 << 16), &ccm->dram_clk_cfg);
293 	do {
294 		debug("Waiting for DRAM_CLK_CFG\n");
295 		sdelay(10000);
296 	} while (readl(&ccm->dram_clk_cfg) & (1 << 16));
297 	setbits_le32(&ccm->dram_clk_cfg, (1 << 31));
298 
299 	/* TODO: we only support the common case ... i.e. 2*CK */
300 	setbits_le32(&mctl_com->ccr, (1 << 14) | (1 << 30));
301 	writel(2, &mctl_com->rmcr); /* controller clock is PLL6/4 */
302 
303 	sdelay(2000);
304 
305 	/* Original dram init code which may come in handy later
306 	********************************************************
307 	if ((para->dram_clk <= 400) | ((para->dram_tpr8 & 0x1) == 0)) {
308 		 * PLL6 should be 2*CK *
309 		 * gating 2 channel pll *
310 		reg_val = mctl_read_w(MC_CCR);
311 		reg_val |= ((0x1 << 14) | (0x1U << 30));
312 		mctl_write_w(MC_CCR, reg_val);
313 		mctl_write_w(MC_RMCR, 0x2); * controller clock use pll6/4 *
314 	} else {
315 		 * enable 2 channel pll *
316 		reg_val = mctl_read_w(MC_CCR);
317 		reg_val &= ~((0x1 << 14) | (0x1U << 30));
318 		mctl_write_w(MC_CCR, reg_val);
319 		mctl_write_w(MC_RMCR, 0x0); * controller clock use pll6 *
320 	}
321 
322 	reg_val = mctl_read_w(MC_CCR);
323 	reg_val &= ~((0x1<<15)|(0x1U<<31));
324 	mctl_write_w(MC_CCR, reg_val);
325 	aw_delay(20);
326 	//aw_delay(0x10);
327 	********************************************************
328 	*/
329 
330 	clrbits_le32(&mctl_com->ccr, MCTL_CCR_CH0_CLK_EN | MCTL_CCR_CH1_CLK_EN);
331 	sdelay(1000);
332 
333 	setbits_le32(&mctl_com->ccr, MCTL_CCR_CH0_CLK_EN);
334 	/* TODO if (para->chan == 2) */
335 	setbits_le32(&mctl_com->ccr, MCTL_CCR_CH1_CLK_EN);
336 }
337 
338 static void mctl_com_init(struct dram_sun9i_para *para)
339 {
340 	struct sunxi_mctl_com_reg * const mctl_com =
341 		(struct sunxi_mctl_com_reg *)SUNXI_DRAM_COM_BASE;
342 
343 	/* TODO: hard-wired for DDR3 now */
344 	writel(((para->chan == 2) ? MCTL_CR_CHANNEL_DUAL :
345 				    MCTL_CR_CHANNEL_SINGLE)
346 	       | MCTL_CR_DRAMTYPE_DDR3 | MCTL_CR_BANK(1)
347 	       | MCTL_CR_ROW(para->rows)
348 	       | ((para->bus_width == 32) ? MCTL_CR_BUSW32 : MCTL_CR_BUSW16)
349 	       | MCTL_CR_PAGE_SIZE(para->page_size) | MCTL_CR_RANK(para->rank),
350 	       &mctl_com->cr);
351 
352 	debug("CR: %d\n", readl(&mctl_com->cr));
353 }
354 
355 static u32 mctl_channel_init(u32 ch_index, struct dram_sun9i_para *para)
356 {
357 	struct sunxi_mctl_ctl_reg *mctl_ctl;
358 	struct sunxi_mctl_phy_reg *mctl_phy;
359 
360 	u32 CL = 0;
361 	u32 CWL = 0;
362 	u16 mr[4] = { 0, };
363 
364 #define PS2CYCLES_FLOOR(n)    ((n * CONFIG_DRAM_CLK) / 1000000)
365 #define PS2CYCLES_ROUNDUP(n)  ((n * CONFIG_DRAM_CLK + 999999) / 1000000)
366 #define NS2CYCLES_FLOOR(n)    ((n * CONFIG_DRAM_CLK) / 1000)
367 #define NS2CYCLES_ROUNDUP(n)  ((n * CONFIG_DRAM_CLK + 999) / 1000)
368 #define MAX(a, b)             ((a) > (b) ? (a) : (b))
369 
370 	/*
371 	 * Convert the values to cycle counts (nCK) from what is provided
372 	 * by the definition of each speed bin.
373 	 */
374 	/* const u32 tREFI = NS2CYCLES_FLOOR(para->tREFI); */
375 	const u32 tREFI = NS2CYCLES_FLOOR(para->tREFI);
376 	const u32 tRFC  = NS2CYCLES_ROUNDUP(para->tRFC);
377 	const u32 tRCD  = PS2CYCLES_ROUNDUP(para->tRCD);
378 	const u32 tRP   = PS2CYCLES_ROUNDUP(para->tRP);
379 	const u32 tRC   = PS2CYCLES_ROUNDUP(para->tRC);
380 	const u32 tRAS  = PS2CYCLES_ROUNDUP(para->tRAS);
381 
382 	/* command and address timing */
383 	const u32 tDLLK = para->tDLLK;
384 	const u32 tRTP  = MAX(para->tRTP.ck, PS2CYCLES_ROUNDUP(para->tRTP.ps));
385 	const u32 tWTR  = MAX(para->tWTR.ck, PS2CYCLES_ROUNDUP(para->tWTR.ps));
386 	const u32 tWR   = NS2CYCLES_FLOOR(para->tWR);
387 	const u32 tMRD  = para->tMRD;
388 	const u32 tMOD  = MAX(para->tMOD.ck, PS2CYCLES_ROUNDUP(para->tMOD.ps));
389 	const u32 tCCD  = para->tCCD;
390 	const u32 tRRD  = MAX(para->tRRD.ck, PS2CYCLES_ROUNDUP(para->tRRD.ps));
391 	const u32 tFAW  = PS2CYCLES_ROUNDUP(para->tFAW);
392 
393 	/* calibration timings */
394 	/* const u32 tZQinit = MAX(para->tZQinit.ck,
395 				PS2CYCLES_ROUNDUP(para->tZQinit.ps)); */
396 	const u32 tZQoper = MAX(para->tZQoper.ck,
397 				PS2CYCLES_ROUNDUP(para->tZQoper.ps));
398 	const u32 tZQCS   = MAX(para->tZQCS.ck,
399 				PS2CYCLES_ROUNDUP(para->tZQCS.ps));
400 
401 	/* reset timing */
402 	/* const u32 tXPR  = MAX(para->tXPR.ck,
403 				PS2CYCLES_ROUNDUP(para->tXPR.ps)); */
404 
405 	/* power-down timings */
406 	const u32 tXP    = MAX(para->tXP.ck, PS2CYCLES_ROUNDUP(para->tXP.ps));
407 	const u32 tXPDLL = MAX(para->tXPDLL.ck,
408 			       PS2CYCLES_ROUNDUP(para->tXPDLL.ps));
409 	const u32 tCKE   = MAX(para->tCKE.ck, PS2CYCLES_ROUNDUP(para->tCKE.ps));
410 
411 	/*
412 	 * self-refresh timings (keep below power-down timings, as tCKESR
413 	 * needs to be calculated based on the nCK value of tCKE)
414 	 */
415 	const u32 tXS    = MAX(para->tXS.ck, PS2CYCLES_ROUNDUP(para->tXS.ps));
416 	const u32 tXSDLL = para->tXSDLL;
417 	const u32 tCKSRE = MAX(para->tCKSRE.ck,
418 			       PS2CYCLES_ROUNDUP(para->tCKSRE.ps));
419 	const u32 tCKESR = tCKE + 1;
420 	const u32 tCKSRX = MAX(para->tCKSRX.ck,
421 			       PS2CYCLES_ROUNDUP(para->tCKSRX.ps));
422 
423 	/* write leveling timings */
424 	const u32 tWLMRD = para->tWLMRD;
425 	/* const u32 tWLDQSEN = para->tWLDQSEN; */
426 	const u32 tWLO = PS2CYCLES_FLOOR(para->tWLO);
427 	/* const u32 tWLOE = PS2CYCLES_FLOOR(para->tWLOE); */
428 
429 	const u32 tRASmax = tREFI * 9;
430 	int i;
431 
432 	for (i = 0; i < para->cl_cwl_numentries; ++i) {
433 		const u32 tCK = 1000000 / CONFIG_DRAM_CLK;
434 
435 		if ((para->cl_cwl_table[i].tCKmin <= tCK) &&
436 		    (tCK < para->cl_cwl_table[i].tCKmax)) {
437 			CL = para->cl_cwl_table[i].CL;
438 			CWL = para->cl_cwl_table[i].CWL;
439 
440 			debug("found CL/CWL: CL = %d, CWL = %d\n", CL, CWL);
441 			break;
442 		}
443 	}
444 
445 	if ((CL == 0) && (CWL == 0)) {
446 		printf("failed to find valid CL/CWL for operating point %d MHz\n",
447 		       CONFIG_DRAM_CLK);
448 		return 0;
449 	}
450 
451 	if (ch_index == 0) {
452 		mctl_ctl = (struct sunxi_mctl_ctl_reg *)SUNXI_DRAM_CTL0_BASE;
453 		mctl_phy = (struct sunxi_mctl_phy_reg *)SUNXI_DRAM_PHY0_BASE;
454 	} else {
455 		mctl_ctl = (struct sunxi_mctl_ctl_reg *)SUNXI_DRAM_CTL1_BASE;
456 		mctl_phy = (struct sunxi_mctl_phy_reg *)SUNXI_DRAM_PHY1_BASE;
457 	}
458 
459 	if (para->dram_type == DRAM_TYPE_DDR3) {
460 		mr[0] = DDR3_MR0_PPD_FAST_EXIT | DDR3_MR0_WR(tWR) |
461 			DDR3_MR0_CL(CL);
462 		mr[1] = DDR3_MR1_RTT120OHM;
463 		mr[2] = DDR3_MR2_TWL(CWL);
464 		mr[3] = 0;
465 
466 		/*
467 		 * DRAM3 initialisation requires holding CKE LOW for
468 		 * at least 500us prior to starting the initialisation
469 		 * sequence and at least 10ns after driving CKE HIGH
470 		 * before the initialisation sequence may be started).
471 		 *
472 		 * Refer to Micron document "TN-41-07: DDR3 Power-Up,
473 		 * Initialization, and Reset DDR3 Initialization
474 		 * Routine" for details).
475 		 */
476 		writel(MCTL_INIT0_POST_CKE_x1024(1) |
477 		       MCTL_INIT0_PRE_CKE_x1024(
478 			    (500 * CONFIG_DRAM_CLK + 1023) / 1024), /* 500us */
479 		       &mctl_ctl->init[0]);
480 		writel(MCTL_INIT1_DRAM_RSTN_x1024(1),
481 		       &mctl_ctl->init[1]);
482 		/* INIT2 is not used for DDR3 */
483 		writel(MCTL_INIT3_MR(mr[0]) | MCTL_INIT3_EMR(mr[1]),
484 		       &mctl_ctl->init[3]);
485 		writel(MCTL_INIT4_EMR2(mr[2]) | MCTL_INIT4_EMR3(mr[3]),
486 		       &mctl_ctl->init[4]);
487 		writel(MCTL_INIT5_DEV_ZQINIT_x32(512 / 32), /* 512 cycles */
488 		       &mctl_ctl->init[5]);
489 	} else {
490 		/* !!! UNTESTED !!! */
491 		/*
492 		 * LPDDR2 and/or LPDDR3 require a 200us minimum delay
493 		 * after driving CKE HIGH in the initialisation sequence.
494 		 */
495 		writel(MCTL_INIT0_POST_CKE_x1024(
496 				(200 * CONFIG_DRAM_CLK + 1023) / 1024),
497 		       &mctl_ctl->init[0]);
498 		writel(MCTL_INIT1_DRAM_RSTN_x1024(1),
499 		       &mctl_ctl->init[1]);
500 		writel(MCTL_INIT2_IDLE_AFTER_RESET_x32(
501 				(CONFIG_DRAM_CLK + 31) / 32) /* 1us */
502 		       | MCTL_INIT2_MIN_STABLE_CLOCK_x1(5),  /* 5 cycles */
503 		       &mctl_ctl->init[2]);
504 		writel(MCTL_INIT3_MR(mr[1]) | MCTL_INIT3_EMR(mr[2]),
505 		       &mctl_ctl->init[3]);
506 		writel(MCTL_INIT4_EMR2(mr[3]),
507 		       &mctl_ctl->init[4]);
508 		writel(MCTL_INIT5_DEV_ZQINIT_x32(
509 				(CONFIG_DRAM_CLK + 31) / 32) /* 1us */
510 		       | MCTL_INIT5_MAX_AUTO_INIT_x1024(
511 				(10 * CONFIG_DRAM_CLK + 1023) / 1024),
512 		       &mctl_ctl->init[5]);
513 	}
514 
515 	/* (DDR3) We always use a burst-length of 8. */
516 #define MCTL_BL               8
517 	/* wr2pre: WL + BL/2 + tWR */
518 #define WR2PRE           (MCTL_BL/2 + CWL + tWTR)
519 	/* wr2rd = CWL + BL/2 + tWTR */
520 #define WR2RD            (MCTL_BL/2 + CWL + tWTR)
521 	/*
522 	 * rd2wr = RL + BL/2 + 2 - WL (for DDR3)
523 	 * rd2wr = RL + BL/2 + RU(tDQSCKmax/tCK) + 1 - WL (for LPDDR2/LPDDR3)
524 	 */
525 #define RD2WR            (CL + MCTL_BL/2 + 2 - CWL)
526 #define MCTL_PHY_TRTW        0
527 #define MCTL_PHY_TRTODT      0
528 
529 #define MCTL_DIV2(n)         ((n + 1)/2)
530 #define MCTL_DIV32(n)        (n/32)
531 #define MCTL_DIV1024(n)      (n/1024)
532 
533 	writel((MCTL_DIV2(WR2PRE) << 24) | (MCTL_DIV2(tFAW) << 16) |
534 	       (MCTL_DIV1024(tRASmax) << 8) | (MCTL_DIV2(tRAS) << 0),
535 	       &mctl_ctl->dramtmg[0]);
536 	writel((MCTL_DIV2(tXP) << 16) | (MCTL_DIV2(tRTP) << 8) |
537 	       (MCTL_DIV2(tRC) << 0),
538 	       &mctl_ctl->dramtmg[1]);
539 	writel((MCTL_DIV2(CWL) << 24) | (MCTL_DIV2(CL) << 16) |
540 	       (MCTL_DIV2(RD2WR) << 8) | (MCTL_DIV2(WR2RD) << 0),
541 	       &mctl_ctl->dramtmg[2]);
542 	/*
543 	 * Note: tMRW is located at bit 16 (and up) in DRAMTMG3...
544 	 * this is only relevant for LPDDR2/LPDDR3
545 	 */
546 	writel((MCTL_DIV2(tMRD) << 12) | (MCTL_DIV2(tMOD) << 0),
547 	       &mctl_ctl->dramtmg[3]);
548 	writel((MCTL_DIV2(tRCD) << 24) | (MCTL_DIV2(tCCD) << 16) |
549 	       (MCTL_DIV2(tRRD) << 8) | (MCTL_DIV2(tRP) << 0),
550 	       &mctl_ctl->dramtmg[4]);
551 	writel((MCTL_DIV2(tCKSRX) << 24) | (MCTL_DIV2(tCKSRE) << 16) |
552 	       (MCTL_DIV2(tCKESR) << 8) | (MCTL_DIV2(tCKE) << 0),
553 	       &mctl_ctl->dramtmg[5]);
554 
555 	/* These timings are relevant for LPDDR2/LPDDR3 only */
556 	/* writel((MCTL_TCKDPDE << 24) | (MCTL_TCKDPX << 16) |
557 	       (MCTL_TCKCSX << 0), &mctl_ctl->dramtmg[6]); */
558 
559 	/* printf("DRAMTMG7 reset value: 0x%x\n",
560 		readl(&mctl_ctl->dramtmg[7])); */
561 	/* DRAMTMG7 reset value: 0x202 */
562 	/* DRAMTMG7 should contain t_ckpde and t_ckpdx: check reset values!!! */
563 	/* printf("DRAMTMG8 reset value: 0x%x\n",
564 		readl(&mctl_ctl->dramtmg[8])); */
565 	/* DRAMTMG8 reset value: 0x44 */
566 
567 	writel((MCTL_DIV32(tXSDLL) << 0), &mctl_ctl->dramtmg[8]);
568 
569 	writel((MCTL_DIV32(tREFI) << 16) | (MCTL_DIV2(tRFC) << 0),
570 	       &mctl_ctl->rfshtmg);
571 
572 	if (para->dram_type == DRAM_TYPE_DDR3) {
573 		writel((2 << 24) | ((MCTL_DIV2(CL) - 2) << 16) |
574 		       (1 << 8) | ((MCTL_DIV2(CWL) - 2) << 0),
575 			&mctl_ctl->dfitmg[0]);
576 	} else {
577 		/* TODO */
578 	}
579 
580 	/* TODO: handle the case of the write latency domain going to 0 ... */
581 
582 	/*
583 	 * Disable dfi_init_complete_en (the triggering of the SDRAM
584 	 * initialisation when the PHY initialisation completes).
585 	 */
586 	clrbits_le32(&mctl_ctl->dfimisc, MCTL_DFIMISC_DFI_INIT_COMPLETE_EN);
587 	/* Disable the automatic generation of DLL calibration requests */
588 	setbits_le32(&mctl_ctl->dfiupd[0], MCTL_DFIUPD0_DIS_AUTO_CTRLUPD);
589 
590 	/* A80-Q7: 2T, 1 rank, DDR3, full-32bit-DQ */
591 	/* TODO: make 2T and BUSWIDTH configurable  */
592 	writel(MCTL_MSTR_DEVICETYPE(para->dram_type) |
593 	       MCTL_MSTR_BURSTLENGTH(para->dram_type) |
594 	       MCTL_MSTR_ACTIVERANKS(para->rank) |
595 	       MCTL_MSTR_2TMODE | MCTL_MSTR_BUSWIDTH32,
596 	       &mctl_ctl->mstr);
597 
598 	if (para->dram_type == DRAM_TYPE_DDR3) {
599 		writel(MCTL_ZQCTRL0_TZQCL(MCTL_DIV2(tZQoper)) |
600 		       (MCTL_DIV2(tZQCS)), &mctl_ctl->zqctrl[0]);
601 		/*
602 		 * TODO: is the following really necessary as the bottom
603 		 * half should already be 0x100 and the upper half should
604 		 * be ignored for a DDR3 device???
605 		 */
606 		writel(MCTL_ZQCTRL1_TZQSI_x1024(0x100),
607 		       &mctl_ctl->zqctrl[1]);
608 	} else {
609 		writel(MCTL_ZQCTRL0_TZQCL(0x200) | MCTL_ZQCTRL0_TZQCS(0x40),
610 		       &mctl_ctl->zqctrl[0]);
611 		writel(MCTL_ZQCTRL1_TZQRESET(0x28) |
612 		       MCTL_ZQCTRL1_TZQSI_x1024(0x100),
613 		       &mctl_ctl->zqctrl[1]);
614 	}
615 
616 	/* Assert dfi_init_complete signal */
617 	setbits_le32(&mctl_ctl->dfimisc, MCTL_DFIMISC_DFI_INIT_COMPLETE_EN);
618 	/* Disable auto-refresh */
619 	setbits_le32(&mctl_ctl->rfshctl3, MCTL_RFSHCTL3_DIS_AUTO_REFRESH);
620 
621 	/* PHY initialisation */
622 
623 	/* TODO: make 2T and 8-bank mode configurable  */
624 	writel(MCTL_PHY_DCR_BYTEMASK | MCTL_PHY_DCR_2TMODE |
625 	       MCTL_PHY_DCR_DDR8BNK | MCTL_PHY_DRAMMODE_DDR3,
626 	       &mctl_phy->dcr);
627 
628 	/* For LPDDR2 or LPDDR3, set DQSGX to 0 before training. */
629 	if (para->dram_type != DRAM_TYPE_DDR3)
630 		clrbits_le32(&mctl_phy->dsgcr, (3 << 6));
631 
632 	writel(mr[0], &mctl_phy->mr0);
633 	writel(mr[1], &mctl_phy->mr1);
634 	writel(mr[2], &mctl_phy->mr2);
635 	writel(mr[3], &mctl_phy->mr3);
636 
637 	/*
638 	 * The DFI PHY is running at full rate. We thus use the actual
639 	 * timings in clock cycles here.
640 	 */
641 	writel((tRC << 26) | (tRRD << 22) | (tRAS << 16) |
642 	       (tRCD << 12) | (tRP << 8) | (tWTR << 4) | (tRTP << 0),
643 		&mctl_phy->dtpr[0]);
644 	writel((tMRD << 0) | ((tMOD - 12) << 2) | (tFAW << 5) |
645 	       (tRFC << 11) | (tWLMRD << 20) | (tWLO << 26),
646 	       &mctl_phy->dtpr[1]);
647 	writel((tXS << 0) | (MAX(tXP, tXPDLL) << 10) |
648 	       (tCKE << 15) | (tDLLK << 19) |
649 	       (MCTL_PHY_TRTODT << 29) | (MCTL_PHY_TRTW << 30) |
650 	       (((tCCD - 4) & 0x1) << 31),
651 	       &mctl_phy->dtpr[2]);
652 
653 	/* tDQSCK and tDQSCKmax are used LPDDR2/LPDDR3 */
654 	/* writel((tDQSCK << 0) | (tDQSCKMAX << 3), &mctl_phy->dtpr[3]); */
655 
656 	/*
657 	 * We use the same values used by Allwinner's Boot0 for the PTR
658 	 * (PHY timing register) configuration that is tied to the PHY
659 	 * implementation.
660 	 */
661 	writel(0x42C21590, &mctl_phy->ptr[0]);
662 	writel(0xD05612C0, &mctl_phy->ptr[1]);
663 	if (para->dram_type == DRAM_TYPE_DDR3) {
664 		const unsigned int tdinit0 = 500 * CONFIG_DRAM_CLK; /* 500us */
665 		const unsigned int tdinit1 = (360 * CONFIG_DRAM_CLK + 999) /
666 			1000; /* 360ns */
667 		const unsigned int tdinit2 = 200 * CONFIG_DRAM_CLK; /* 200us */
668 		const unsigned int tdinit3 = CONFIG_DRAM_CLK; /* 1us */
669 
670 		writel((tdinit1 << 20) | tdinit0, &mctl_phy->ptr[3]);
671 		writel((tdinit3 << 18) | tdinit2, &mctl_phy->ptr[4]);
672 	} else {
673 		/* LPDDR2 or LPDDR3 */
674 		const unsigned int tdinit0 = (100 * CONFIG_DRAM_CLK + 999) /
675 			1000; /* 100ns */
676 		const unsigned int tdinit1 = 200 * CONFIG_DRAM_CLK; /* 200us */
677 		const unsigned int tdinit2 = 22 * CONFIG_DRAM_CLK; /* 11us */
678 		const unsigned int tdinit3 = 2 * CONFIG_DRAM_CLK; /* 2us */
679 
680 		writel((tdinit1 << 20) | tdinit0, &mctl_phy->ptr[3]);
681 		writel((tdinit3 << 18) | tdinit2, &mctl_phy->ptr[4]);
682 	}
683 
684 	/* TEST ME */
685 	writel(0x00203131, &mctl_phy->acmdlr);
686 
687 	/* TODO: can we enable this for 2 ranks, even when we don't know yet */
688 	writel(MCTL_DTCR_DEFAULT | MCTL_DTCR_RANKEN(para->rank),
689 	       &mctl_phy->dtcr);
690 
691 	/* TODO: half width */
692 	debug("DX2GCR0 reset: 0x%x\n", readl(&mctl_phy->dx[2].gcr[0]));
693 	writel(0x7C000285, &mctl_phy->dx[2].gcr[0]);
694 	writel(0x7C000285, &mctl_phy->dx[3].gcr[0]);
695 
696 	clrsetbits_le32(&mctl_phy->zq[0].pr, 0xff,
697 			(CONFIG_DRAM_ZQ >>  0) & 0xff);  /* CK/CA */
698 	clrsetbits_le32(&mctl_phy->zq[1].pr, 0xff,
699 			(CONFIG_DRAM_ZQ >>  8) & 0xff);  /* DX0/DX1 */
700 	clrsetbits_le32(&mctl_phy->zq[2].pr, 0xff,
701 			(CONFIG_DRAM_ZQ >> 16) & 0xff);  /* DX2/DX3 */
702 
703 	/* TODO: make configurable & implement non-ODT path */
704 	if (1) {
705 		int lane;
706 		for (lane = 0; lane < 4; ++lane) {
707 			clrbits_le32(&mctl_phy->dx[lane].gcr[2], 0xffff);
708 			clrbits_le32(&mctl_phy->dx[lane].gcr[3],
709 				     (0x3<<12) | (0x3<<4));
710 		}
711 	} else {
712 		/* TODO: check */
713 		int lane;
714 		for (lane = 0; lane < 4; ++lane) {
715 			clrsetbits_le32(&mctl_phy->dx[lane].gcr[2], 0xffff,
716 					0xaaaa);
717 			if (para->dram_type == DRAM_TYPE_DDR3)
718 				setbits_le32(&mctl_phy->dx[lane].gcr[3],
719 					     (0x3<<12) | (0x3<<4));
720 			else
721 				setbits_le32(&mctl_phy->dx[lane].gcr[3],
722 					     0x00000012);
723 		}
724 	}
725 
726 	writel(0x04058D02, &mctl_phy->zq[0].cr); /* CK/CA */
727 	writel(0x04058D02, &mctl_phy->zq[1].cr); /* DX0/DX1 */
728 	writel(0x04058D02, &mctl_phy->zq[2].cr); /* DX2/DX3 */
729 
730 	/* Disable auto-refresh prior to data training */
731 	setbits_le32(&mctl_ctl->rfshctl3, MCTL_RFSHCTL3_DIS_AUTO_REFRESH);
732 
733 	setbits_le32(&mctl_phy->dsgcr, 0xf << 24); /* unclear what this is... */
734 	/* TODO: IODDRM (IO DDR-MODE) for DDR3L */
735 	clrsetbits_le32(&mctl_phy->pgcr[1],
736 			MCTL_PGCR1_ZCKSEL_MASK,
737 			MCTL_PGCR1_IODDRM_DDR3 | MCTL_PGCR1_INHVT_EN);
738 
739 	setbits_le32(&mctl_phy->pllcr, 0x3 << 19); /* PLL frequency select */
740 	/* TODO: single-channel PLL mode??? missing */
741 	setbits_le32(&mctl_phy->pllcr,
742 		     MCTL_PLLGCR_PLL_BYPASS | MCTL_PLLGCR_PLL_POWERDOWN);
743 	/* setbits_le32(&mctl_phy->pir, MCTL_PIR_PLL_BYPASS); included below */
744 
745 	/* Disable VT compensation */
746 	clrbits_le32(&mctl_phy->pgcr[0], 0x3f);
747 
748 	/* TODO: "other" PLL mode ... 0x20000 seems to be the PLL Bypass */
749 	if (para->dram_type == DRAM_TYPE_DDR3)
750 		clrsetbits_le32(&mctl_phy->pir, MCTL_PIR_MASK, 0x20df3);
751 	else
752 		clrsetbits_le32(&mctl_phy->pir, MCTL_PIR_MASK, 0x2c573);
753 
754 	sdelay(10000); /* XXX necessary? */
755 
756 	/* Wait for the INIT bit to clear itself... */
757 	while ((readl(&mctl_phy->pir) & MCTL_PIR_INIT) != MCTL_PIR_INIT) {
758 		/* not done yet -- keep spinning */
759 		debug("MCTL_PIR_INIT not set\n");
760 		sdelay(1000);
761 		/* TODO: implement timeout */
762 	}
763 
764 	/* TODO: not used --- there's a "2rank debug" section here */
765 
766 	/* Original dram init code which may come in handy later
767 	********************************************************
768 	 * LPDDR2 and LPDDR3 *
769 	if ((para->dram_type) == 6 || (para->dram_type) == 7) {
770 		reg_val = mctl_read_w(P0_DSGCR + ch_offset);
771 		reg_val &= (~(0x3<<6));		* set DQSGX to 1 *
772 		reg_val |= (0x1<<6);		* dqs gate extend *
773 		mctl_write_w(P0_DSGCR + ch_offset, reg_val);
774 		dram_dbg("DQS Gate Extend Enable!\n", ch_index);
775 	}
776 
777 	 * Disable ZCAL after initial--for nand dma debug--20140330 by YSZ *
778 	if (para->dram_tpr13 & (0x1<<31)) {
779 		reg_val = mctl_read_w(P0_ZQ0CR + ch_offset);
780 		reg_val |= (0x7<<11);
781 		mctl_write_w(P0_ZQ0CR + ch_offset, reg_val);
782 	}
783 	********************************************************
784 	*/
785 
786 	/*
787 	 * TODO: more 2-rank support
788 	 * (setting the "dqs gate delay to average between 2 rank")
789 	 */
790 
791 	/* check if any errors are set */
792 	if (readl(&mctl_phy->pgsr[0]) & MCTL_PGSR0_ERRORS) {
793 		debug("Channel %d unavailable!\n", ch_index);
794 		return 0;
795 	} else{
796 		/* initial OK */
797 		debug("Channel %d OK!\n", ch_index);
798 		/* return 1; */
799 	}
800 
801 	while ((readl(&mctl_ctl->stat) & 0x1) != 0x1) {
802 		debug("Waiting for INIT to be done (controller to come up into 'normal operating' mode\n");
803 		sdelay(100000);
804 		/* init not done */
805 		/* TODO: implement time-out */
806 	}
807 	debug("done\n");
808 
809 	/* "DDR is controller by contoller" */
810 	clrbits_le32(&mctl_phy->pgcr[3], (1 << 25));
811 
812 	/* TODO: is the following necessary? */
813 	debug("DFIMISC before writing 0: 0x%x\n", readl(&mctl_ctl->dfimisc));
814 	writel(0, &mctl_ctl->dfimisc);
815 
816 	/* Enable auto-refresh */
817 	clrbits_le32(&mctl_ctl->rfshctl3, MCTL_RFSHCTL3_DIS_AUTO_REFRESH);
818 
819 	debug("channel_init complete\n");
820 	return 1;
821 }
822 
823 signed int DRAMC_get_dram_size(void)
824 {
825 	struct sunxi_mctl_com_reg * const mctl_com =
826 		(struct sunxi_mctl_com_reg *)SUNXI_DRAM_COM_BASE;
827 
828 	unsigned int reg_val;
829 	unsigned int dram_size;
830 	unsigned int temp;
831 
832 	reg_val = readl(&mctl_com->cr);
833 
834 	temp = (reg_val >> 8) & 0xf;	/* page size code */
835 	dram_size = (temp - 6);		/* (1 << dram_size) * 512Bytes */
836 
837 	temp = (reg_val >> 4) & 0xf;	/* row width code */
838 	dram_size += (temp + 1);	/* (1 << dram_size) * 512Bytes */
839 
840 	temp = (reg_val >> 2) & 0x3;	/* bank number code */
841 	dram_size += (temp + 2);	/* (1 << dram_size) * 512Bytes */
842 
843 	temp = reg_val & 0x3;		/* rank number code */
844 	dram_size += temp;		/* (1 << dram_size) * 512Bytes */
845 
846 	temp = (reg_val >> 19) & 0x1;	/* channel number code */
847 	dram_size += temp;		/* (1 << dram_size) * 512Bytes */
848 
849 	dram_size = dram_size - 11;	/* (1 << dram_size) MBytes */
850 
851 	return 1 << dram_size;
852 }
853 
854 unsigned long sunxi_dram_init(void)
855 {
856 	struct sunxi_mctl_com_reg * const mctl_com =
857 		(struct sunxi_mctl_com_reg *)SUNXI_DRAM_COM_BASE;
858 
859 	struct dram_sun9i_cl_cwl_timing cl_cwl[] = {
860 		{ .CL =  5, .CWL = 5, .tCKmin = 3000, .tCKmax = 3300 },
861 		{ .CL =  6, .CWL = 5, .tCKmin = 2500, .tCKmax = 3300 },
862 		{ .CL =  8, .CWL = 6, .tCKmin = 1875, .tCKmax = 2500 },
863 		{ .CL = 10, .CWL = 7, .tCKmin = 1500, .tCKmax = 1875 },
864 		{ .CL = 11, .CWL = 8, .tCKmin = 1250, .tCKmax = 1500 }
865 	};
866 
867 	/* Set initial parameters, these get modified by the autodetect code */
868 	struct dram_sun9i_para para = {
869 		.dram_type = DRAM_TYPE_DDR3,
870 		.bus_width = 32,
871 		.chan = 2,
872 		.rank = 1,
873 		/* .rank = 2, */
874 		.page_size = 4096,
875 		/* .rows = 16, */
876 		.rows = 15,
877 
878 		/* CL/CWL table for the speed bin */
879 		.cl_cwl_table = cl_cwl,
880 		.cl_cwl_numentries = sizeof(cl_cwl) /
881 			sizeof(struct dram_sun9i_cl_cwl_timing),
882 
883 		/* timings */
884 		.tREFI = 7800,	/* 7.8us (up to 85 degC) */
885 		.tRFC  = 260,	/* 260ns for 4GBit devices */
886 				/* 350ns @ 8GBit */
887 
888 		.tRCD  = 13750,
889 		.tRP   = 13750,
890 		.tRC   = 48750,
891 		.tRAS  = 35000,
892 
893 		.tDLLK = 512,
894 		.tRTP  = { .ck = 4, .ps = 7500 },
895 		.tWTR  = { .ck = 4, .ps = 7500 },
896 		.tWR   = 15,
897 		.tMRD  = 4,
898 		.tMOD  = { .ck = 12, .ps = 15000 },
899 		.tCCD  = 4,
900 		.tRRD  = { .ck = 4, .ps = 7500 },
901 		.tFAW  = 40,
902 
903 		/* calibration timing */
904 		/* .tZQinit = { .ck = 512, .ps = 640000 }, */
905 		.tZQoper = { .ck = 256, .ps = 320000 },
906 		.tZQCS   = { .ck = 64,  .ps = 80000 },
907 
908 		/* reset timing */
909 		/* .tXPR  = { .ck = 5, .ps = 10000 }, */
910 
911 		/* self-refresh timings */
912 		.tXS  = { .ck = 5, .ps = 10000 },
913 		.tXSDLL = 512,
914 		.tCKSRE = { .ck = 5, .ps = 10000 },
915 		.tCKSRX = { .ck = 5, .ps = 10000 },
916 
917 		/* power-down timings */
918 		.tXP = { .ck = 3, .ps = 6000 },
919 		.tXPDLL = { .ck = 10, .ps = 24000 },
920 		.tCKE = { .ck = 3, .ps = 5000 },
921 
922 		/* write leveling timings */
923 		.tWLMRD = 40,
924 		/* .tWLDQSEN = 25, */
925 		.tWLO = 7500,
926 		/* .tWLOE = 2000, */
927 	};
928 
929 	/*
930 	 * Disable A80 internal 240 ohm resistor.
931 	 *
932 	 * This code sequence is adapated from Allwinner's Boot0 (see
933 	 * https://github.com/allwinner-zh/bootloader.git), as there
934 	 * is no documentation for these two registers in the R_PRCM
935 	 * block.
936 	 */
937 	setbits_le32(SUNXI_PRCM_BASE + 0x1e0, (0x3 << 8));
938 	writel(0, SUNXI_PRCM_BASE + 0x1e8);
939 
940 	mctl_sys_init();
941 
942 	if (!mctl_channel_init(0, &para))
943 		return 0;
944 
945 	/* dual-channel */
946 	if (!mctl_channel_init(1, &para)) {
947 		/* disable channel 1 */
948 		clrsetbits_le32(&mctl_com->cr, MCTL_CR_CHANNEL_MASK,
949 				MCTL_CR_CHANNEL_SINGLE);
950 		/* disable channel 1 global clock */
951 		clrbits_le32(&mctl_com->cr, MCTL_CCR_CH1_CLK_EN);
952 	}
953 
954 	mctl_com_init(&para);
955 
956 	/* return the proper RAM size */
957 	return DRAMC_get_dram_size() << 20;
958 }
959