1 /* 2 * Sun8i a33 platform dram controller init. 3 * 4 * (C) Copyright 2007-2015 Allwinner Technology Co. 5 * Jerry Wang <wangflord@allwinnertech.com> 6 * (C) Copyright 2015 Vishnu Patekar <vishnupatekar0510@gmail.com> 7 * (C) Copyright 2015 Hans de Goede <hdegoede@redhat.com> 8 * 9 * SPDX-License-Identifier: GPL-2.0+ 10 */ 11 #include <common.h> 12 #include <errno.h> 13 #include <asm/io.h> 14 #include <asm/arch/clock.h> 15 #include <asm/arch/dram.h> 16 #include <asm/arch/prcm.h> 17 18 /* PLL runs at 2x dram-clk, controller runs at PLL / 4 (dram-clk / 2) */ 19 #define DRAM_CLK_MUL 2 20 #define DRAM_CLK_DIV 4 21 #define DRAM_SIGMA_DELTA_ENABLE 1 22 23 struct dram_para { 24 u8 cs1; 25 u8 seq; 26 u8 bank; 27 u8 rank; 28 u8 rows; 29 u8 bus_width; 30 u16 page_size; 31 }; 32 33 static void mctl_set_cr(struct dram_para *para) 34 { 35 struct sunxi_mctl_com_reg * const mctl_com = 36 (struct sunxi_mctl_com_reg *)SUNXI_DRAM_COM_BASE; 37 38 writel(MCTL_CR_CS1_CONTROL(para->cs1) | MCTL_CR_UNKNOWN | 39 MCTL_CR_CHANNEL(1) | MCTL_CR_DDR3 | 40 (para->seq ? MCTL_CR_SEQUENCE : 0) | 41 ((para->bus_width == 16) ? MCTL_CR_BUSW16 : MCTL_CR_BUSW8) | 42 MCTL_CR_PAGE_SIZE(para->page_size) | MCTL_CR_ROW(para->rows) | 43 MCTL_CR_BANK(para->bank) | MCTL_CR_RANK(para->rank), 44 &mctl_com->cr); 45 } 46 47 static void auto_detect_dram_size(struct dram_para *para) 48 { 49 u8 orig_rank = para->rank; 50 int rows, columns; 51 52 /* Row detect */ 53 para->page_size = 512; 54 para->seq = 1; 55 para->rows = 16; 56 para->rank = 1; 57 mctl_set_cr(para); 58 for (rows = 11 ; rows < 16 ; rows++) { 59 if (mctl_mem_matches(1 << (rows + 9))) /* row-column */ 60 break; 61 } 62 63 /* Column (page size) detect */ 64 para->rows = 11; 65 para->page_size = 8192; 66 mctl_set_cr(para); 67 for (columns = 9 ; columns < 13 ; columns++) { 68 if (mctl_mem_matches(1 << columns)) 69 break; 70 } 71 72 para->seq = 0; 73 para->rank = orig_rank; 74 para->rows = rows; 75 para->page_size = 1 << columns; 76 mctl_set_cr(para); 77 } 78 79 static inline int ns_to_t(int nanoseconds) 80 { 81 const unsigned int ctrl_freq = 82 CONFIG_DRAM_CLK * DRAM_CLK_MUL / DRAM_CLK_DIV; 83 84 return (ctrl_freq * nanoseconds + 999) / 1000; 85 } 86 87 static void auto_set_timing_para(struct dram_para *para) 88 { 89 struct sunxi_mctl_ctl_reg * const mctl_ctl = 90 (struct sunxi_mctl_ctl_reg *)SUNXI_DRAM_CTL0_BASE; 91 u32 reg_val; 92 93 u8 tccd = 2; 94 u8 tfaw = ns_to_t(50); 95 u8 trrd = max(ns_to_t(10), 4); 96 u8 trcd = ns_to_t(15); 97 u8 trc = ns_to_t(53); 98 u8 txp = max(ns_to_t(8), 3); 99 u8 twtr = max(ns_to_t(8), 4); 100 u8 trtp = max(ns_to_t(8), 4); 101 u8 twr = max(ns_to_t(15), 3); 102 u8 trp = ns_to_t(15); 103 u8 tras = ns_to_t(38); 104 105 u16 trefi = ns_to_t(7800) / 32; 106 u16 trfc = ns_to_t(350); 107 108 /* Fixed timing parameters */ 109 u8 tmrw = 0; 110 u8 tmrd = 4; 111 u8 tmod = 12; 112 u8 tcke = 3; 113 u8 tcksrx = 5; 114 u8 tcksre = 5; 115 u8 tckesr = 4; 116 u8 trasmax = 24; 117 u8 tcl = 6; /* CL 12 */ 118 u8 tcwl = 4; /* CWL 8 */ 119 u8 t_rdata_en = 4; 120 u8 wr_latency = 2; 121 122 u32 tdinit0 = (500 * CONFIG_DRAM_CLK) + 1; /* 500us */ 123 u32 tdinit1 = (360 * CONFIG_DRAM_CLK) / 1000 + 1; /* 360ns */ 124 u32 tdinit2 = (200 * CONFIG_DRAM_CLK) + 1; /* 200us */ 125 u32 tdinit3 = (1 * CONFIG_DRAM_CLK) + 1; /* 1us */ 126 127 u8 twtp = tcwl + 2 + twr; /* WL + BL / 2 + tWR */ 128 u8 twr2rd = tcwl + 2 + twtr; /* WL + BL / 2 + tWTR */ 129 u8 trd2wr = tcl + 2 + 1 - tcwl; /* RL + BL / 2 + 2 - WL */ 130 131 /* Set work mode register */ 132 mctl_set_cr(para); 133 /* Set mode register */ 134 writel(MCTL_MR0, &mctl_ctl->mr0); 135 writel(MCTL_MR1, &mctl_ctl->mr1); 136 writel(MCTL_MR2, &mctl_ctl->mr2); 137 writel(MCTL_MR3, &mctl_ctl->mr3); 138 /* Set dram timing */ 139 reg_val = (twtp << 24) | (tfaw << 16) | (trasmax << 8) | (tras << 0); 140 writel(reg_val, &mctl_ctl->dramtmg0); 141 reg_val = (txp << 16) | (trtp << 8) | (trc << 0); 142 writel(reg_val, &mctl_ctl->dramtmg1); 143 reg_val = (tcwl << 24) | (tcl << 16) | (trd2wr << 8) | (twr2rd << 0); 144 writel(reg_val, &mctl_ctl->dramtmg2); 145 reg_val = (tmrw << 16) | (tmrd << 12) | (tmod << 0); 146 writel(reg_val, &mctl_ctl->dramtmg3); 147 reg_val = (trcd << 24) | (tccd << 16) | (trrd << 8) | (trp << 0); 148 writel(reg_val, &mctl_ctl->dramtmg4); 149 reg_val = (tcksrx << 24) | (tcksre << 16) | (tckesr << 8) | (tcke << 0); 150 writel(reg_val, &mctl_ctl->dramtmg5); 151 /* Set two rank timing and exit self-refresh timing */ 152 reg_val = readl(&mctl_ctl->dramtmg8); 153 reg_val &= ~(0xff << 8); 154 reg_val &= ~(0xff << 0); 155 reg_val |= (0x33 << 8); 156 reg_val |= (0x8 << 0); 157 writel(reg_val, &mctl_ctl->dramtmg8); 158 /* Set phy interface time */ 159 reg_val = (0x2 << 24) | (t_rdata_en << 16) | (0x1 << 8) 160 | (wr_latency << 0); 161 /* PHY interface write latency and read latency configure */ 162 writel(reg_val, &mctl_ctl->pitmg0); 163 /* Set phy time PTR0-2 use default */ 164 writel(((tdinit0 << 0) | (tdinit1 << 20)), &mctl_ctl->ptr3); 165 writel(((tdinit2 << 0) | (tdinit3 << 20)), &mctl_ctl->ptr4); 166 /* Set refresh timing */ 167 reg_val = (trefi << 16) | (trfc << 0); 168 writel(reg_val, &mctl_ctl->rfshtmg); 169 } 170 171 static void mctl_set_pir(u32 val) 172 { 173 struct sunxi_mctl_ctl_reg * const mctl_ctl = 174 (struct sunxi_mctl_ctl_reg *)SUNXI_DRAM_CTL0_BASE; 175 176 writel(val, &mctl_ctl->pir); 177 mctl_await_completion(&mctl_ctl->pgsr0, 0x1, 0x1); 178 } 179 180 static void mctl_data_train_cfg(struct dram_para *para) 181 { 182 struct sunxi_mctl_ctl_reg * const mctl_ctl = 183 (struct sunxi_mctl_ctl_reg *)SUNXI_DRAM_CTL0_BASE; 184 185 if (para->rank == 2) 186 clrsetbits_le32(&mctl_ctl->dtcr, 0x3 << 24, 0x3 << 24); 187 else 188 clrsetbits_le32(&mctl_ctl->dtcr, 0x3 << 24, 0x1 << 24); 189 } 190 191 static int mctl_train_dram(struct dram_para *para) 192 { 193 struct sunxi_mctl_ctl_reg * const mctl_ctl = 194 (struct sunxi_mctl_ctl_reg *)SUNXI_DRAM_CTL0_BASE; 195 196 mctl_data_train_cfg(para); 197 mctl_set_pir(0x5f3); 198 199 return ((readl(&mctl_ctl->pgsr0) >> 20) & 0xff) ? -EIO : 0; 200 } 201 202 static int mctl_channel_init(struct dram_para *para) 203 { 204 struct sunxi_mctl_ctl_reg * const mctl_ctl = 205 (struct sunxi_mctl_ctl_reg *)SUNXI_DRAM_CTL0_BASE; 206 struct sunxi_mctl_com_reg * const mctl_com = 207 (struct sunxi_mctl_com_reg *)SUNXI_DRAM_COM_BASE; 208 u32 low_data_lines_status; /* Training status of datalines 0 - 7 */ 209 u32 high_data_lines_status; /* Training status of datalines 8 - 15 */ 210 211 auto_set_timing_para(para); 212 213 /* Disable dram VTC */ 214 clrbits_le32(&mctl_ctl->pgcr0, 0x3f << 0); 215 216 /* Set ODT */ 217 if ((CONFIG_DRAM_CLK > 400) && IS_ENABLED(CONFIG_DRAM_ODT_EN)) { 218 setbits_le32(DXnGCR0(0), 0x3 << 9); 219 setbits_le32(DXnGCR0(1), 0x3 << 9); 220 } else { 221 clrbits_le32(DXnGCR0(0), 0x3 << 9); 222 clrbits_le32(DXnGCR0(1), 0x3 << 9); 223 } 224 225 /* set PLL configuration */ 226 if (CONFIG_DRAM_CLK >= 480) 227 setbits_le32(&mctl_ctl->pllgcr, 0x1 << 18); 228 else 229 setbits_le32(&mctl_ctl->pllgcr, 0x3 << 18); 230 231 /* Auto detect dram config, set 2 rank and 16bit bus-width */ 232 para->cs1 = 0; 233 para->rank = 2; 234 para->bus_width = 16; 235 mctl_set_cr(para); 236 237 /* Open DQS gating */ 238 clrbits_le32(&mctl_ctl->pgcr2, (0x3 << 6)); 239 clrbits_le32(&mctl_ctl->dqsgmr, (0x1 << 8) | (0x7)); 240 241 mctl_data_train_cfg(para); 242 243 /* ZQ calibration */ 244 writel(CONFIG_DRAM_ZQ & 0xff, &mctl_ctl->zqcr1); 245 /* CA calibration */ 246 mctl_set_pir(0x00000003); 247 /* More ZQ calibration */ 248 writel(readl(&mctl_ctl->zqsr0) | 0x10000000, &mctl_ctl->zqcr2); 249 writel((CONFIG_DRAM_ZQ >> 8) & 0xff, &mctl_ctl->zqcr1); 250 251 /* DQS gate training */ 252 if (mctl_train_dram(para) != 0) { 253 low_data_lines_status = (readl(DXnGSR0(0)) >> 24) & 0x03; 254 high_data_lines_status = (readl(DXnGSR0(1)) >> 24) & 0x03; 255 256 if (low_data_lines_status == 0x3) 257 return -EIO; 258 259 /* DRAM has only one rank */ 260 para->rank = 1; 261 mctl_set_cr(para); 262 263 if (low_data_lines_status == high_data_lines_status) 264 goto done; /* 16 bit bus, 1 rank */ 265 266 if (!(low_data_lines_status & high_data_lines_status)) { 267 /* Retry 16 bit bus-width with CS1 set */ 268 para->cs1 = 1; 269 mctl_set_cr(para); 270 if (mctl_train_dram(para) == 0) 271 goto done; 272 } 273 274 /* Try 8 bit bus-width */ 275 writel(0x0, DXnGCR0(1)); /* Disable high DQ */ 276 para->cs1 = 0; 277 para->bus_width = 8; 278 mctl_set_cr(para); 279 if (mctl_train_dram(para) != 0) 280 return -EIO; 281 } 282 done: 283 /* Check the dramc status */ 284 mctl_await_completion(&mctl_ctl->statr, 0x1, 0x1); 285 286 /* Close DQS gating */ 287 setbits_le32(&mctl_ctl->pgcr2, 0x3 << 6); 288 289 /* Enable master access */ 290 writel(0xffffffff, &mctl_com->maer); 291 292 return 0; 293 } 294 295 static void mctl_sys_init(struct dram_para *para) 296 { 297 struct sunxi_ccm_reg * const ccm = 298 (struct sunxi_ccm_reg *)SUNXI_CCM_BASE; 299 struct sunxi_mctl_ctl_reg * const mctl_ctl = 300 (struct sunxi_mctl_ctl_reg *)SUNXI_DRAM_CTL0_BASE; 301 struct sunxi_mctl_com_reg * const mctl_com = 302 (struct sunxi_mctl_com_reg *)SUNXI_DRAM_COM_BASE; 303 304 clrsetbits_le32(&ccm->dram_pll_cfg, CCM_DRAMPLL_CFG_SRC_MASK, 305 CCM_DRAMPLL_CFG_SRC_PLL11); 306 307 clock_set_pll11(CONFIG_DRAM_CLK * 1000000 * DRAM_CLK_MUL, 308 DRAM_SIGMA_DELTA_ENABLE); 309 310 clrsetbits_le32(&ccm->dram_clk_cfg, CCM_DRAMCLK_CFG_DIV_MASK, 311 CCM_DRAMCLK_CFG_DIV(DRAM_CLK_DIV) | 312 CCM_DRAMCLK_CFG_RST | CCM_DRAMCLK_CFG_UPD); 313 mctl_await_completion(&ccm->dram_clk_cfg, CCM_DRAMCLK_CFG_UPD, 0); 314 315 setbits_le32(&ccm->ahb_reset0_cfg, 1 << AHB_RESET_OFFSET_MCTL); 316 setbits_le32(&ccm->ahb_gate0, 1 << AHB_GATE_OFFSET_MCTL); 317 setbits_le32(&ccm->mbus_reset, CCM_MBUS_RESET_RESET); 318 setbits_le32(&ccm->mbus0_clk_cfg, MBUS_CLK_GATE); 319 320 /* Set dram master access priority */ 321 writel(0x0, &mctl_com->mapr); 322 writel(0x0f802f01, &mctl_ctl->sched); 323 writel(0x0000400f, &mctl_ctl->clken); /* normal */ 324 325 udelay(250); 326 } 327 328 unsigned long sunxi_dram_init(void) 329 { 330 struct sunxi_mctl_com_reg * const mctl_com = 331 (struct sunxi_mctl_com_reg *)SUNXI_DRAM_COM_BASE; 332 struct sunxi_mctl_ctl_reg * const mctl_ctl = 333 (struct sunxi_mctl_ctl_reg *)SUNXI_DRAM_CTL0_BASE; 334 335 struct dram_para para = { 336 .cs1 = 0, 337 .bank = 1, 338 .rank = 1, 339 .rows = 15, 340 .bus_width = 16, 341 .page_size = 2048, 342 }; 343 344 mctl_sys_init(¶); 345 346 if (mctl_channel_init(¶) != 0) 347 return 0; 348 349 auto_detect_dram_size(¶); 350 351 /* Enable master software clk */ 352 writel(readl(&mctl_com->swonr) | 0x3ffff, &mctl_com->swonr); 353 354 /* Set DRAM ODT MAP */ 355 if (para.rank == 2) 356 writel(0x00000303, &mctl_ctl->odtmap); 357 else 358 writel(0x00000201, &mctl_ctl->odtmap); 359 360 return para.page_size * (para.bus_width / 8) * 361 (1 << (para.bank + para.rank + para.rows)); 362 } 363