1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * Sun8i platform dram controller init. 4 * 5 * (C) Copyright 2014 Hans de Goede <hdegoede@redhat.com> 6 */ 7 8 /* 9 * Note this code uses a lot of magic hex values, that is because this code 10 * simply replays the init sequence as done by the Allwinner boot0 code, so 11 * we do not know what these values mean. There are no symbolic constants for 12 * these magic values, since we do not know how to name them and making up 13 * names for them is not useful. 14 * 15 * The register-layout of the sunxi_mctl_phy_reg-s looks a lot like the one 16 * found in the TI Keystone2 documentation: 17 * http://www.ti.com/lit/ug/spruhn7a/spruhn7a.pdf 18 * "Table4-2 DDR3 PHY Registers" 19 * This may be used as a (possible) reference for future work / cleanups. 20 */ 21 22 #include <common.h> 23 #include <errno.h> 24 #include <asm/io.h> 25 #include <asm/arch/clock.h> 26 #include <asm/arch/dram.h> 27 #include <asm/arch/prcm.h> 28 29 static const struct dram_para dram_para = { 30 .clock = CONFIG_DRAM_CLK, 31 .type = 3, 32 .zq = CONFIG_DRAM_ZQ, 33 .odt_en = IS_ENABLED(CONFIG_DRAM_ODT_EN), 34 .odt_correction = CONFIG_DRAM_ODT_CORRECTION, 35 .para1 = 0, /* not used (only used when tpr13 bit 31 is set */ 36 .para2 = 0, /* not used (only used when tpr13 bit 31 is set */ 37 .mr0 = 6736, 38 .mr1 = 4, 39 .mr2 = 16, 40 .mr3 = 0, 41 /* tpr0 - 10 contain timing constants or-ed together in u32 vals */ 42 .tpr0 = 0x2ab83def, 43 .tpr1 = 0x18082356, 44 .tpr2 = 0x00034156, 45 .tpr3 = 0x448c5533, 46 .tpr4 = 0x08010d00, 47 .tpr5 = 0x0340b20f, 48 .tpr6 = 0x20d118cc, 49 .tpr7 = 0x14062485, 50 .tpr8 = 0x220d1d52, 51 .tpr9 = 0x1e078c22, 52 .tpr10 = 0x3c, 53 .tpr11 = 0, /* not used */ 54 .tpr12 = 0, /* not used */ 55 .tpr13 = 0x30000, 56 }; 57 58 static void mctl_sys_init(void) 59 { 60 struct sunxi_ccm_reg * const ccm = 61 (struct sunxi_ccm_reg *)SUNXI_CCM_BASE; 62 63 /* enable pll5, note the divide by 2 is deliberate! */ 64 clock_set_pll5(dram_para.clock * 1000000 / 2, 65 dram_para.tpr13 & 0x40000); 66 67 /* deassert ahb mctl reset */ 68 setbits_le32(&ccm->ahb_reset0_cfg, 1 << AHB_RESET_OFFSET_MCTL); 69 70 /* enable ahb mctl clock */ 71 setbits_le32(&ccm->ahb_gate0, 1 << AHB_GATE_OFFSET_MCTL); 72 } 73 74 static void mctl_apply_odt_correction(u32 *reg, int correction) 75 { 76 int val; 77 78 val = (readl(reg) >> 8) & 0xff; 79 val += correction; 80 81 /* clamp */ 82 if (val < 0) 83 val = 0; 84 else if (val > 255) 85 val = 255; 86 87 clrsetbits_le32(reg, 0xff00, val << 8); 88 } 89 90 static void mctl_init(u32 *bus_width) 91 { 92 struct sunxi_ccm_reg * const ccm = 93 (struct sunxi_ccm_reg *)SUNXI_CCM_BASE; 94 struct sunxi_mctl_com_reg * const mctl_com = 95 (struct sunxi_mctl_com_reg *)SUNXI_DRAM_COM_BASE; 96 struct sunxi_mctl_ctl_reg * const mctl_ctl = 97 (struct sunxi_mctl_ctl_reg *)SUNXI_DRAM_CTL0_BASE; 98 struct sunxi_mctl_phy_reg * const mctl_phy = 99 (struct sunxi_mctl_phy_reg *)SUNXI_DRAM_PHY0_BASE; 100 101 if (dram_para.tpr13 & 0x20) 102 writel(0x40b, &mctl_phy->dcr); 103 else 104 writel(0x1000040b, &mctl_phy->dcr); 105 106 if (dram_para.clock >= 480) 107 writel(0x5c000, &mctl_phy->dllgcr); 108 else 109 writel(0xdc000, &mctl_phy->dllgcr); 110 111 writel(0x0a003e3f, &mctl_phy->pgcr0); 112 writel(0x03008421, &mctl_phy->pgcr1); 113 114 writel(dram_para.mr0, &mctl_phy->mr0); 115 writel(dram_para.mr1, &mctl_phy->mr1); 116 writel(dram_para.mr2, &mctl_phy->mr2); 117 writel(dram_para.mr3, &mctl_phy->mr3); 118 119 if (!(dram_para.tpr13 & 0x10000)) { 120 clrsetbits_le32(&mctl_phy->dx0gcr, 0x3800, 0x2000); 121 clrsetbits_le32(&mctl_phy->dx1gcr, 0x3800, 0x2000); 122 } 123 124 /* 125 * All the masking and shifting below converts what I assume are DDR 126 * timing constants from Allwinner dram_para tpr format to the actual 127 * timing registers format. 128 */ 129 130 writel((dram_para.tpr0 & 0x000fffff), &mctl_phy->ptr2); 131 writel((dram_para.tpr1 & 0x1fffffff), &mctl_phy->ptr3); 132 writel((dram_para.tpr0 & 0x3ff00000) >> 2 | 133 (dram_para.tpr2 & 0x0003ffff), &mctl_phy->ptr4); 134 135 writel(dram_para.tpr3, &mctl_phy->dtpr0); 136 writel(dram_para.tpr4, &mctl_phy->dtpr2); 137 138 writel(0x01000081, &mctl_phy->dtcr); 139 140 if (dram_para.clock <= 240 || !dram_para.odt_en) { 141 clrbits_le32(&mctl_phy->dx0gcr, 0x600); 142 clrbits_le32(&mctl_phy->dx1gcr, 0x600); 143 } 144 if (dram_para.clock <= 240) { 145 writel(0, &mctl_phy->odtcr); 146 writel(0, &mctl_ctl->odtmap); 147 } 148 149 writel(((dram_para.tpr5 & 0x0f00) << 12) | 150 ((dram_para.tpr5 & 0x00f8) << 9) | 151 ((dram_para.tpr5 & 0x0007) << 8), 152 &mctl_ctl->rfshctl0); 153 154 writel(((dram_para.tpr5 & 0x0003f000) << 12) | 155 ((dram_para.tpr5 & 0x00fc0000) >> 2) | 156 ((dram_para.tpr5 & 0x3f000000) >> 16) | 157 ((dram_para.tpr6 & 0x0000003f) >> 0), 158 &mctl_ctl->dramtmg0); 159 160 writel(((dram_para.tpr6 & 0x000007c0) << 10) | 161 ((dram_para.tpr6 & 0x0000f800) >> 3) | 162 ((dram_para.tpr6 & 0x003f0000) >> 16), 163 &mctl_ctl->dramtmg1); 164 165 writel(((dram_para.tpr6 & 0x0fc00000) << 2) | 166 ((dram_para.tpr7 & 0x0000001f) << 16) | 167 ((dram_para.tpr7 & 0x000003e0) << 3) | 168 ((dram_para.tpr7 & 0x0000fc00) >> 10), 169 &mctl_ctl->dramtmg2); 170 171 writel(((dram_para.tpr7 & 0x03ff0000) >> 16) | 172 ((dram_para.tpr6 & 0xf0000000) >> 16), 173 &mctl_ctl->dramtmg3); 174 175 writel(((dram_para.tpr7 & 0x3c000000) >> 2 ) | 176 ((dram_para.tpr8 & 0x00000007) << 16) | 177 ((dram_para.tpr8 & 0x00000038) << 5) | 178 ((dram_para.tpr8 & 0x000003c0) >> 6), 179 &mctl_ctl->dramtmg4); 180 181 writel(((dram_para.tpr8 & 0x00003c00) << 14) | 182 ((dram_para.tpr8 & 0x0003c000) << 2) | 183 ((dram_para.tpr8 & 0x00fc0000) >> 10) | 184 ((dram_para.tpr8 & 0x0f000000) >> 24), 185 &mctl_ctl->dramtmg5); 186 187 writel(0x00000008, &mctl_ctl->dramtmg8); 188 189 writel(((dram_para.tpr8 & 0xf0000000) >> 4) | 190 ((dram_para.tpr9 & 0x00007c00) << 6) | 191 ((dram_para.tpr9 & 0x000003e0) << 3) | 192 ((dram_para.tpr9 & 0x0000001f) >> 0), 193 &mctl_ctl->pitmg0); 194 195 setbits_le32(&mctl_ctl->pitmg1, 0x80000); 196 197 writel(((dram_para.tpr9 & 0x003f8000) << 9) | 0x2001, 198 &mctl_ctl->sched); 199 200 writel((dram_para.mr0 << 16) | dram_para.mr1, &mctl_ctl->init3); 201 writel((dram_para.mr2 << 16) | dram_para.mr3, &mctl_ctl->init4); 202 203 writel(0x00000000, &mctl_ctl->pimisc); 204 writel(0x80000000, &mctl_ctl->upd0); 205 206 writel(((dram_para.tpr9 & 0xffc00000) >> 22) | 207 ((dram_para.tpr10 & 0x00000fff) << 16), 208 &mctl_ctl->rfshtmg); 209 210 if (dram_para.tpr13 & 0x20) 211 writel(0x01040001, &mctl_ctl->mstr); 212 else 213 writel(0x01040401, &mctl_ctl->mstr); 214 215 if (!(dram_para.tpr13 & 0x20000)) { 216 writel(0x00000002, &mctl_ctl->pwrctl); 217 writel(0x00008001, &mctl_ctl->pwrtmg); 218 } 219 220 writel(0x00000001, &mctl_ctl->rfshctl3); 221 writel(0x00000001, &mctl_ctl->pimisc); 222 223 /* deassert dram_clk_cfg reset */ 224 setbits_le32(&ccm->dram_clk_cfg, CCM_DRAMCLK_CFG_RST); 225 226 setbits_le32(&mctl_com->ccr, 0x80000); 227 228 /* zq stuff */ 229 writel((dram_para.zq >> 8) & 0xff, &mctl_phy->zqcr1); 230 231 writel(0x00000003, &mctl_phy->pir); 232 udelay(10); 233 mctl_await_completion(&mctl_phy->pgsr0, 0x09, 0x09); 234 235 writel(readl(&mctl_phy->zqsr0) | 0x10000000, &mctl_phy->zqcr2); 236 writel(dram_para.zq & 0xff, &mctl_phy->zqcr1); 237 238 /* A23-v1.0 SDK uses 0xfdf3, A23-v2.0 SDK uses 0x5f3 */ 239 writel(0x000005f3, &mctl_phy->pir); 240 udelay(10); 241 mctl_await_completion(&mctl_phy->pgsr0, 0x03, 0x03); 242 243 if (readl(&mctl_phy->dx1gsr0) & 0x1000000) { 244 *bus_width = 8; 245 writel(0, &mctl_phy->dx1gcr); 246 writel(dram_para.zq & 0xff, &mctl_phy->zqcr1); 247 writel(0x5f3, &mctl_phy->pir); 248 udelay(10000); 249 setbits_le32(&mctl_ctl->mstr, 0x1000); 250 } else 251 *bus_width = 16; 252 253 if (dram_para.odt_correction) { 254 mctl_apply_odt_correction(&mctl_phy->dx0lcdlr1, 255 dram_para.odt_correction); 256 mctl_apply_odt_correction(&mctl_phy->dx1lcdlr1, 257 dram_para.odt_correction); 258 } 259 260 mctl_await_completion(&mctl_ctl->statr, 0x01, 0x01); 261 262 writel(0x08003e3f, &mctl_phy->pgcr0); 263 writel(0x00000000, &mctl_ctl->rfshctl3); 264 } 265 266 unsigned long sunxi_dram_init(void) 267 { 268 struct sunxi_mctl_com_reg * const mctl_com = 269 (struct sunxi_mctl_com_reg *)SUNXI_DRAM_COM_BASE; 270 const u32 columns = 13; 271 u32 bus, bus_width, offset, page_size, rows; 272 273 mctl_sys_init(); 274 mctl_init(&bus_width); 275 276 if (bus_width == 16) { 277 page_size = 8; 278 bus = 1; 279 } else { 280 page_size = 7; 281 bus = 0; 282 } 283 284 if (!(dram_para.tpr13 & 0x80000000)) { 285 /* Detect and set rows */ 286 writel(0x000310f4 | MCTL_CR_PAGE_SIZE(page_size), 287 &mctl_com->cr); 288 setbits_le32(&mctl_com->swonr, 0x0003ffff); 289 for (rows = 11; rows < 16; rows++) { 290 offset = 1 << (rows + columns + bus); 291 if (mctl_mem_matches(offset)) 292 break; 293 } 294 clrsetbits_le32(&mctl_com->cr, MCTL_CR_ROW_MASK, 295 MCTL_CR_ROW(rows)); 296 } else { 297 rows = (dram_para.para1 >> 16) & 0xff; 298 writel(((dram_para.para2 & 0x000000f0) << 11) | 299 ((rows - 1) << 4) | 300 ((dram_para.para1 & 0x0f000000) >> 22) | 301 0x31000 | MCTL_CR_PAGE_SIZE(page_size), 302 &mctl_com->cr); 303 setbits_le32(&mctl_com->swonr, 0x0003ffff); 304 } 305 306 /* Setup DRAM master priority? If this is left out things still work */ 307 writel(0x00000008, &mctl_com->mcr0_0); 308 writel(0x0001000d, &mctl_com->mcr1_0); 309 writel(0x00000004, &mctl_com->mcr0_1); 310 writel(0x00000080, &mctl_com->mcr1_1); 311 writel(0x00000004, &mctl_com->mcr0_2); 312 writel(0x00000019, &mctl_com->mcr1_2); 313 writel(0x00000004, &mctl_com->mcr0_3); 314 writel(0x00000080, &mctl_com->mcr1_3); 315 writel(0x00000004, &mctl_com->mcr0_4); 316 writel(0x01010040, &mctl_com->mcr1_4); 317 writel(0x00000004, &mctl_com->mcr0_5); 318 writel(0x0001002f, &mctl_com->mcr1_5); 319 writel(0x00000004, &mctl_com->mcr0_6); 320 writel(0x00010020, &mctl_com->mcr1_6); 321 writel(0x00000004, &mctl_com->mcr0_7); 322 writel(0x00010020, &mctl_com->mcr1_7); 323 writel(0x00000008, &mctl_com->mcr0_8); 324 writel(0x00000001, &mctl_com->mcr1_8); 325 writel(0x00000008, &mctl_com->mcr0_9); 326 writel(0x00000005, &mctl_com->mcr1_9); 327 writel(0x00000008, &mctl_com->mcr0_10); 328 writel(0x00000003, &mctl_com->mcr1_10); 329 writel(0x00000008, &mctl_com->mcr0_11); 330 writel(0x00000005, &mctl_com->mcr1_11); 331 writel(0x00000008, &mctl_com->mcr0_12); 332 writel(0x00000003, &mctl_com->mcr1_12); 333 writel(0x00000008, &mctl_com->mcr0_13); 334 writel(0x00000004, &mctl_com->mcr1_13); 335 writel(0x00000008, &mctl_com->mcr0_14); 336 writel(0x00000002, &mctl_com->mcr1_14); 337 writel(0x00000008, &mctl_com->mcr0_15); 338 writel(0x00000003, &mctl_com->mcr1_15); 339 writel(0x00010138, &mctl_com->bwcr); 340 341 return 1 << (rows + columns + bus); 342 } 343