1 /* 2 * Sun6i platform dram controller init. 3 * 4 * (C) Copyright 2007-2012 5 * Allwinner Technology Co., Ltd. <www.allwinnertech.com> 6 * Berg Xing <bergxing@allwinnertech.com> 7 * Tom Cubie <tangliang@allwinnertech.com> 8 * 9 * (C) Copyright 2014 Hans de Goede <hdegoede@redhat.com> 10 * 11 * SPDX-License-Identifier: GPL-2.0+ 12 */ 13 #include <common.h> 14 #include <errno.h> 15 #include <asm/io.h> 16 #include <asm/arch/clock.h> 17 #include <asm/arch/dram.h> 18 #include <asm/arch/prcm.h> 19 20 #define DRAM_CLK (CONFIG_DRAM_CLK * 1000000) 21 22 struct dram_sun6i_para { 23 u8 bus_width; 24 u8 chan; 25 u8 rank; 26 u8 rows; 27 u16 page_size; 28 }; 29 30 static void mctl_sys_init(void) 31 { 32 struct sunxi_ccm_reg * const ccm = 33 (struct sunxi_ccm_reg *)SUNXI_CCM_BASE; 34 const int dram_clk_div = 2; 35 36 clock_set_pll5(DRAM_CLK * dram_clk_div, false); 37 38 clrsetbits_le32(&ccm->dram_clk_cfg, CCM_DRAMCLK_CFG_DIV0_MASK, 39 CCM_DRAMCLK_CFG_DIV0(dram_clk_div) | CCM_DRAMCLK_CFG_RST | 40 CCM_DRAMCLK_CFG_UPD); 41 mctl_await_completion(&ccm->dram_clk_cfg, CCM_DRAMCLK_CFG_UPD, 0); 42 43 writel(MDFS_CLK_DEFAULT, &ccm->mdfs_clk_cfg); 44 45 /* deassert mctl reset */ 46 setbits_le32(&ccm->ahb_reset0_cfg, 1 << AHB_RESET_OFFSET_MCTL); 47 48 /* enable mctl clock */ 49 setbits_le32(&ccm->ahb_gate0, 1 << AHB_GATE_OFFSET_MCTL); 50 } 51 52 static void mctl_dll_init(int ch_index, struct dram_sun6i_para *para) 53 { 54 struct sunxi_mctl_phy_reg *mctl_phy; 55 56 if (ch_index == 0) 57 mctl_phy = (struct sunxi_mctl_phy_reg *)SUNXI_DRAM_PHY0_BASE; 58 else 59 mctl_phy = (struct sunxi_mctl_phy_reg *)SUNXI_DRAM_PHY1_BASE; 60 61 /* disable + reset dlls */ 62 writel(MCTL_DLLCR_DISABLE, &mctl_phy->acdllcr); 63 writel(MCTL_DLLCR_DISABLE, &mctl_phy->dx0dllcr); 64 writel(MCTL_DLLCR_DISABLE, &mctl_phy->dx1dllcr); 65 if (para->bus_width == 32) { 66 writel(MCTL_DLLCR_DISABLE, &mctl_phy->dx2dllcr); 67 writel(MCTL_DLLCR_DISABLE, &mctl_phy->dx3dllcr); 68 } 69 udelay(2); 70 71 /* enable + reset dlls */ 72 writel(0, &mctl_phy->acdllcr); 73 writel(0, &mctl_phy->dx0dllcr); 74 writel(0, &mctl_phy->dx1dllcr); 75 if (para->bus_width == 32) { 76 writel(0, &mctl_phy->dx2dllcr); 77 writel(0, &mctl_phy->dx3dllcr); 78 } 79 udelay(22); 80 81 /* enable and release reset of dlls */ 82 writel(MCTL_DLLCR_NRESET, &mctl_phy->acdllcr); 83 writel(MCTL_DLLCR_NRESET, &mctl_phy->dx0dllcr); 84 writel(MCTL_DLLCR_NRESET, &mctl_phy->dx1dllcr); 85 if (para->bus_width == 32) { 86 writel(MCTL_DLLCR_NRESET, &mctl_phy->dx2dllcr); 87 writel(MCTL_DLLCR_NRESET, &mctl_phy->dx3dllcr); 88 } 89 udelay(22); 90 } 91 92 static bool mctl_rank_detect(u32 *gsr0, int rank) 93 { 94 const u32 done = MCTL_DX_GSR0_RANK0_TRAIN_DONE << rank; 95 const u32 err = MCTL_DX_GSR0_RANK0_TRAIN_ERR << rank; 96 97 mctl_await_completion(gsr0, done, done); 98 mctl_await_completion(gsr0 + 0x10, done, done); 99 100 return !(readl(gsr0) & err) && !(readl(gsr0 + 0x10) & err); 101 } 102 103 static void mctl_channel_init(int ch_index, struct dram_sun6i_para *para) 104 { 105 struct sunxi_mctl_com_reg * const mctl_com = 106 (struct sunxi_mctl_com_reg *)SUNXI_DRAM_COM_BASE; 107 struct sunxi_mctl_ctl_reg *mctl_ctl; 108 struct sunxi_mctl_phy_reg *mctl_phy; 109 110 if (ch_index == 0) { 111 mctl_ctl = (struct sunxi_mctl_ctl_reg *)SUNXI_DRAM_CTL0_BASE; 112 mctl_phy = (struct sunxi_mctl_phy_reg *)SUNXI_DRAM_PHY0_BASE; 113 } else { 114 mctl_ctl = (struct sunxi_mctl_ctl_reg *)SUNXI_DRAM_CTL1_BASE; 115 mctl_phy = (struct sunxi_mctl_phy_reg *)SUNXI_DRAM_PHY1_BASE; 116 } 117 118 writel(MCTL_MCMD_NOP, &mctl_ctl->mcmd); 119 mctl_await_completion(&mctl_ctl->mcmd, MCTL_MCMD_BUSY, 0); 120 121 /* PHY initialization */ 122 writel(MCTL_PGCR, &mctl_phy->pgcr); 123 writel(MCTL_MR0, &mctl_phy->mr0); 124 writel(MCTL_MR1, &mctl_phy->mr1); 125 writel(MCTL_MR2, &mctl_phy->mr2); 126 writel(MCTL_MR3, &mctl_phy->mr3); 127 128 writel((MCTL_TITMSRST << 18) | (MCTL_TDLLLOCK << 6) | MCTL_TDLLSRST, 129 &mctl_phy->ptr0); 130 131 writel((MCTL_TDINIT1 << 19) | MCTL_TDINIT0, &mctl_phy->ptr1); 132 writel((MCTL_TDINIT3 << 17) | MCTL_TDINIT2, &mctl_phy->ptr2); 133 134 writel((MCTL_TCCD << 31) | (MCTL_TRC << 25) | (MCTL_TRRD << 21) | 135 (MCTL_TRAS << 16) | (MCTL_TRCD << 12) | (MCTL_TRP << 8) | 136 (MCTL_TWTR << 5) | (MCTL_TRTP << 2) | (MCTL_TMRD << 0), 137 &mctl_phy->dtpr0); 138 139 writel((MCTL_TDQSCKMAX << 27) | (MCTL_TDQSCK << 24) | 140 (MCTL_TRFC << 16) | (MCTL_TRTODT << 11) | 141 ((MCTL_TMOD - 12) << 9) | (MCTL_TFAW << 3) | (0 << 2) | 142 (MCTL_TAOND << 0), &mctl_phy->dtpr1); 143 144 writel((MCTL_TDLLK << 19) | (MCTL_TCKE << 15) | (MCTL_TXPDLL << 10) | 145 (MCTL_TEXSR << 0), &mctl_phy->dtpr2); 146 147 writel(1, &mctl_ctl->dfitphyupdtype0); 148 writel(MCTL_DCR_DDR3, &mctl_phy->dcr); 149 writel(MCTL_DSGCR, &mctl_phy->dsgcr); 150 writel(MCTL_DXCCR, &mctl_phy->dxccr); 151 writel(MCTL_DX_GCR | MCTL_DX_GCR_EN, &mctl_phy->dx0gcr); 152 writel(MCTL_DX_GCR | MCTL_DX_GCR_EN, &mctl_phy->dx1gcr); 153 writel(MCTL_DX_GCR | MCTL_DX_GCR_EN, &mctl_phy->dx2gcr); 154 writel(MCTL_DX_GCR | MCTL_DX_GCR_EN, &mctl_phy->dx3gcr); 155 156 mctl_await_completion(&mctl_phy->pgsr, 0x03, 0x03); 157 158 writel(CONFIG_DRAM_ZQ, &mctl_phy->zq0cr1); 159 160 setbits_le32(&mctl_phy->pir, MCTL_PIR_CLEAR_STATUS); 161 writel(MCTL_PIR_STEP1, &mctl_phy->pir); 162 udelay(10); 163 mctl_await_completion(&mctl_phy->pgsr, 0x1f, 0x1f); 164 165 /* rank detect */ 166 if (!mctl_rank_detect(&mctl_phy->dx0gsr0, 1)) { 167 para->rank = 1; 168 clrbits_le32(&mctl_phy->pgcr, MCTL_PGCR_RANK); 169 } 170 171 /* 172 * channel detect, check channel 1 dx0 and dx1 have rank 0, if not 173 * assume nothing is connected to channel 1. 174 */ 175 if (ch_index == 1 && !mctl_rank_detect(&mctl_phy->dx0gsr0, 0)) { 176 para->chan = 1; 177 clrbits_le32(&mctl_com->ccr, MCTL_CCR_CH1_CLK_EN); 178 return; 179 } 180 181 /* bus width detect, if dx2 and dx3 don't have rank 0, assume 16 bit */ 182 if (!mctl_rank_detect(&mctl_phy->dx2gsr0, 0)) { 183 para->bus_width = 16; 184 para->page_size = 2048; 185 setbits_le32(&mctl_phy->dx2dllcr, MCTL_DLLCR_DISABLE); 186 setbits_le32(&mctl_phy->dx3dllcr, MCTL_DLLCR_DISABLE); 187 clrbits_le32(&mctl_phy->dx2gcr, MCTL_DX_GCR_EN); 188 clrbits_le32(&mctl_phy->dx3gcr, MCTL_DX_GCR_EN); 189 } 190 191 setbits_le32(&mctl_phy->pir, MCTL_PIR_CLEAR_STATUS); 192 writel(MCTL_PIR_STEP2, &mctl_phy->pir); 193 udelay(10); 194 mctl_await_completion(&mctl_phy->pgsr, 0x11, 0x11); 195 196 if (readl(&mctl_phy->pgsr) & MCTL_PGSR_TRAIN_ERR_MASK) 197 panic("Training error initialising DRAM\n"); 198 199 /* Move to configure state */ 200 writel(MCTL_SCTL_CONFIG, &mctl_ctl->sctl); 201 mctl_await_completion(&mctl_ctl->sstat, 0x07, 0x01); 202 203 /* Set number of clks per micro-second */ 204 writel(DRAM_CLK / 1000000, &mctl_ctl->togcnt1u); 205 /* Set number of clks per 100 nano-seconds */ 206 writel(DRAM_CLK / 10000000, &mctl_ctl->togcnt100n); 207 /* Set memory timing registers */ 208 writel(MCTL_TREFI, &mctl_ctl->trefi); 209 writel(MCTL_TMRD, &mctl_ctl->tmrd); 210 writel(MCTL_TRFC, &mctl_ctl->trfc); 211 writel((MCTL_TPREA << 16) | MCTL_TRP, &mctl_ctl->trp); 212 writel(MCTL_TRTW, &mctl_ctl->trtw); 213 writel(MCTL_TAL, &mctl_ctl->tal); 214 writel(MCTL_TCL, &mctl_ctl->tcl); 215 writel(MCTL_TCWL, &mctl_ctl->tcwl); 216 writel(MCTL_TRAS, &mctl_ctl->tras); 217 writel(MCTL_TRC, &mctl_ctl->trc); 218 writel(MCTL_TRCD, &mctl_ctl->trcd); 219 writel(MCTL_TRRD, &mctl_ctl->trrd); 220 writel(MCTL_TRTP, &mctl_ctl->trtp); 221 writel(MCTL_TWR, &mctl_ctl->twr); 222 writel(MCTL_TWTR, &mctl_ctl->twtr); 223 writel(MCTL_TEXSR, &mctl_ctl->texsr); 224 writel(MCTL_TXP, &mctl_ctl->txp); 225 writel(MCTL_TXPDLL, &mctl_ctl->txpdll); 226 writel(MCTL_TZQCS, &mctl_ctl->tzqcs); 227 writel(MCTL_TZQCSI, &mctl_ctl->tzqcsi); 228 writel(MCTL_TDQS, &mctl_ctl->tdqs); 229 writel(MCTL_TCKSRE, &mctl_ctl->tcksre); 230 writel(MCTL_TCKSRX, &mctl_ctl->tcksrx); 231 writel(MCTL_TCKE, &mctl_ctl->tcke); 232 writel(MCTL_TMOD, &mctl_ctl->tmod); 233 writel(MCTL_TRSTL, &mctl_ctl->trstl); 234 writel(MCTL_TZQCL, &mctl_ctl->tzqcl); 235 writel(MCTL_TMRR, &mctl_ctl->tmrr); 236 writel(MCTL_TCKESR, &mctl_ctl->tckesr); 237 writel(MCTL_TDPD, &mctl_ctl->tdpd); 238 239 /* Unknown magic performed by boot0 */ 240 setbits_le32(&mctl_ctl->dfiodtcfg, 1 << 3); 241 clrbits_le32(&mctl_ctl->dfiodtcfg1, 0x1f); 242 243 /* Select 16/32-bits mode for MCTL */ 244 if (para->bus_width == 16) 245 setbits_le32(&mctl_ctl->ppcfg, 1); 246 247 /* Set DFI timing registers */ 248 writel(MCTL_TCWL, &mctl_ctl->dfitphywrl); 249 writel(MCTL_TCL - 1, &mctl_ctl->dfitrdden); 250 writel(MCTL_DFITPHYRDL, &mctl_ctl->dfitphyrdl); 251 writel(MCTL_DFISTCFG0, &mctl_ctl->dfistcfg0); 252 253 writel(MCTL_MCFG_DDR3, &mctl_ctl->mcfg); 254 255 /* DFI update configuration register */ 256 writel(MCTL_DFIUPDCFG_UPD, &mctl_ctl->dfiupdcfg); 257 258 /* Move to access state */ 259 writel(MCTL_SCTL_ACCESS, &mctl_ctl->sctl); 260 mctl_await_completion(&mctl_ctl->sstat, 0x07, 0x03); 261 } 262 263 static void mctl_com_init(struct dram_sun6i_para *para) 264 { 265 struct sunxi_mctl_com_reg * const mctl_com = 266 (struct sunxi_mctl_com_reg *)SUNXI_DRAM_COM_BASE; 267 struct sunxi_mctl_phy_reg * const mctl_phy1 = 268 (struct sunxi_mctl_phy_reg *)SUNXI_DRAM_PHY1_BASE; 269 struct sunxi_prcm_reg * const prcm = 270 (struct sunxi_prcm_reg *)SUNXI_PRCM_BASE; 271 272 writel(MCTL_CR_UNKNOWN | MCTL_CR_CHANNEL(para->chan) | MCTL_CR_DDR3 | 273 ((para->bus_width == 32) ? MCTL_CR_BUSW32 : MCTL_CR_BUSW16) | 274 MCTL_CR_PAGE_SIZE(para->page_size) | MCTL_CR_ROW(para->rows) | 275 MCTL_CR_BANK(1) | MCTL_CR_RANK(para->rank), &mctl_com->cr); 276 277 /* Unknown magic performed by boot0 */ 278 setbits_le32(&mctl_com->dbgcr, (1 << 6)); 279 280 if (para->chan == 1) { 281 /* Shutdown channel 1 */ 282 setbits_le32(&mctl_phy1->aciocr, MCTL_ACIOCR_DISABLE); 283 setbits_le32(&mctl_phy1->dxccr, MCTL_DXCCR_DISABLE); 284 clrbits_le32(&mctl_phy1->dsgcr, MCTL_DSGCR_ENABLE); 285 /* 286 * CH0 ?? this is what boot0 does. Leave as is until we can 287 * confirm this. 288 */ 289 setbits_le32(&prcm->vdd_sys_pwroff, 290 PRCM_VDD_SYS_DRAM_CH0_PAD_HOLD_PWROFF); 291 } 292 } 293 294 static void mctl_port_cfg(void) 295 { 296 struct sunxi_mctl_com_reg * const mctl_com = 297 (struct sunxi_mctl_com_reg *)SUNXI_DRAM_COM_BASE; 298 struct sunxi_ccm_reg * const ccm = 299 (struct sunxi_ccm_reg *)SUNXI_CCM_BASE; 300 301 /* enable DRAM AXI clock for CPU access */ 302 setbits_le32(&ccm->axi_gate, 1 << AXI_GATE_OFFSET_DRAM); 303 304 /* Bunch of magic writes performed by boot0 */ 305 writel(0x00400302, &mctl_com->rmcr[0]); 306 writel(0x01000307, &mctl_com->rmcr[1]); 307 writel(0x00400302, &mctl_com->rmcr[2]); 308 writel(0x01000307, &mctl_com->rmcr[3]); 309 writel(0x01000307, &mctl_com->rmcr[4]); 310 writel(0x01000303, &mctl_com->rmcr[6]); 311 writel(0x01000303, &mctl_com->mmcr[0]); 312 writel(0x00400310, &mctl_com->mmcr[1]); 313 writel(0x01000307, &mctl_com->mmcr[2]); 314 writel(0x01000303, &mctl_com->mmcr[3]); 315 writel(0x01800303, &mctl_com->mmcr[4]); 316 writel(0x01800303, &mctl_com->mmcr[5]); 317 writel(0x01800303, &mctl_com->mmcr[6]); 318 writel(0x01800303, &mctl_com->mmcr[7]); 319 writel(0x01000303, &mctl_com->mmcr[8]); 320 writel(0x00000002, &mctl_com->mmcr[15]); 321 writel(0x00000310, &mctl_com->mbagcr[0]); 322 writel(0x00400310, &mctl_com->mbagcr[1]); 323 writel(0x00400310, &mctl_com->mbagcr[2]); 324 writel(0x00000307, &mctl_com->mbagcr[3]); 325 writel(0x00000317, &mctl_com->mbagcr[4]); 326 writel(0x00000307, &mctl_com->mbagcr[5]); 327 } 328 329 unsigned long sunxi_dram_init(void) 330 { 331 struct sunxi_mctl_com_reg * const mctl_com = 332 (struct sunxi_mctl_com_reg *)SUNXI_DRAM_COM_BASE; 333 u32 offset; 334 int bank, bus, columns; 335 336 /* Set initial parameters, these get modified by the autodetect code */ 337 struct dram_sun6i_para para = { 338 .bus_width = 32, 339 .chan = 2, 340 .rank = 2, 341 .page_size = 4096, 342 .rows = 16, 343 }; 344 345 /* A31s only has one channel */ 346 if (sunxi_get_ss_bonding_id() == SUNXI_SS_BOND_ID_A31S) 347 para.chan = 1; 348 349 mctl_sys_init(); 350 351 mctl_dll_init(0, ¶); 352 setbits_le32(&mctl_com->ccr, MCTL_CCR_CH0_CLK_EN); 353 354 if (para.chan == 2) { 355 mctl_dll_init(1, ¶); 356 setbits_le32(&mctl_com->ccr, MCTL_CCR_CH1_CLK_EN); 357 } 358 359 setbits_le32(&mctl_com->ccr, MCTL_CCR_MASTER_CLK_EN); 360 361 mctl_channel_init(0, ¶); 362 if (para.chan == 2) 363 mctl_channel_init(1, ¶); 364 365 mctl_com_init(¶); 366 mctl_port_cfg(); 367 368 /* 369 * Change to 1 ch / sequence / 8192 byte pages / 16 rows / 370 * 8 bit banks / 1 rank mode. 371 */ 372 clrsetbits_le32(&mctl_com->cr, 373 MCTL_CR_CHANNEL_MASK | MCTL_CR_PAGE_SIZE_MASK | 374 MCTL_CR_ROW_MASK | MCTL_CR_BANK_MASK | MCTL_CR_RANK_MASK, 375 MCTL_CR_CHANNEL(1) | MCTL_CR_SEQUENCE | 376 MCTL_CR_PAGE_SIZE(8192) | MCTL_CR_ROW(16) | 377 MCTL_CR_BANK(1) | MCTL_CR_RANK(1)); 378 379 /* Detect and set page size */ 380 for (columns = 7; columns < 20; columns++) { 381 if (mctl_mem_matches(1 << columns)) 382 break; 383 } 384 bus = (para.bus_width == 32) ? 2 : 1; 385 columns -= bus; 386 para.page_size = (1 << columns) * (bus << 1); 387 clrsetbits_le32(&mctl_com->cr, MCTL_CR_PAGE_SIZE_MASK, 388 MCTL_CR_PAGE_SIZE(para.page_size)); 389 390 /* Detect and set rows */ 391 for (para.rows = 11; para.rows < 16; para.rows++) { 392 offset = 1 << (para.rows + columns + bus); 393 if (mctl_mem_matches(offset)) 394 break; 395 } 396 clrsetbits_le32(&mctl_com->cr, MCTL_CR_ROW_MASK, 397 MCTL_CR_ROW(para.rows)); 398 399 /* Detect bank size */ 400 offset = 1 << (para.rows + columns + bus + 2); 401 bank = mctl_mem_matches(offset) ? 0 : 1; 402 403 /* Restore interleave, chan and rank values, set bank size */ 404 clrsetbits_le32(&mctl_com->cr, 405 MCTL_CR_CHANNEL_MASK | MCTL_CR_SEQUENCE | 406 MCTL_CR_BANK_MASK | MCTL_CR_RANK_MASK, 407 MCTL_CR_CHANNEL(para.chan) | MCTL_CR_BANK(bank) | 408 MCTL_CR_RANK(para.rank)); 409 410 return 1 << (para.rank + para.rows + bank + columns + para.chan + bus); 411 } 412